Abstract: A method includes depositing a silicon layer on a plurality of strips. The silicon layer is etched back to remove top portions of the silicon layer, and to expose some portions of the plurality of strips. Some bottom portions of the silicon layer at bottoms of trenches between the plurality of strips remain after the etching back. A germanium layer is selectively grown from remaining portions of the silicon layer, and exposed portions of the plurality of strips remain exposed after the germanium layer is selectively grown.

Abstract: A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

Abstract: According to one embodiment, a method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes three steps of a providing step, a bonding step, and a thinning step. In the providing step, a mitigation layer that mitigates warping of the device substrate being thinned by grinding is provided on the supporting substrate. In the bonding step, the device substrate is bonded to the supporting substrate on which the mitigation layer is provided. In the thinning step, the device substrate supported by the supporting substrate is thinned by grinding.

Abstract: A die is packaged by flip-chip mounting the die with the active side facing a low loss substrate. A ground plane is coupled to the active side of the die by vias through the low loss substrate. The ground plane is positioned to concentrate high frequency electromagnetic fields in the low loss substrate. A tuning height can be adjusted to tune the center frequency of a circuit in the die.

Abstract: Provided are a semiconductor device and a method for fabricating the same. The method for fabricating a semiconductor device comprises, providing an active fin and a field insulating film including a first trench disposed on the active fin; forming a second trench through performing first etching of the field insulating film that is disposed on side walls and a lower portion of the first trench; forming a first region and a second region in the field insulating film through performing second etching of the field insulating film that is disposed on side walls and a lower portion of the second trench, the first region is disposed adjacent to the active fin and has a first thickness, and the second region is disposed spaced apart from the active fin as compared with the first region and has a second thickness that is thicker than the first thickness; and forming a gate structure on the active fin and the field insulating film.

Abstract: This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.

Abstract: A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device.

Abstract: A semiconductor device includes a first well formed in a predetermined region of a semiconductor substrate, a second well formed in a predetermined region in the first well, and a third well formed in the first well with the third well being spaced apart from the second well at a predetermined distance. A multiple well of the semiconductor substrate, the first well, the second well, the first well, and the third well, which are sequentially disposed, is formed. Accordingly, a breakdown voltage can be increased and a leakage current can be reduced. It is therefore possible to prevent the drop of an erase voltage and to reduce the error of an erase operation.

Abstract: Provided is a semiconductor and a method for forming the same. The method includes forming a buried insulating layer locally in a substrate. The substrate is etched to form an opening exposing the buried insulating layer, and a silicon pattern spaced in at least one direction from the substrate is formed on the buried insulating layer. A first insulating layer is formed to enclose the silicon pattern.

Abstract: A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.

Abstract: A light receiving device 1 includes a support substrate 12 provided thereon with a photodetector 11 including a photodetecting portion 111 and a base substrate 112 on which the photodetecting portion 111 is placed; and a transparent substrate 13 disposed so as to oppose the face of the support substrate 12 on which the photodetector 11 is provided. Between the support substrate 12 and the transparent substrate 13, a frame portion 14 is provided so as to surround the photodetector 11. The frame portion 14 is a photo-curing adhesive, and directly adhered to the transparent substrate 13 and the support substrate 12. Such structure provides a light receiving device capable of exhibiting the desired performance, and a method of manufacturing such light receiving device can also be provided.

Abstract: A method of forming a passivation layer comprises contacting at least one surface of a wide band-gap semiconductor material with a passivating agent comprising an alkali hypochloride to form the passivation layer on said at least one surface. The passivation layer may be encapsulated with a layer of encapsulation material.

Abstract: A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device.

Abstract: Provided is a semiconductor and a method for forming the same. The method includes forming a buried insulating layer locally in a substrate. The substrate is etched to form an opening exposing the buried insulating layer, and a silicon pattern spaced in at least one direction from the substrate is formed on the buried insulating layer. A first insulating layer is formed to enclose the silicon pattern.

Abstract: A semiconductor device includes a semiconductor substrate having an active region which includes a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate to expose side surfaces of a portion of the active region including the gate forming zone, such that the portion of the active region including the gate forming zone constitutes a fin pattern; a silicon epitaxial layer formed on the active region including the fin pattern; and a gate formed to cover the fin pattern on which the silicon epitaxial layer is formed.

Abstract: Embodiments relate to a passivation fabricating method. In the passivation fabricating method according to embodiments, a first oxide film may be formed by repeating deposition and etching of an oxide film on a silicon substrate in which an upper metal pad may be formed and a second oxide film may be formed by performing only deposition on the first oxide film. A thickness of the first oxide film may be set to be above 5 k?. A first passivation layer may be formed by planarizing the first and second oxide films. In the planarizing process, a thickness of the first passivation layer may be 4 k?. A second passivation layer of a nitride film may be formed on the first passivation layer and the first and second passivations may be selectively etched so as to expose the upper metal pad.

Abstract: A semiconductor device includes a first well formed in a predetermined region of a semiconductor substrate, a second well formed in a predetermined region in the first well, and a third well formed in the first well with the third well being spaced apart from the second well at a predetermined distance. A multiple well of the semiconductor substrate, the first well, the second well, the first well, and the third well, which are sequentially disposed, is formed. Accordingly, a breakdown voltage can be increased and a leakage current can be reduced. It is therefore possible to prevent the drop of an erase voltage and to reduce the error of an erase operation.

Abstract: A semiconductor structure and its method of fabrication utilize a semiconductor substrate having an active region mesa surrounded by an isolation trench. A first isolation region having a first stress is located in the isolation trench. A second isolation region having a second stress different than the first stress is also located in the isolation trench. The first isolation region and the second isolation region are sized and positioned to rotationally shear stress the active region mesa.

Abstract: A method of forming a semiconductor structure is provided. The method includes providing a substrate and forming a mask layer on the substrate. Next, dielectric isolations are formed in the mask layer and the substrate, wherein the dielectric isolations extend above the substrate. Then, the mask layer is removed to expose a portion of the substrate, and a dielectric layer is formed on the exposed portion of the substrate. Subsequently, a first conductive layer is formed on the dielectric layer, and a portion of the dielectric isolation is removed, wherein a top surface of the remaining dielectric isolation is lower than a top surface of the first conductive layer. Moreover, a conformal layer is formed over the substrate, and a second conductive layer is formed on the conformal layer.

Abstract: Certain modifications and additions to the prior art short passivation technique have lead to improvements in the low light voltage of solar cells which are made using the improved passivation technique. Examples of the modifications include: 1) reducing the voltage bias on the cell while increasing the time of application of the voltage; 2) reversing the polarity of the voltage bias on the devices; 3) alternating pulsing between forward and reverse polarity bias; or 4) applying light energy simultaneously with an electrical bias voltage.

Abstract: The present invention provides improvements to the use of silyating agents in semiconductor processing. More particularly, the silyating agents may be provided in combination with a substantially non-flammable ether, so that the combination is substantially non-flammable. Additionally, the silyating agent may be utilized in vapor form, or applied in conjunction with the electromagnetic radiation. Each of these embodiments can enhance the usability of the silyating agent, i.e., by rendering the silyating agent more safe, more easily utilized in a variety of processing equipment and/or by enhancing the passivation efficacy/efficiency of the silyating agent.

Abstract: A thin film transistor array substrate device includes a gate line formed on a substrate, a data line crossing the gate line with a gate insulating pattern position therebetween, a thin film transistor at a crossing of the gate line and the data line, a pixel electrode formed at a pixel region defined by the crossing of the gate line and the data line and connected to the thin film transistor, a gate pad part having a lower gate pad electrode connected to the gate line and an upper gate pad electrode connected to the lower gate pad electrode, a data pad part having a lower data pad electrode connected to the date line and an upper data pad electrode connected to the lower data pad electrode, and a passivation film pattern formed at a region besides the region including the pixel electrode, the upper data pad electrode, and the upper gate pad electrode, wherein the pixel electrode is formed on the gate insulating pattern of the pixel region exposed by the passivation film pattern.

Abstract: Certain modifications and additions to the prior art short passivation technique have lead to improvements in the low light voltage of solar cells which are made using the improved passivation technique. Examples of the modifications include: 1) reducing the voltage bias on the cell while increasing the time of application of the voltage; 2) reversing the polarity of the voltage bias on the devices; 3) alternating pulsing between forward and reverse polarity bias; or 4) applying light energy simultaneously with an electrical bias voltage.

Abstract: A thin film transistor array substrate device includes a gate line formed on a substrate, a data line crossing the gate line with a gate insulating pattern position therebetween, a thin film transistor at a crossing of the gate line and the data line, a pixel electrode formed at a pixel region defined by the crossing of the gate line and the data line and connected to the thin film transistor, a gate pad part having a lower gate pad electrode connected to the gate line and an upper gate pad electrode connected to the lower gate pad electrode, a data pad part having a lower data pad electrode connected to the date line and an upper data pad electrode connected to the lower data pad electrode, and a passivation film pattern formed at a region besides the region including the pixel electrode, the upper data pad electrode, and the upper gate pad electrode, wherein the pixel electrode is formed on the gate insulating pattern of the pixel region exposed by the passivation film pattern.