Dielectric Regions, E.g., Epic Dielectric Isolation, Locos; Trench Refilling Techniques, Soi Technology, Use Of Channel Stoppers (epo) Patents (Class 257/E21.545)

  • Patent number: 10304741
    Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: May 28, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie
  • Patent number: 10211167
    Abstract: An integrated circuit assembly is formed with an insulating layer, a semiconductor layer, an active device, first, second, and third electrically conductive interconnect layers, and a plurality of electrically conductive vias. The insulating layer has a first surface and a second surface. The second surface is below the first surface. A substrate layer has been removed from the second surface. The semiconductor layer has a first surface and a second surface. The first surface of the semiconductor layer contacts the first surface of the insulating layer. The active device is formed in a region of the semiconductor layer. The first electrically conductive interconnect layer forms an electrically conductive ring. The second electrically conductive interconnect layer forms a first electrically conductive plate above the electrically conductive ring and the region of the semiconductor layer.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: February 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Michael A. Stuber
  • Patent number: 10153195
    Abstract: Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with dielectric material comprising silicon, oxygen and carbon. The carbon is present to a concentration within a range of from about 3 atomic percent to about 20 atomic percent. Some embodiments include a method of providing dielectric fill across a semiconductor construction having an opening extending therein. The semiconductor construction has an upper surface proximate the opening. The method includes forming photopatternable dielectric material within the opening and across the upper surface, and exposing the photopatternable dielectric material to patterned actinic radiation.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: December 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Scott L. Light, John A. Smythe, Sony Varghese
  • Patent number: 10014398
    Abstract: The disclosure relates to bipolar transistor devices and a method of fabricating the same. The device comprises a field plate, in an isolation region adjacent to a base-collector junction of said active region. The isolation region comprises a gate terminal arranged to be biased independently of a collector, base or emitter terminal of said transistor.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: July 3, 2018
    Assignee: NXP B.V.
    Inventors: Johannes Donkers, Viet Thanh Dinh, Tony Vanhoucke, Evelyne Gridelet, Anco Heringa, Dirk Klaassen
  • Patent number: 9953878
    Abstract: A method of forming a semiconductor device is provided. The method includes forming a recess in a substrate and forming a first dielectric layer in the recess. A portion of the first dielectric layer is removed. A second dielectric layer is formed over the first dielectric layer. A gate structure is formed over the second dielectric layer.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Lien Huang, Tung Ying Lee, Pei-Yi Lin, Chun-Hsiang Fan, Sheng-Wen Yu, Neng-Kuo Chen, Ming-Huan Tsai
  • Patent number: 9870956
    Abstract: An integrated circuit structure includes a semiconductor substrate, which includes a semiconductor strip. A Shallow Trench Isolation (STI) region is on a side of the semiconductor strip. The STI region includes a first portion comprising an oxide and a second portion free from oxide. The second portion separates the first portion from the semiconductor substrate. A semiconductor fin is over and aligned to the semiconductor strip, wherein the semiconductor fin is higher than a top surface of the STI region.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Neng-Kuo Chen, Gin-Chen Huang, Ching-Hong Jiang, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 9748245
    Abstract: A semiconductor device including an nFET device and pFET device adjacent one another. The semiconductor device includes a shallow trench isolator (STI), a gate and a substrate having fins extending upwardly through the STI. The fins include: nFET fins disposed in an nFET epi well formed in the STI and pFET fins disposed in a pFET epi well formed in the STI, a top the STI being above a top of the fins.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: August 29, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 9704745
    Abstract: A sacrificial layer is formed to cover the gate structures. The sacrificial layer is patterned to form a first opening in the sacrificial layer. A preliminary contact is formed in the first opening and the sacrificial layer is selectively removed. An insulating layer is formed to cover the gate structures and to expose the preliminary contact. The preliminary contact is removed to form a second opening in the insulating layer, and then a contact is formed in the second opening.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: July 11, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: KeunHee Bai, Dohyoung Kim, Johnsoo Kim, Heungsik Park, Doo-Young Lee, Sanghyun Lee
  • Patent number: 9673082
    Abstract: A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chen-Nan Yeh, Chu-Yun Fu, Ding-Yuan Chen
  • Patent number: 9673088
    Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: June 6, 2017
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Joblot, Pierre Bar
  • Patent number: 9530796
    Abstract: An integrated circuit assembly comprises an insulating layer, a semiconductor layer, a handle layer, a metal interconnect layer, and transistors. The insulating layer has a first surface, a second surface, and a hole extending from the first surface to the second surface. The semiconductor layer has a first surface and a second surface, the first surface of the semiconductor layer contacting the first surface of the insulating layer. The handle layer is coupled to the second surface of the semiconductor layer. The metal interconnect layer is coupled to the second surface of the insulating layer, the metal interconnect layer being disposed within the hole in the insulating layer. The transistors are located in the semiconductor layer. The hole in the insulating layer extends to at least the first surface of the semiconductor layer. The metal interconnect layer electrically couples a plurality of the transistors to each other.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: December 27, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Michael A. Stuber, Stuart B. Molin, Chris Brindle
  • Patent number: 9502292
    Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: November 22, 2016
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMicroelectronics, Inc., COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Bruce B. Doris, Shom Ponoth, Prasanna Khare, Qing Liu, Nicolas Loubet, Maud Vinet
  • Patent number: 9040424
    Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: May 26, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Janos Fucsko, David H. Wells, Patrick Flynn, Whonchee Lee
  • Patent number: 8994177
    Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tymon Barwicz, Robert L. Bruce, Swetha Kamlapurkar
  • Patent number: 8981480
    Abstract: A semiconductor device includes a buried well, first and second active regions, an isolation layer, and a low resistance region. The buried well is disposed on a substrate and has impurity ions of a first conductivity type. The first and second active regions are disposed on the buried well and each have impurity ions of a second conductivity type, which is different from the first conductivity type. The isolation layer is disposed between the first and second active regions. The low resistance region is disposed between the isolation layer and the substrate and has impurity ions of the second conductivity type. The concentration of impurity ions in the low resistance region is greater than the concentration of the impurity ions in each of the first and second active regions.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Hee Lim, Satoru Yamada, Sung-Duk Hong
  • Patent number: 8975128
    Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: March 10, 2015
    Assignee: SuVolta, Inc.
    Inventors: Scott E. Thompson, Damodar R. Thummalapally
  • Patent number: 8952454
    Abstract: An SOI wafer according to the present invention includes a support substrate and an insulating layer formed on the support substrate, a predetermined cavity pattern being formed on one of main surfaces of the support substrate on which the insulating layer is provided, further includes an active semiconductor layer formed on the insulating layer with the cavity pattern being closed, the active semiconductor layer not being formed in an outer peripheral portion of the support substrate, and further includes a plurality of superposition mark patterns formed in the outer peripheral portion on the one of the main surfaces of the support substrate for specifying a position of the cavity pattern.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: February 10, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuhiro Shimizu, Junichi Yamashita, Takuichiro Shitomi
  • Patent number: 8952485
    Abstract: An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such that it completely fills the smaller isolation trench and lines the larger isolation trench. The nitride layer is etched back to form a recess in the nitride layer in the smaller isolation trench while at least a portion of the nitride layer lining the larger isolation trench is completely removed. A layer of HDP oxide is deposited over the substrate, completely filling the smaller and larger isolation trenches. The HDP oxide layer is planarized to the upper surface of the substrate. The deeper larger isolation trench may be formed by performing an etching step after the nitride layer has been etched back, prior to depositing HDP oxide.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Xianfeng Zhou
  • Patent number: 8946829
    Abstract: A semiconductor apparatus includes fin field-effect transistor (FinFETs) having shaped fins and regular fins. Shaped fins have top portions that may be smaller, larger, thinner, or shorter than top portions of regular fins. The bottom portions of shaped fins and regular fins are the same. FinFETs may have only one or more shaped fins, one or more regular fins, or a mixture of shaped fins and regular fins. A semiconductor manufacturing process to shape one fin includes forming a photolithographic opening of one fin, optionally doping a portion of the fin, and etching a portion of the fin.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Yi-Tang Lin, Chih-Sheng Chang, Chi-Wen Liu
  • Patent number: 8946051
    Abstract: It is an object to provide a method for manufacturing an SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced even when a single crystal semiconductor substrate in which crystal defects exist is used. Such an SOI substrate can be manufactured through the steps of forming a single crystal semiconductor layer which has an extremely small number of defects over a single crystal semiconductor substrate by an epitaxial growth method; forming an oxide film on the single crystal semiconductor substrate by thermal oxidation treatment; introducing ions into the single crystal semiconductor substrate through the oxide film; bonding the single crystal semiconductor substrate into which the ions are introduced and a semiconductor substrate to each other; causing separation by heat treatment; and performing planarization treatment on the single crystal semiconductor layer provided over the semiconductor substrate.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Eriko Nishida
  • Patent number: 8932956
    Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tymon Barwicz, Robert L. Bruce, Swetha Kamlapurkar
  • Patent number: 8927388
    Abstract: A method of fabricating a dielectric layer includes the following steps. At first, a dielectric layer is formed on a substrate, and a chemical mechanical polishing (CMP) process is performed on the dielectric layer. Subsequently, a surface treatment process is performed on the dielectric layer after the chemical mechanical polishing process, and the surface treatment process includes introducing an oxygen plasma.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: January 6, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Jei-Ming Chen, Wen-Yi Teng, Chia-Lung Chang, Chih-Chien Liu
  • Patent number: 8928121
    Abstract: The present invention relates to a method for thermal stress reduction on a wafer, comprising the steps of providing a patterned wafer with saw lanes between adjacent dies, forming thin holes within the silicon substrate, which holes create a dotted groove in the saw lanes, and wherein no second layer on an opposing side of the wafer is formed, a patterned wafer obtained by said method. The forming of the holes is preferably combined with other processing steps or another step to avoid additional operations and manipulations prior to, or after standard wafer processing, and it therefore optimizes fabrication quality and costs. Preferably the holes within the silicon substrate having a depth of more than 3 to 50 ?m, preferably from 5-40 ?m, like 20 ?m.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: January 6, 2015
    Assignee: NXP B.V.
    Inventor: Alain Cousin
  • Patent number: 8928119
    Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 ?m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: January 6, 2015
    Inventor: Glenn J. Leedy
  • Patent number: 8927416
    Abstract: A first insulating film is formed on a semiconductor substrate, an interconnect groove is formed in the first insulating film, the inside of the interconnect groove is filled with a metal film, thereby forming a first interconnect. Then, a protective film is formed on the first insulating film and the first interconnect, and the surface of the protective film is exposed to reactive gas, thereby forming a reaction layer on an interface between the first interconnect and the protective film.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: January 6, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takeshi Harada, Junichi Shibata, Akira Ueki
  • Patent number: 8907410
    Abstract: A through-the silicon via (TSV) structure providing a built-in TSV U-shaped FET that includes an annular gate shaped as a TSV partially embedded in a substrate, the annular gate having an inner and an outer surface bound by an oxide layer; a drain formed on an isolated epitaxial layer on top of the substrate conformally connecting the gate oxide layer surrounding the inner annular surface of the TSV; a source partially contacting said gate oxide layer conformally contacting gate oxide layer surrounding the outer surface of the TSV.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chandrasekharan Kothandaraman, Sami Rosenblatt, Geng Wang
  • Patent number: 8884377
    Abstract: In one embodiment, first and second pattern structures respectively include first and second conductive line patterns and first and second hard masks sequentially stacked, and at least portions thereof extends in a first direction. The insulation layer patterns contact end portions of the first and second pattern structures. The first pattern structure and a first insulation layer pattern of the insulation layer patterns form a first closed curve shape in plan view, and the second pattern structure and a second insulation layer pattern of the insulation layer patterns form a second closed curve shape in plan view. The insulating interlayer covers upper portions of the first and second pattern structures and the insulation layer patterns, a first air gap between the first and second pattern structures, and a second air gap between the insulation layer patterns.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sok-Won Lee, Joon-Hee Lee, Jung-Dal Choi, Seong-Min Jo
  • Patent number: 8871649
    Abstract: One illustrative method disclosed herein involves forming a layer of insulating material, forming a patterned layer of photoresist above the layer of insulating material, wherein the patterned layer of photoresist has an opening defined therein, forming an internal spacer within the opening in the patterned layer of photoresist, wherein the spacer defines a reduced-size opening, performing an etching process through the reduced-size opening on the layer of insulating material to define a trench/hole type feature in the layer of insulating material, and forming a conductive structure in the trench/hole type feature in the layer of insulating material.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 28, 2014
    Assignees: GLOBALFOUNDRIES Inc., Renesas Electronics Corporation, International Business Machines Corporation
    Inventors: Linus Jang, Yoshinori Matsui, Chiahsun Tseng
  • Patent number: 8815694
    Abstract: Embodiments include semiconductor-on-insulator (SOI) substrates having SOI layers strained by oxidation of the base substrate layer and methods of forming the same. The method may include forming a strained channel region in a semiconductor-on-insulator (SOI) substrate including a buried insulator (BOX) layer above a base substrate layer and a SOI layer above the BOX layer by first etching the SOI layer and the BOX layer to form a first isolation recess region and a second isolation recess region. A portion of the SOI layer between the first isolation recess region and the second isolation recess region defines a channel region in the SOI layer. A portion of the base substrate layer below the first isolation recess region and below the second isolation recess region may then be oxidized to form a first oxide region and a second oxide region, respectively, that apply compressive strain to the channel region.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz, Pranita Kerber
  • Patent number: 8816470
    Abstract: A semiconductor chip has an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. A bottom, or floor, of the independently voltage controlled silicon region is a deep implant of opposite doping to a doping of a substrate of the independently voltage controlled silicon region. A top, or ceiling, of the independently voltage controlled silicon region is a buried oxide implant in the substrate. Sides of the independently voltage controlled silicon region are deep trench isolation. Voltage of the independently voltage controlled silicon region is applied through a contact structure formed through the buried oxide.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
  • Patent number: 8815699
    Abstract: Generally, the present disclosure is directed to methods for forming reverse shallow trench isolation structures with super-steep retrograde wells for use with field effect transistor elements. One illustrative method disclosed herein includes performing a thermal oxidation process to form a layer of thermal oxide material on a semiconductor layer of a semiconductor substrate, and forming a plurality of openings in the layer of thermal oxide material to form a plurality of isolation regions from the layer of thermal oxide material, wherein each of the plurality of openings exposes a respective surface region of the semiconductor layer.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: August 26, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tong Weihua, Krishnan Bharat, Lun Zhao, Kim Seung, Lee Yongmeng, Kim Sun
  • Patent number: 8796149
    Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, David L. Harame, Qizhi Liu
  • Patent number: 8785290
    Abstract: A method for manufacturing a semiconductor device, the method comprising, forming an opening in an insulating layer, which is formed on a semiconductor substrate, using a photoresist pattern formed on the insulating layer as a mask, forming a first element isolation portion in the semiconductor substrate by implanting an ion into the semiconductor substrate using the photoresist pattern as a mask, forming a second element isolation portion, in the semiconductor substrate, whose outer edge is outside an outer edge of the opening, by implanting an ion into the semiconductor substrate through the opening, and forming a third element isolation portion, which is inside the outer edge of the second element isolation portion, by embedding an insulating member in the opening and removing the insulating layer.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: July 22, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiroaki Naruse
  • Patent number: 8785291
    Abstract: Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: July 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xiaojun Yu, Brian J. Greene, Yue Liang
  • Patent number: 8779469
    Abstract: Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: July 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brian J. Greene, Yue Liang, Xiaojun Yu
  • Patent number: 8779435
    Abstract: A semiconductor wafer has a plurality of optical semiconductor devices (namely, semiconductor lasers) which are formed from epitaxially grown layers and arranged across the surface of the semiconductor wafer. The InGaAs epitaxial layer of the semiconductor wafer has an opening (or groove) which continuously extends along and between the plurality of optical semiconductor devices, and which exposes the layer underlying the InGaAs epitaxial layer to at least the layer overlying the InGaAs epitaxial layer. The semiconductor wafer may be scribed along this opening to form a vertically extending crack therein.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: July 15, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Masato Negishi
  • Patent number: 8772126
    Abstract: A cavity is etched from a front surface into a semiconductor substrate. After providing an etch stop structure at the bottom of the cavity, the cavity is closed. From a back surface opposite to the front surface the semiconductor substrate is grinded at least up to an edge of the etch stop structure oriented to the back surface. Providing the etch stop structure at the bottom of an etched cavity allows for precisely adjusting a thickness of a semiconductor body of a semiconductor device.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: July 8, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Anton Mauder
  • Patent number: 8765555
    Abstract: A phase change memory cell includes a first electrode having a cylindrical portion. A dielectric material having a cylindrical portion is longitudinally over the cylindrical portion of the first electrode. Heater material is radially inward of and electrically coupled to the cylindrical portion of the first electrode. Phase change material is over the heater material and a second electrode is electrically coupled to the phase change material. Other embodiments are disclosed, including methods of forming memory cells which include first and second electrodes having phase change material and heater material in electrical series there-between.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: July 1, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Damon E. Van Gerpen
  • Patent number: 8759944
    Abstract: Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric layer to expose the silicon layer, the trench having trench walls in the <100> direction. The method includes epitaxially growing silicon between trench walls formed in the dielectric layer.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: June 24, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Du Li
  • Patent number: 8748261
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer, a base region of a second-conductivity-type formed in an upper portion of the first-conductivity-type semiconductor layer, first though third trenches penetrating through the base region and reaching to the first-conductivity-type semiconductor layer, the first through third trenches being linked to one another, a source interconnect layer buried in the first through third trenches, the source interconnect layer including a protruding portion, a gate electrode buried in the first trench and the third trench, and formed over the source interconnect layer, a source metal contacting the protruding portion of the source interconnect layer, and a gate metal contacting the gate electrode in the third trench. A contact face between the source metal and the protruding portion at the second trench is formed higher than a contact face between the gate metal and the gate electrode at the third trench.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Kei Takehara
  • Patent number: 8735294
    Abstract: A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device includes a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one implementation, a method for fabricating a vertically arranged LDMOS device includes forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: May 27, 2014
    Assignee: International Rectifier Corporation
    Inventor: Igor Bol
  • Patent number: 8736019
    Abstract: A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: May 27, 2014
    Assignee: Icemos Technology Ltd.
    Inventors: Samuel Anderson, Koon Chong So
  • Patent number: 8729662
    Abstract: A semiconductor integrated circuit is reduced in size by suppressing lateral extension of an isolation region when impurities are thermally diffused in a semiconductor substrate to form the isolation region. Boron ions (B+) are implanted into an epitaxial layer through a third opening K3 to form a P-type impurity region, using a third photoresist as a mask. Then a fourth photoresist is formed on a silicon oxide film to have fourth openings K4 (phosphorus ion implantation regions) that partially overlap the P-type impurity region. Phosphorus ions (P+) are implanted into the surface of the epitaxial layer in etched-off regions using the fourth photoresist as a mask to form N-type impurity regions that are adjacent the P-type impurity region. After that, a P-type upper isolation region is formed in the epitaxial layer by thermal diffusion so that the upper isolation region and a lower isolation region are combined together to make an isolation region.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: May 20, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Keiji Mita
  • Patent number: 8716138
    Abstract: Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 6, 2014
    Assignee: FlashSilicon Incorporation
    Inventor: Lee Wang
  • Patent number: 8716829
    Abstract: A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: May 6, 2014
    Assignee: Icemos Technology Ltd.
    Inventors: Samuel Anderson, Koon Chong So
  • Patent number: 8704329
    Abstract: SOI devices for plasma display panel driver chip, include a substrate, a buried oxide layer and an n-type SOI layer in a bottom-up order, where the SOI layer is integrated with an HV-NMOS device, an HV-PMOS device, a Field-PMOS device, an LIGBT device, a CMOS device, an NPN device, a PNP device and an HV-PNP device; the SOI layer includes an n+ doped region within the SOI layer at an interface between the n-type SOI layer and the buried oxide layer; and the n+ doped region has a higher doping concentration than the n-type SOI layer.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: April 22, 2014
    Assignee: University of Electronic Science and Technology of China
    Inventors: Ming Qiao, Bo Luo, Xi Hu, Jun Ye, Bo Zhang, Zhaoji Li
  • Patent number: 8692299
    Abstract: An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min Hao Hong, You-Hua Chou, Chih-Tsung Lee, Shiu-Ko JangJian, Miao-Cheng Liao, Hsiang Hsiang Ko, Chen-Ming Huang
  • Patent number: 8686535
    Abstract: Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth. In various embodiments the implant of energetic species is used to densify the dielectric material to provide a uniform wet etch rate across the surface of the dielectric material. Embodiments also include memory devices, integrated circuits, and electronic systems that include shallow trench isolation structures having the dielectric material with the high flux of energetic species implanted to the predetermined depth of the dielectric material.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, John A. Smythe, III
  • Patent number: 8685830
    Abstract: A method of filling shallow trenches is disclosed. The method includes: successively forming a first oxide layer and a second oxide layer over the surface of a silicon substrate where shallow trenches are formed in; etching the second oxide layer to form inner sidewalls with an etchant which has a high etching selectivity ratio of the second oxide layer to the first oxide layer; growing a high-quality pad oxide layer by thermal oxidation after the inner sidewalls are removed; and filling the trenches with an isolation dielectric material. By using this method, the risk of occurrence of junction spiking and electrical leakage during a subsequent process of forming a metal silicide can be reduced.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: April 1, 2014
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Fan Chen, Xiongbin Chen, Kai Xue, Keran Zhou, Jia Pan, Hao Li, Yongcheng Wang
  • Patent number: RE45361
    Abstract: The object of the present invention is to embed an insulating film in a hole having a high aspect ratio and a small width without the occurrence of a void. The thickness of a polishing stopper layer is reduced by making separate layers respectively serve as a mask during forming the hole in a semiconductor substrate, and a stopper during removing the insulating film filled in the hole.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: February 3, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Toshiyuki Hirota