Abstract: There is a method of manufacturing a memory device. The method includes forming a mask layer on an etching target layer; forming, on the mask layer, a compensation layer with a second impurity that chemically bonds to the mask layer with a first impurity; performing a first etching process that patterns the compensation layer and the mask layer to form a mask pattern; and performing a second etching process that etches the etching target layer, which is exposed through openings of the mask pattern.

Abstract: A method includes bonding a first and a second device die to a third device die, forming a plurality of gap-filling layers extending between the first and the second device dies, and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. A first etch stop layer in the plurality of gap-filling layers is used to stop the first etching process. The opening is then extended through the first etch stop layer. A second etching process is performed to extend the opening through a second dielectric layer underlying the first etch stop layer. The second etching process stops on a second etch stop layer in the plurality of gap-filling layers. The method further includes extending the opening through the second etch stop layer, and filling the opening with a conductive material to form a through-via.

Abstract: A semiconductor device includes a first lower line and a second lower line on a substrate, the first and second lower lines extending in a first direction, being adjacent to each other, and being spaced apart along a second direction, orthogonal the first direction, an airgap between the first and second lower lines and spaced therefrom along the second direction, a first insulating spacer on a side wall of the first lower line facing the second lower line, wherein a distance from the first airgap to the first lower line along the second direction is equal to or greater than an overlay specification of a design rule of the semiconductor device, and a second insulating spacer between the airgap and the second lower line.

Abstract: A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.

Abstract: A method for forming a semiconductor structure includes: providing a substrate, the substrate including an array area and a metal interconnection area located at the periphery of the array area; and forming a metal interconnection structure in the metal interconnection area, in which the metal interconnection structure includes a plurality of stacked metal wiring layers and a plurality of connecting pillars connected between each of the metal wiring layers, each of the metal wiring layer includes a plurality of metal strips distributed at intervals, the metal strips of two adjacent metal wiring layers are staggered, and two adjacent metal strips located in a same layer are respectively connected with one same metal strip directly below them through the connecting pillars.

Abstract: A structure includes a first dielectric film and a second dielectric film. The second dielectric film is formed on and in contact with the first dielectric film, in which a first pore is formed between the first dielectric film and the second dielectric film, and a thickness of the first dielectric film is smaller than a diameter of the first pore.

Abstract: A semiconductor structure for a memory device includes a substrate including a memory cell region and a peripheral circuit region defined thereon, at least an active region formed in the peripheral circuit region, a buried gate structure formed in the active region in the peripheral circuit region, a conductive line structure formed on the buried gate structure, and at least a bit line contact plug formed in the memory cell region.

Abstract: The present technology relates to an imaging device capable of preventing a decrease of sensitivity of the imaging device in a case where a capacitance element is provided in a pixel, a method of manufacturing an imaging device, and an electronic device. The imaging device includes, in a pixel, a photoelectric conversion element and a capacitance element accumulating an electric charge generated by the photoelectric conversion element. The capacitance element includes a first electrode including a plurality of trenches, a plurality of second electrodes each having a cross-sectional area smaller than a contact connected to a gate electrode of a transistor in the pixel, and buried in each of the trenches, and a first insulating film disposed between the first electrode and the second electrode in each of the trenches. The present technology can be applied, for example, to a backside irradiation-type CMOS image sensor.

Abstract: The present technology relates to an imaging device capable of preventing a decrease of sensitivity of the imaging device in a case where a capacitance element is provided in a pixel, a method of manufacturing an imaging device, and an electronic device. The imaging device includes, in a pixel, a photoelectric conversion element and a capacitance element accumulating an electric charge generated by the photoelectric conversion element. The capacitance element includes a first electrode including a plurality of trenches, a plurality of second electrodes each having a cross-sectional area smaller than a contact connected to a gate electrode of a transistor in the pixel, and buried in each of the trenches, and a first insulating film disposed between the first electrode and the second electrode in each of the trenches. The present technology can be applied, for example, to a backside irradiation-type CMOS image sensor.

Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner including polymer; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.

Abstract: A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level.

Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.

Abstract: A printed circuit board includes a first insulating layer; a protective filler layer disposed on one surface of the first insulating layer; a first wiring layer disposed on the one surface of the first insulating layer and having a pad protruding with respect to the protective filler layer; a first via passing through the first insulating layer and contacting the pad; and a second insulating layer disposed on the first wiring layer and the protective filler layer, and having a cavity exposing the pad and at least a portion of the protective filler layer, respectively.

Abstract: Some embodiments relate to a semiconductor structure including an inter-level dielectric (ILD) layer overlying a substrate. A conductive via is disposed within the ILD layer. A plurality of conductive wires overlie the ILD layer. The plurality of conductive wires includes a first conductive wire laterally offset a second conductive wire. A dielectric structure is disposed laterally between the first and second conductive wires. The dielectric structure includes a first dielectric liner, a dielectric layer, and an air-gap. The air-gap is disposed between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is disposed along an upper surface of the dielectric structure. The dielectric capping layer continuously extends between opposing sidewalls of the dielectric structure and is laterally offset from the plurality of conductive wires.

Abstract: An interconnect structure includes a damascene structure, an inter-metal dielectric (IMD), a dielectric block and a metal via. The inter-metal dielectric layer is over the damascene structure. The dielectric block is embedded in the IMD layer and has a different etch selectivity than the IMD layer. The metal via is in the IMD layer and through the dielectric block to electrically connect the damascene structure.

Abstract: A method includes providing a structure having a gate stack; first gate spacers; a second gate spacer over one of the first gate spacers and having an upper portion over a lower portion; a dummy spacer; an etch stop layer; and a dummy cap. The method further includes removing the dummy cap, resulting in a first void above the gate stack and between the first gate spacers; removing the dummy spacer, resulting in a second void above the lower portion and between the etch stop layer and the upper portion; depositing a layer of a decomposable material into the first and the second voids; depositing a seal layer over the etch stop layer, the first and the second gate spacers, and the layer of the decomposable material; and removing the layer of the decomposable material, thereby reclaiming at least portions of the first and the second voids.

Abstract: Methods are disclosed herein that improve contours of trenches formed when fabricating vias and conductive lines of a multi-layer interconnect (MLI) structure. An exemplary device that can result from such methods includes a via of an MLI structure and a conductive line of the MLI structure disposed over the via. A first dielectric liner layer is disposed along sidewalls of the via and sidewalls of the conductive line. A thickness of the first dielectric liner layer is substantially the same along the sidewalls of the via. A thickness of the first dielectric liner layer increases along the sidewalls of the conductive line, such that the first dielectric liner layer has a tiger-tooth shape at each bottom corner of the conductive line. A second dielectric liner layer is disposed along the first dielectric liner layer that is disposed along the sidewalls of the via.

Abstract: The present application discloses a semiconductor device with alleviation features for reducing capacitive coupling between conductive features and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first conductive line positioned on the substrate and extend along a first direction, a first conductive line spacer positioned on a sidewall of the first conductive line, a bottom contact positioned adjacent to the first conductive line, a bottom contact spacer positioned on a sidewall of the bottom contact, an air gap positioned between the first conductive line spacer and the bottom contact spacer, and a second conductive line positioned above the bottom contact and extend along a second direction different from the first direction.

Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a metallization structure with a top surface. A conductive pad is over the top surface. An upper passivation layer is over the top surface and the conductive pad and includes a first implanted region. A polymer layer is over the upper passivation layer and the conductive pad. A conductive via penetrates through the upper passivation layer and the polymer layer, and electrically coupled to the conductive pad. A method for manufacturing a semiconductor structure is also provided.

Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.

Abstract: Some embodiments include a conductive structure of an integrated circuit. The conductive structure includes an upper primary portion, with the upper primary portion having a first conductive constituent configured as a container. The container has a bottom, and a pair of sidewalls extending upwardly from the bottom. An interior region of the container is over the bottom and between the sidewalls. The upper primary portion includes a second conductive constituent configured as a mass filling the interior region of the container. The second conductive constituent is a different composition than the first conductive constituent. One or more conductive projections join to the upper primary portion and extend downwardly from the upper primary portion. Some embodiments include assemblies comprising memory cells over conductive structures. Some embodiments include methods of forming conductive structures.

Abstract: There is provided a substrate processing method, including: forming a silicon nitride film laminated on an etching target film by supplying a film forming gas to a substrate; oxidizing a surface of the silicon nitride film to form an oxide layer by supplying an oxidizing gas to the substrate; and etching the etching target film by supplying an etching gas containing halogen to the substrate, in a state in which the etching target film and the oxide layer are exposed on a surface of the substrate.

Abstract: A method of fabricating a hard mask structure is provided. According to the method, a hard mask layer is disposed over a substrate. The hard mask layer includes a lower hard mask layer disposed over the substrate and an upper hard mask layer disposed over the lower hard mask layer. The hard mask layer is patterned and the upper hard mask layer is removed by selectively etching the upper hard mask layer until reaching the lower hard mask layer to form a top portion of the hard mask structure having a first dimension. A spacer material is disposed on a sidewall of the top portion of the hard mask structure. The lower hard mask layer is removed by selectively etching the lower mask layer until reaching the substrate to form a bottom portion of the hard mask structure having a second dimension.

Abstract: A method and structure for providing a semiconductor-on-insulator (SCOI) wafer having a buried low-K dielectric layer includes forming a device layer on a first semiconductor substrate. In various embodiments, at least a portion of the device layer is separated from the first semiconductor substrate, where the separating forms a cleaved surface on the separated portion of the device layer. In some examples, a patterned low-K dielectric layer is formed on a second semiconductor substrate. Thereafter, and in some embodiments, the separated portion of the device layer is bonded, along the cleaved surface, to the patterned low-K dielectric layer.

Abstract: Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a signaling interconnect having a narrow trench disposed within a metallization layer, and a power rail having a wide trench disposed within the metallization layer, wherein the signaling interconnect comprises non-copper material and the power rail comprises copper. The non-copper material may include at least one of ruthenium (Ru), tungsten (W), aluminum (Al), and cobalt (Co). The signaling interconnect and power rail may be processed in a common chemical mechanical polishing step and have approximately the same trench depth. A metal cap may be deposited on top of the power rail.

Abstract: Examples herein relate to devices having substrates with selective airgap regions for mitigating defects resulting from heteroepitaxial growth of device materials. An example device may include a first semiconductor layer disposed on a substrate. The first semiconductor layer may have a window cut through a face, where etching a selective airgap region on the substrate is enabled via the window. A second semiconductor layer may be heteroepitaxially grown on the face of the first semiconductor layer so that at least a portion of the second semiconductor layer is aligned over the selective air gap region.

Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.

Abstract: Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.

Abstract: A method is presented for forming interlayer connections in a semiconductor device. The method includes patterning an etch stack to provide for a plurality of interlayer connections, etching guide layers following the etch stack to a first capping layer to form a plurality of guide openings, concurrently exposing a first plurality of conductive lines and a second plurality of conductive lines to form a plurality of interlayer connection openings by etching through the plurality of guide openings to remove the first capping layer, an interlayer dielectric, and a second capping layer, and depositing a metal fill in the plurality of interlayer connection openings to form the plurality of interlayer connections.

Abstract: A method of forming an interconnect to an electrical device is provided. The structure produced by the method may include a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parallel lengths; and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines.

Abstract: An IC device, such as a wafer, chip, die, processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), or the like include a chamfered VIA that connects an upper wiring line and a first lower wiring line. The chamfered VIA includes a chamfer or fillet upon the edge that connects the VIA sidewall(s) with the VIA contact surface that is connected to the first lower wiring line. The chamfer or fillet effectively increases the amount of a dielectric material, such as a high-k dielectric material, within a trench of the VIA and that is between the chamfered VIA and a second lower wiring line that neighbors the first lower wiring line. This increased dielectric material improves TDDB between the chamfered VIA and the second lower wiring line and mitigates TDDB effects, such as electrical shorts between the chamfered VIA and the second lower wiring line.

Abstract: A semiconductor device is provided that includes a substrate, an integrated circuit with a conductive member and a through-substrate-via (TSV) structure. The substrate includes a front surface and a back surface that is opposite the front surface. The integrated circuit with the conductive member is formed over the front surface of the substrate. The TSV structure having vertical sidewalls is formed in the back surface of the substrate connecting with the conductive member. The TSV structure includes a tapered first insulation layer, a conformal conductive layer and a second insulation layer, with the conformal conductive layer positioned between the first and second insulation layers. The conformal conductive layer is electrically connected to the conductive member.

Abstract: In some embodiments, an integrated chip (IC) is provided. The IC includes a metallization structure disposed over a semiconductor substrate, where the metallization structure includes an interconnect structure disposed in an interlayer dielectric (ILD) structure. A passivation layer is disposed over the metallization structure, where an upper surface of the interconnect structure is at least partially disposed between opposite inner sidewalls of the passivation layer. A sidewall spacer is disposed along the opposite inner sidewalls of the passivation layer, where the sidewall spacer has rounded sidewalls. A conductive structure is disposed on the passivation layer, the rounded sidewalls of the sidewall spacer, and the upper surface of the interconnect structure.

Abstract: Embodiments of the invention are directed to a method that includes forming a dielectric region having a dielectric region top surface, wherein the dielectric top surface is substantially planar. A first interconnect structure having a substantially planar interconnect structure top surface with unintended non-planar regions is formed in the dielectric region.

Abstract: A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment, the method comprises receiving a substrate and depositing a first layer over the substrate. A copolymer layer that includes a first constituent polymer and a second constituent polymer is formed over the first layer. The first constituent polymer is selectively removed from the copolymer layer. A first region of the first layer corresponding to the selectively removed first constituent polymer is etched. The etching leaves a second region of the first layer underlying the second constituent polymer unetched. A metallization process is performed on the etched substrate, and the first layer is removed from the second region to form an air gap. The method may further comprise depositing a dielectric material within the etched first region.

Abstract: An SOI substrate manufacturing method and an SOI substrate are provided, where the method includes: forming a patterned etch-stop layer in an oxide layer of a first silicon substrate, bonding a surface, having the patterned etch-stop layer (130), of the first silicon substrate with a surface of a second silicon substrate, and peeling off a part of the first silicon substrate to form a patterned SOI substrate.

Abstract: Grating based plugs and cuts for feature end formation for back end of line (BEOL) interconnects are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a hardmask layer above an interlayer dielectric (ILD) material layer. A first patterned hardmask layer is formed above the hardmask layer. A second patterned hardmask layer is formed above the first patterned hardmask layer. A lithographic patterning mask is formed above the second patterned hardmask layer. Portions of the second patterned hardmask layer not protected by the regions of the lithographic patterning mask are removed to form a third patterned hardmask layer and then the lithographic patterning mask is removed. A combined pattern of the third patterned hardmask layer and the first patterned hardmask layer is transferred to the hardmask layer and to the ILD material layer.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes following steps. A MEOL structure is formed on an etch stop layer. A patterned masking layer with at least one opening is formed on the MEOL structure and a first etching process is performed to form a trench in the MEOL structure. A second etching process is performed to modify at least one sidewall of the trench.

Abstract: A method of producing a layer structure and a method of forming a pattern, the method of producing a layer structure including coating a first composition on a substrate that has a pattern thereon; curing the coated first composition to form a first organic layer; applying a liquid material to the first organic layer to remove a part of the first organic layer; and coating a second composition on remaining parts of the first organic layer; and curing the coated second composition on the remaining parts of the first organic layer to form a second organic layer: wherein the first composition and the second composition each independently include a solvent, and a polymer including a structural unit represented by Chemical Formula 1, *A1-B1*.

Abstract: The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 ?m to about 0.2 ?m.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an active region on the substrate, an electrode in the active region, and an interlayer dielectric layer covering the active region and the electrode. The method also includes etching the interlayer dielectric layer to form a contact hole exposing the electrode, forming a conductive adhesion layer on a bottom and sidewalls of the contact hole, and forming a contact member on the conductive adhesion layer filling the contact hole. The conductive adhesion layer at the bottom and sidewalls of the contact hole prevents the electrode from being oxidized while forming the contact member, thereby effectively reducing the contact resistance and the barrier height of the semiconductor device.

Abstract: Embodiments of the invention provide a substrate processing method for bottom-up formation of a film in a recessed feature. According to one embodiment, the method includes providing a substrate containing a first layer and a second layer on the first layer, the second layer having a recessed feature extending through the second layer, and depositing a non-conformal mask layer on the substrate, where the mask layer has an overhang at an opening of the recessed feature. The method further includes removing the mask layer from a bottom of the recessed feature, while maintaining at least a portion of the overhang at the opening, selectively depositing a film on the bottom of the recessed feature, and removing the mask layer overhang from the substrate. The processing steps may be repeated at least once until the film has a desired thickness in the recessed feature.

Abstract: A semiconductor device is provided. The semiconductor device includes an insulating structure and a dielectric structure. The insulating structure is disposed on a substrate and has a plurality of openings. The dielectric structure is disposed on the insulating structure and extending into the plurality of openings.

Abstract: A method for etching an organic carbon based layer below a silicon containing hardmask is provided. An etch gas is provided comprising oxygen and a halogen containing component, and a passivation component, wherein a ratio by volume of total flow rate of the etch gas to flow rate of the halogen containing component is between 10,000:1 to 10:1. The etch gas is formed into a plasma, wherein the organic carbon based layer and the silicon contain hardmask are exposed to the plasma and wherein the plasma selectively etches the organic carbon based layer with respect to the silicon containing hardmask.

Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than other parts of the line. Thereafter, vias are created where the notches are located. The locations of the vias are such that the effect of blown-out areas is minimized. Thereafter, the lines are etched and the vias and line areas are filled. The layers are planarized such that the metal fill is level with a surrounding ultra-low-k dielectric. Additional metal layers, lines, and vias can be created. Other embodiments are also described herein.

Abstract: A method for connecting metal layers in a mixed wire structure for a semiconductor substrate. A lower metal layer and a via in the mixed wired structure is formed in a dielectric structure on the semiconductor substrate, wherein a layer of a barrier metal is absent between the lower metal layer and the via. A trench is formed in the dielectric structure for an upper metal layer that contacts the via. A barrier metal layer is formed on the via and in the trench. The upper metal layer is formed after forming the barrier metal layer, wherein the barrier metal layer is located between the via and the upper metal layer.

Abstract: The present disclosure relates to the field of liquid crystal display technology, and more particularly, to the flexible display panel and the manufacturing method thereof. The method includes forming the polymer on the anode layer from vapor of the organic dimer as the micro-cavity adjusting layer by the chemical vapor deposition method at the controlled temperature between 650° C. to 750° C. The structural formula of the organic dimer is as shown in Formula 1, wherein R is selected from one of H, F, Cl, and Br. The cathodic protective layer and the encapsulation layer can be formed by the same material and processes. The present disclosure discloses preparing the micro-cavity adjustment layer, the cathodic protective layer, and the encapsulation layer of the flexible OLED with the same material, which can simplify the preparation processes.

Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor.

Abstract: A semiconductor device according to the present embodiment is provided with a lower layer. A first film is provided on the lower layer. A first side-wall film covers a contact hole provided in the first film, along a side wall in the contact hole and from a lower end of the contact hole to an upper end of the contact hole. A second side-wall film is provided on the side wall in the contact hole via the first side-wall film, to cover the contact hole from a position higher than a lower end of the first side-wall film to the upper end of the contact hole. A conductor is provided inside the first and second side-wall films in the contact hole. An upper layer is provided on the first film.

Abstract: Described are methods for controlling the doping of metal nitride films such as TaN, TiN and MnN. The temperature during deposition of the metal nitride film may be controlled to provide a film density that permits a desired amount of doping. Dopants may include Ru, Cu, Co, Mn, Mo, Al, Mg, Cr, Nb, Ta, Ti and V. The metal nitride film may optionally be exposed to plasma treatment after doping.