Barrier, Adhesion Or Liner Layer (epo) Patents (Class 257/E21.584)
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Publication number: 20120326311Abstract: Alternative methods of fabricating an interconnect structure in which an enhanced diffusion barrier including an in-situ formed metal nitride liner formed between an interconnect dielectric material and an overlying metal diffusion barrier liner are provided. In one embodiment, the method includes forming at least one opening into an interconnect dielectric material. A nitrogen enriched dielectric surface layer is formed within exposed surfaces of the interconnect dielectric material utilizing thermal nitridation. A metal diffusion barrier liner is formed on the nitrogen enriched dielectric surface. During and/or after the formation of the metal diffusion barrier liner, a metal nitride liner forms in-situ in a lower region of the metal diffusion barrier liner. A conductive material is then formed on the metal diffusion barrier liner.Type: ApplicationFiled: June 21, 2011Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Chao Yang, Daniel C. Edelstein, Steven E. Molis
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Publication number: 20120326326Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.Type: ApplicationFiled: June 24, 2011Publication date: December 27, 2012Applicant: Tessera, Inc.Inventors: Cyprian Uzoh, Vage Oganesian, Ilyas Mohammed
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Publication number: 20120329269Abstract: Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.Type: ApplicationFiled: September 1, 2012Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Griselda Bonilla, William J. Cote, Geraud Dubois, Daniel C. Edelstein, Alfred Grill, Elbert Huang, Robert D. Miller, Satya V. Nitta, Sampath Purushothaman, E. Todd Ryan, Muthumanickam Sankarapandian, Terry A. Spooner, Willi Volksen
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Publication number: 20120325920Abstract: A method of forming an interconnection structure includes forming an opening in an insulation film by a dry etching process that uses an etching gas containing fluorine; cleaning a bottom surface and a sidewall surface of the opening by exposing to a superheated steam; covering the bottom surface and the sidewall surface of the opening with a barrier metal film; depositing a conductor film on the insulation film via the barrier metal film to fill the opening with the conductor film; forming an interconnection pattern by the conductor film in the opening by polishing the conductor film and the barrier metal film underneath the conductor film by a chemical mechanical polishing process until a surface of the insulation film is exposed.Type: ApplicationFiled: September 10, 2012Publication date: December 27, 2012Applicant: FUJITSU LIMITEDInventors: Shirou Ozaki, Yoshihiro Nakata
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Publication number: 20120322256Abstract: The manufacturing method of the high performance metal-oxide-metal according to the present invention resolves the problems of implementing high capacitance in the metal-oxide-metal region by the steps of filling with a low-k material both in the metal-oxide-metal region and the metal interconnection region, utilizing performing selective photolithography and etching of the first dielectric layer to define metal-oxide-metal (MOM for short) region, and fulfilling the MOM region with high dielectric constant (high-k) material to realize a high performance MOM capacitor. Using the present method, high-k material and low-k material within the same film layer are realized. High-k material region is used as MOM to achieve high capacitor c, thereby reducing the area used by chips and further improving the electrics performance.Type: ApplicationFiled: December 29, 2011Publication date: December 20, 2012Applicant: SHANGHAI HUALI MICROELECTRONICS CORPORATIONInventors: Youcun Hu, Lei Li, Chaos Zhang, Feng Ji, Yuwen Chen
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Publication number: 20120319278Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.Type: ApplicationFiled: June 16, 2011Publication date: December 20, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Chieh Lin, Hung-Wen Su, Minghsing Tsai, Syun-Ming Jang
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Publication number: 20120319184Abstract: A multi-path transistor includes an active region including a channel region and an impurity region. A gate is dielectrically separated from the channel region. A signal line is dielectrically separated from the impurity region. A conductive shield is disposed between, and dielectrically separated from, the signal line and the channel region. In some multi-path transistors, the channel region includes an extension-channel region under the conductive shield and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being in the extension-channel region to conduct substantially independent of a voltage on the signal line. In other multi-path transistors, the conductive shield is operably coupled to the impurity region and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being under the conductive shield to conduct substantially independent of a voltage on the signal line.Type: ApplicationFiled: August 27, 2012Publication date: December 20, 2012Applicant: MICRON TECHNOLOGY, INC.Inventor: Toru Tanzawa
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Publication number: 20120315755Abstract: A passivation layer is formed on inlaid Cu for protection against oxidation and removal during subsequent removal of an overlying metal hardmask. Embodiments include treating an exposed upper surface of inlaid Cu with hydrofluoric acid and a copper complexing agent, such as benzene triazole, to form a passivation monolayer of a copper complex, etching to remove the metal hardmask, removing the passivation layer by heating to at least 300° C., and forming a barrier layer on the exposed upper surface of the inlaid Cu.Type: ApplicationFiled: June 10, 2011Publication date: December 13, 2012Applicant: GLOBALFOUNDRIES Inc.Inventors: Christin Bartsch, Susanne Leppack
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Publication number: 20120315754Abstract: Interconnects containing ruthenium and methods of forming can include utilization of a sacrificial protective material. Planarization or other material removal operations can be performed on a substrate having a recess, the recess containing a ruthenium containing material along with the sacrificial protective material. The protective material is later removed, and a conductor can be filled in the remaining recess.Type: ApplicationFiled: June 8, 2011Publication date: December 13, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Xiaoyun Zhu, Dale W. Collins, Joseph Lindgren, Anurag Jindal
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Publication number: 20120315756Abstract: Embodiments of the invention provide methods for forming conductive materials within contact features on a substrate by depositing a seed layer within a feature and subsequently filling the feature with a copper-containing material during an electroless deposition process. In one example, a copper electroless deposition solution contains levelers to form convexed or concaved copper surfaces. In another example, a seed layer is selectively deposited on the bottom surface of the aperture while leaving the sidewalls substantially free of the seed material during a collimated PVD process. In another example, the seed layer is conformably deposited by a PVD process and subsequently, a portion of the seed layer and the underlayer are plasma etched to expose an underlying contact surface. In another example, a ruthenium seed layer is formed on an exposed contact surface by an ALD process utilizing the chemical precursor ruthenium tetroxide.Type: ApplicationFiled: March 15, 2012Publication date: December 13, 2012Inventors: Timothy W. Weidman, Arulkumar Shanmugasundram, Kapila Wijekoon, Schubert S. Chu, Frederick C. Wu, Kavita Shah
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Patent number: 8329575Abstract: A through-silicon via fabrication method includes etching a plurality of through holes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate and on the sidewalls and bottom wall of the through holes. A metallic conductor is then deposited in the through holes. In another version, which may be used concurrently with the oxide liner, a silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate.Type: GrantFiled: December 22, 2010Date of Patent: December 11, 2012Assignee: Applied Materials, Inc.Inventors: Nagarajan Rajagopalan, Ji Ae Park, Ryan Yamase, Shamik Patel, Thomas Nowak, Li-Qun Xia, Bok Hoen Kim, Ran Ding, Jim Baldino, Mehul Naik, Sesh Ramaswami
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Publication number: 20120306081Abstract: According to one embodiment, a semiconductor device includes an interconnect provided on a first interlayer insulating film covering a semiconductor substrate in which an element is formed, a cap layer provided on the upper surface of the interconnect, and a barrier film provided between the interconnect and a second interlayer insulating film covering the interconnect. The interconnect includes a high-melting-point conductive layer, and the width of the interconnect is smaller than the width of the cap layer. The barrier film includes a compound of a contained element in the high-melting-point conductive layer.Type: ApplicationFiled: March 22, 2012Publication date: December 6, 2012Inventors: Takeshi ISHIZAKI, Atsuko Sakata, Junichi Wada, Masahiko Hasunuma
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Patent number: 8324098Abstract: A via is formed on a wafer to lie within an opening in a non-conductive structure and make an electrical connection with an underlying conductive structure so that the entire top surface of the via is substantially planar, and lies substantially in the same plane as the top surface of the non-conductive structure. The substantially planar top surface of the via enables a carbon nanotube switch to be predictably and reliably closed.Type: GrantFiled: July 8, 2010Date of Patent: December 4, 2012Assignee: National Semiconductor CorporationInventors: Mehmet Emin Aklik, Thomas James Moutinho
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Patent number: 8324097Abstract: A copper-topped interconnect structure allows the combination of high density design areas, which have low current requirements that can be met with tightly packed thin and narrow copper traces, and low density design areas, which have high current requirements that can be met with more widely spaced thick and wide copper traces, on the same chip.Type: GrantFiled: March 31, 2010Date of Patent: December 4, 2012Assignee: National Semiconductor CorporationInventor: Abdalla Aly Naem
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Patent number: 8324095Abstract: A method and apparatus for depositing a tantalum nitride barrier layer is provided for use in an integrated processing tool. The tantalum nitride is deposited by atomic layer deposition. The tantalum nitride is removed from the bottom of features in dielectric layers to reveal the conductive material under the deposited tantalum nitride. Optionally, a tantalum layer may be deposited by physical vapor deposition after the tantalum nitride deposition. Optionally, the tantalum nitride deposition and the tantalum deposition may occur in the same processing chamber.Type: GrantFiled: November 30, 2009Date of Patent: December 4, 2012Assignee: Applied Materials, Inc.Inventors: Hua Chung, Nirmalya Maity, Jick Yu, Roderick Craig Mosely, Mei Chang
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Publication number: 20120299184Abstract: A monitor wafer for use in monitoring a preclean process and method of making same are described. One embodiment is a monitor wafer comprising a silicon base layer; a capping layer disposed on the silicon base layer; and a barrier layer disposed on the USG layer. The monitor wafer further comprises a copper (“Cu”) seed layer disposed on the barrier layer; and a thick Cu layer disposed on the Cu seed layer.Type: ApplicationFiled: May 25, 2011Publication date: November 29, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Liang Sung, Cheng-Hui Weng
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Publication number: 20120299188Abstract: Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.Type: ApplicationFiled: May 24, 2011Publication date: November 29, 2012Applicant: International Business Machines CorporationInventors: Fen Chen, Jeffrey P. Gambino, Anthony K. Stamper, Timothy D. Sullivan
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Publication number: 20120302058Abstract: A method of manufacturing a semiconductor device comprises forming a contact hole within an interlayer insulating film of a substrate and forming a contact plug while the substrate is heated. In forming the contact plug, the substrate is held on a stage within the chamber of a sputtering apparatus through a chuck, and an ESC voltage applied to the chuck is increased stepwise in a plurality of steps. First target power is applied to a target within the chamber to form a first Al film in the contact hole. Next, second target power higher than the first target power is applied to the target within the chamber to form a second Al film on the first Al film.Type: ApplicationFiled: March 22, 2012Publication date: November 29, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Katsuhiko TANAKA
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Patent number: 8319341Abstract: A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-based electrode. An intermediate structure, which includes a titanium layer and a tungsten silicide layer, is formed over the polysilicon-based electrode. A metal electrode is formed over the intermediate structure.Type: GrantFiled: August 23, 2010Date of Patent: November 27, 2012Assignee: Hynix Semiconductor Inc.Inventors: Min-Gyu Sung, Hong-Seon Yang, Heung-Jae Cho, Yong-Soo Kim, Kwan-Yong Lim
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Publication number: 20120295435Abstract: In one embodiment, a pattern transfer method includes forming a photoreactive resin on a substrate to be processed. The method further includes pressing a mold against the photoreactive resin, the mold including a transparent substrate having a concave-convex pattern, and a light-blocking film provided on a part of surfaces of the concave-convex pattern. The method further includes irradiating the photoreactive resin with light through the mold in a state in which the mold is pressed against the photoreactive resin. The method further includes baking the photoreactive resin in a state in which the mold is pressed against the photoreactive resin after irradiating the photoreactive resin with the light. The method further includes releasing the mold from the photoreactive resin after baking the photoreactive resin. The method further includes rinsing the photoreactive resin with a rinsing solution after releasing the mold.Type: ApplicationFiled: February 17, 2012Publication date: November 22, 2012Inventor: Ikuo Yoneda
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Publication number: 20120292770Abstract: A device for preventing corrosion on sensors and a method of fabricating the same is disclosed, wherein the device comprises an insulation layer and an adhesion layer covering a metallization layer of a silicon sensor with a corrosion resistant layer located over the adhesion layer.Type: ApplicationFiled: May 19, 2011Publication date: November 22, 2012Applicant: General Electric CompanyInventors: Qiang Wang, Keith Matthew Jackson, Naresh Venkata Mantravadi
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Publication number: 20120292767Abstract: A method for fabricating an integrated circuit structure and the resulting integrated circuit structure are provided. The method includes forming a low-k dielectric layer; form an opening in the low-k dielectric layer; forming a barrier layer covering a bottom and sidewalls of the low-k dielectric layer; performing a treatment to the barrier layer in an environment comprising a treatment gas; and filling the opening with a conductive material, wherein the conductive material is on the barrier layer.Type: ApplicationFiled: July 30, 2012Publication date: November 22, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Ming Lee, Minghsing Tsai, Syun-Ming Jang
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Publication number: 20120295438Abstract: A copper interconnection structure includes an insulating layer, an interconnection body including copper and a barrier layer surrounding the interconnection body. The barrier layer includes a first barrier layer formed between a first portion of the interconnection body and the insulating layer. The first portion of the interconnection body is part of the interconnection body that faces the insulating layer. The barrier layer also includes a second barrier layer formed on a second portion of the interconnection body. The second portion of the interconnection body is part of the interconnection body not facing the insulating layer. Each of the first and the second barrier layers is formed of an oxide layer including manganese, and each of the first and the second barrier layers has a position where the atomic concentration of manganese is maximized in their thickness direction of the first and the second barrier layers.Type: ApplicationFiled: August 1, 2012Publication date: November 22, 2012Applicant: ADVANCED INTERCONNECT MATERIALS, LLCInventors: Junichi KOIKE, Akihiro SHIBATOMI
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Publication number: 20120292766Abstract: The present invention provides a semiconductor structure and a manufacturing method thereof. The method comprises: providing a semiconductor substrate comprising semiconductor devices; depositing a copper diffusion barrier layer on the semiconductor substrate; forming a copper composite layer on the copper diffusion barrier layer; decomposing the copper composite at corresponding positions, where copper interconnection is to be formed, into copper according to the shape of the copper interconnection; and etching off the undecomposed copper composite and the copper diffusion barrier layer underneath, to interconnect the semiconductor devices. The present invention is adaptive for manufacturing interconnection in integrated circuits.Type: ApplicationFiled: September 19, 2010Publication date: November 22, 2012Inventors: Huilong Zhu, Haizhou Yin, Zhijiong Luo
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Patent number: 8314021Abstract: A method for fabricating a semiconductor device includes: forming a thin film over trenches by using a first source gas and a first reaction gas; performing a first post-treatment on the thin film by using a second reaction gas; and performing a second post-treatment on the thin film by using a second source gas.Type: GrantFiled: November 3, 2010Date of Patent: November 20, 2012Assignee: Hynix Semiconductor Inc.Inventors: Jik-Ho Cho, Seung-Jin Yeom, Seung-Hee Hong, Nam-Yeal Lee
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Publication number: 20120289062Abstract: An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.Type: ApplicationFiled: July 30, 2012Publication date: November 15, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Yu Lo, Hung-Jung Tu, Hai-Ching Chen, Tien-I Bao, Wen-Chih Chiou, Chen-Hua Yu
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Publication number: 20120289043Abstract: A method for fabricating a damascene trench structure, wherein the method comprises steps as follows: A semiconductor structure having an inner layer dielectric (ILD) and a patterned hard mask stacked in sequence is firstly provided, in which a trench extends from the patterned hard mask downwards into the ILD. Subsequently, the patterned hard mask is etched in an atmosphere essentially consisting of nitrogen (N2) and carbon-fluoride compositions (CxFy).Type: ApplicationFiled: May 12, 2011Publication date: November 15, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ming-Da HSIEH, Yu-Tsung Lai, Jiunn-Hsiung Liao
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Patent number: 8310052Abstract: A semiconductor device includes: a trench formed on an interlayer insulating film on a semiconductor substrate; a first barrier metal film formed to cover the bottom and sidewalls of the trench, the first barrier metal film being comprised of an electric conductor containing a platinum-group element, a refractory metal, and nitrogen; and a metal film formed on the first barrier metal film in the trench. The amount of nitrogen decreases in the thickness direction of the first barrier metal film toward the metal film.Type: GrantFiled: November 19, 2010Date of Patent: November 13, 2012Assignee: Panasonic CorporationInventor: Naoki Torazawa
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Patent number: 8309456Abstract: A method for making an electrode in a semiconductor device. The method includes forming a trench in a first layer. The first layer is associated with a top surface, and the trench is associated with a bottom surface and a side surface. Additionally, the method includes depositing a diffusion barrier layer on at least the bottom surface, the side surface, and a part of the top surface, removing the diffusion barrier layer from at least a part of the bottom surface, depositing a seed layer on at least the part of the bottom surface and the diffusion barrier layer, and depositing an electrode layer on the seed layer.Type: GrantFiled: October 11, 2005Date of Patent: November 13, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventor: Ting Cheong Ang
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Publication number: 20120282768Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.Type: ApplicationFiled: July 17, 2012Publication date: November 8, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
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Patent number: 8304343Abstract: In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitridation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole.Type: GrantFiled: September 22, 2011Date of Patent: November 6, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-In Choi, Hyeon-Deok Lee, Gil-Heyun Choi, Jong-Myeong Lee
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Publication number: 20120273952Abstract: Microelectronic chip including a semiconductor substrate; at least one area of its surface which is suitable to be electrically connected to a metal frame designed to accommodate the chip; at least one interconnect area formed by a copper-based conductive layer and comprising a connecting device, the interconnect area being connected to the area by a conductor, wherein the area is formed by a layer forming a copper diffusion barrier inserted between interconnect area and the substrate.Type: ApplicationFiled: April 25, 2012Publication date: November 1, 2012Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.Inventors: Laurent Gay, Francois Guyader, Frederic Diette
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Publication number: 20120276738Abstract: A method for forming a TSV structure includes providing a silicon substrate with an interlayer dielectric layer formed thereon, forming a hard mask structure including a first hard mask layer including a metal element on the interlayer dielectric layer and a second hard mask layer on the first hard mask layer; forming an opening through the hard mask structure and the interlayer dielectric layer, the opening has a bottom and sidewalls in the silicon substrate. The method further includes depositing an insulating material on the hard mask structure and on the bottom and the sidewalls of the opening, subsequently removing the insulating material and the second hard mask layer until the first hard mask layer is exposed, and filling a conductive material into the opening. The method also includes removing the conductive material and the first hard mask layer by a CMP process until the interlayer dielectric layer is exposed.Type: ApplicationFiled: November 23, 2011Publication date: November 1, 2012Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventor: ZHONGSHAN HONG
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Publication number: 20120273851Abstract: A manufacturing method of a semiconductor device includes forming a structure comprising an interlayer dielectric layer on a substrate, an ultra-low-k material layer on the interlayer dielectric layer and a plug. The plug passes through the interlayer dielectric layer and the ultra-low-k material layer, and is formed of a first metal material. The method further includes removing an upper portion of the plug by etching to form a recessed portion, and filling the recessed portion with a second metal material. According to the method, contact-hole photolithography is performed only once, and thus avoids alignment issues that may occur when contact-hole photolithography needs to be performed twice.Type: ApplicationFiled: February 16, 2012Publication date: November 1, 2012Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventor: ZHONGSHAN HONG
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Publication number: 20120276737Abstract: A method for post-etching treatment of copper interconnecting wires that are used to electrically couple an upper interconnecting layer with a lower interconnecting layer includes forming the lower interconnecting layer on a substrate, and forming the upper interconnecting layer on the lower interconnecting layer. The lower interconnecting layer includes a first dielectric layer, a plurality of wire trenches formed in the first dielectric layer and being filled with copper, and a first top barrier layer overlying the first dielectric layer and the wire trenches. The upper interconnecting layer includes a second dielectric layer on the top barrier layer, and a plurality of vias extending through the second dielectric layer and the top barrier layer and exposing the copper in the wire trenches. The method further includes treating the exposed copper using a plasma process comprising NH3.Type: ApplicationFiled: November 23, 2011Publication date: November 1, 2012Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: DONGJIANG WANG, Junqing Zhou, Haiyang Zhang
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Patent number: 8298934Abstract: The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer.Type: GrantFiled: June 7, 2011Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Jeffery B. Maxson, Cung Do Tran, Huilong Zhu
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Patent number: 8298937Abstract: An interconnect structure within a microelectronic structure and a method for fabricating the interconnect structure within the microelectronic structure use a developable bottom anti-reflective coating layer and at least one imageable inter-level dielectric layer located thereupon over a substrate that includes a base dielectric layer and a first conductor layer located and formed embedded within the base dielectric layer. Incident to use of the developable bottom anti-reflective coating layer and the at least one imageable inter-level dielectric layer, an aperture, such as but not limited to a dual damascene aperture, may be formed through the at least one imageable inter-level dielectric layer and the developable anti-reflective coating layer to expose a capping layer located and formed upon the first conductor layer, absent use of a dry plasma etch method when forming the interconnect structure within the microelectronic structure.Type: GrantFiled: June 12, 2009Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Maxime Darnon, Jeffrey P. Gambino, Elbert E. Huang, Qinghuang Lin
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Publication number: 20120270389Abstract: A method for manufacturing a metal nitride layer including the following steps is provided. Firstly, a substrate is provided. Then, a physical vapor deposition process is performed at a temperature between 210° C. and 390° C. to form a metal nitride layer on the substrate. Also, the physical vapor deposition process can be performed on a pressure between 21 mTorr and 91 mTorr. The method can be used in the manufacturing process of an interconnection structure for decreasing the film stress of the metal nitride layer. Therefore, the interconnection structure can be prevented from line distortion and film collapse.Type: ApplicationFiled: April 20, 2011Publication date: October 25, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ling LIN, Chin-Fu Lin, Chi-Mao Hsu
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Publication number: 20120270392Abstract: A fabricating method of an active device array substrate is provided. The active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.Type: ApplicationFiled: June 29, 2012Publication date: October 25, 2012Applicant: AU OPTRONICS CORPORATIONInventors: Po-Lin Chen, Chih-Yuan Lin, Yu-Min Lin, Chun-Nan Lin
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Publication number: 20120267785Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.Type: ApplicationFiled: June 26, 2012Publication date: October 25, 2012Inventors: Hyeok-Sang Oh, Woo-Jin Jang, Bum-Ki Moon, Ji-Hong Choi, Minseok Oh, Tien-Jen Cheng
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Publication number: 20120270391Abstract: Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method disclosed herein includes forming a layer of isolation material above a via opening formed in a semiconductor device, the via opening extending into a substrate of the semiconductor device. The method also includes performing a first planarization process to remove at least an upper portion of the layer of isolation material formed outside of the via opening, and forming a conductive via element inside of the via opening after performing the first planarization process.Type: ApplicationFiled: April 21, 2011Publication date: October 25, 2012Applicant: GLOBALFOUNDRIES SINGAPORE PTE LTDInventors: Chen Zengxiang, Zhao Feng, Liu Huang, Yuan Shaoning
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Publication number: 20120264290Abstract: Methods, apparatus, and systems for depositing copper and other metals are provided. In some implementations, a wafer substrate is provided to an apparatus. The wafer substrate has a surface with field regions and a feature. A copper layer is plated onto the surface of the wafer substrate. The copper layer is annealed to redistribute copper from regions of the wafer substrate to the feature. Implementations of the disclosed methods, apparatus, and systems allow for void-free bottom-up fill of features in a wafer substrate.Type: ApplicationFiled: May 16, 2011Publication date: October 18, 2012Inventors: Jonathan D. REID, Huanfeng ZHU
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Publication number: 20120261823Abstract: A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.Type: ApplicationFiled: June 23, 2012Publication date: October 18, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew E. Colburn, Satya V. Nitta, Sampath Purushothaman, Charles Black, Kathryn Guarini
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Publication number: 20120264291Abstract: Embodiments of the invention described herein generally provide methods and apparatuses for forming cobalt silicide layers, metallic cobalt layers, and other cobalt-containing materials. In one embodiment, a method for forming a cobalt silicide containing material on a substrate is provided which includes exposing a substrate to at least one preclean process to expose a silicon-containing surface, depositing a cobalt silicide material on the silicon-containing surface, depositing a metallic cobalt material on the cobalt silicide material, and depositing a metallic contact material on the substrate. In another embodiment, a method includes exposing a substrate to at least one preclean process to expose a silicon-containing surface, depositing a cobalt silicide material on the silicon-containing surface, expose the substrate to an annealing process, depositing a barrier material on the cobalt silicide material, and depositing a metallic contact material on the barrier material.Type: ApplicationFiled: April 20, 2012Publication date: October 18, 2012Applicant: Applied Materials, Inc.Inventors: Seshadri Ganguli, Schubert S. Chu, Mei Chang, Sang-Ho Yu, Kevin Moraes, See-Eng Phan
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Publication number: 20120264292Abstract: A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier layer is located within an opening that is located within a dielectric material and it is between a diffusion barrier layer and a conductive material which are also present within the opening. The redundant diffusion barrier includes a single layered or multilayered structure comprising Ru and a Co-containing material including pure Co or a Co alloy including at least one of N, B and P.Type: ApplicationFiled: June 21, 2012Publication date: October 18, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Chao Yang, Thomas M. Shaw
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Publication number: 20120261817Abstract: A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.Type: ApplicationFiled: June 28, 2012Publication date: October 18, 2012Applicant: STATS ChipPAC, Ltd.Inventors: Byung Tai Do, Stephen A. Murphy, Yaojian Lin, Heap Hoe Kuan, Pandi Chelvam Marimuthu, Hin Hwa Goh
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Publication number: 20120261827Abstract: A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.Type: ApplicationFiled: April 13, 2011Publication date: October 18, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua YU, Cheng-Hung CHANG, Ebin LIAO, Chia-Lin YU, Hsiang-Yi WANG, Chun Hua CHANG, Li-Hsien HUANG, Darryl KUO, Tsang-Jiuh WU, Wen-Chih CHIOU
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Patent number: 8288276Abstract: Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.Type: GrantFiled: December 30, 2008Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Veeraraghavan S. Basker, William Tonti, Keith Kwong Hon Wong
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Publication number: 20120258589Abstract: A method of fabricating a through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage.Type: ApplicationFiled: June 13, 2012Publication date: October 11, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard P. Volant, Mukta G. Farooq, Paul F. Findeis, Kevin S. Petrarca
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Publication number: 20120258590Abstract: A method includes forming conductive material in a contact hole and a TSV opening, and then performing one step to remove portions of the conductive material outside the contact hole and the TSV opening to leave the conductive material in the contact hole and the TSV opening, thereby forming a contact plug and a TSV structure, respectively. In some embodiments, the removing step is performed by a CMP process.Type: ApplicationFiled: June 19, 2012Publication date: October 11, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Fa CHEN, I-Ching LIN