Abstract: A device and method of forming fluoride metal barriers at an interface of a fluorinated low-K dielectric and Cu or Cu alloy interconnects is disclosed. The fluoride metal barriers may prevent interconnects from reacting with the fluorinated low-K dielectric. The method may include depositing a thin film of metal or metal alloy on the fluorinated low-K dielectric. The thin film may include a metal or metal alloying element that reacts with free fluorine and/or fluorine compounds from the fluorinated low-K dielectric to form fluoride metal barriers.

Abstract: Plug contacts may be formed with barrier layers having thicknesses of less than 50 ? in some embodiments. In one embodiment, the barrier layer may be formed by the chemical vapor deposition of diborane, forming a boron layer between a metallic contact and the surrounding dielectric and between a metallic contact and the substrate and/or substrate contact. This boron layer may be substantially pure boron and boron silicide.

Abstract: A through-silicon via fabrication method comprises forming a substrate by bonding the front surface of a silicon plate to a carrier using an adhesive layer therebetween to expose the back surface of the silicon plate. A silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. A plurality of through holes are etched in the silicon plate, the through holes comprising sidewalls and bottom walls. A metallic conductor is deposited in the through holes to form a plurality of through-silicon vias.

Abstract: Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming desired device regions with contacts on the front surface of an initially relatively thick wafer; etching via cavities partly through the wafer in the desired locations; filling the via cavities with a conductive material coupled to some device region contacts; mounting the wafer with its front side facing a support structure; thinning the wafer from the back side to expose internal ends of the conductive material filled vias; applying any desired back-side interconnect region coupled to the exposed ends of the filled vias; removing the support structure and separating the individual device or IC assemblies so as to be available for mounting on a further circuit board, tape or larger circuit.

Abstract: The invention relates to an electronic component having a GaAs semiconductor substrate (HS), semiconductor components (BE) being implemented on the front side thereof, and the back side thereof having a multilayer backside metallization (RM), wherein an advantageous construction of the layer sequence of the backside metallization is proposed, the backside metallization in particular comprising an Au layer as a bonding layer.

Abstract: Embodiments described herein generally provide methods for reducing undesired low-k damages during a damascene process using a sacrificial dielectric material and optionally a barrier/capping layer. In one embodiment, a damascene structure is formed through a sacrificial dielectric material deposited over a dielectric base layer. The damascene structure is filled with a suitable metal such as copper. The sacrificial dielectric material filled in trench areas between the copper damascene is then removed, followed by a barrier/cap layer which conformally or selectively covers exposed surfaces of the copper damascene structure. Ultra low-k dielectric materials may then fill the trench areas that were previously filled with sacrificial dielectric material. The invention prevents the ultra low-k material between the metal lines from exposing to various damaging processes during a damascene process such as etching, stripping, wet cleaning, pre-metal cleaning or CMP process.

Abstract: Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.

Abstract: A method of forming a metal interconnection of semiconductor device is provided. The method includes forming a low-k dielectric layer including an opening; forming a barrier metal pattern conformally covering a bottom surface and an inner sidewall of the opening; forming a metal pattern exposing a part of the inner sidewall of the barrier metal pattern in the opening; forming a metal capping layer on the top surfaces of the metal pattern and the low-k dielectric layer using a selective chemical vapor deposition process, wherein the thickness of the metal capping layer on the metal pattern is greater than the thickness of the metal capping layer on the low-k dielectric layer; and forming a metal capping pattern covering the top surface of the metal pattern by planarizing the metal capping layer down to the top surface of the low-k dielectric layer.

Abstract: A plasma nitriding method includes placing, in a processing chamber, a target object having a structure including a first portion containing a metal and a second portion containing silicon to expose surfaces of the first and the second portion; and performing a plasma process on the target object to selectively nitride the surface of the first portion such that a metal nitride film is selectively formed on the surface of the first portion. Further, the first portion contains tungsten, and a nitrogen-containing plasma is generated by supplying a nitrogen-containing gas into the processing chamber and setting an internal pressure of the processing chamber in a range from 133 Pa to 1333 Pa. The surface of the first portion is selectively nitrided without nitriding the surface of the second portion by the nitrogen-containing plasma such that a tungsten nitride film is formed on the surface of the first portion.

Abstract: The present invention is a method for manufacturing a semiconductor device having a conductor and an insulating film on a substrate, the method including the steps of forming the conductor on the substrate, forming the insulating film on the conductor, removing the insulating film on the conductor, and blowing an organosilane gas and a hydrogen gas to reduce an oxidized region on the conductor, wherein the oxidized region on the conductor is formed when the insulating film is removed.

Abstract: In a modern 0.15 ?m power MOSFET, aluminum voids (voids formed in an aluminum-type electrode) are generated frequently in trench portions (source contact trenches) caused by the reduction of a cell pitch for refinement. It is considered to be attributable to the defects which are generated mainly due to a sudden increase of the aspect ratio from 0.84 in the previous generation to 2.8 in the current generation. Accordingly, concave portions of repetitive trenches having a high aspect ratio are filled with an aluminum-type metal by ionized sputtering throughout the processing, from the formation to the filling of an aluminum-type metal seed film.

Abstract: Embodiments of methods for forming Cu diffusion barriers for semiconductor interconnect structures are provided. The method includes oxidizing an exposed outer portion of a copper line that is disposed along a dielectric substrate to form a copper oxide layer. An oxide reducing metal is deposited onto the copper oxide layer. The copper oxide layer is reduced with at least a portion of the oxide reducing metal that oxidizes to form a metal oxide barrier layer. A dielectric cap is deposited over the metal oxide barrier layer.

Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a method for forming a via structure includes forming a via in a semiconductor substrate, wherein via sidewalls of the via are defined by the semiconductor substrate; forming a dielectric layer on the via sidewalls; removing the dielectric layer from a portion of the via sidewalls; and forming a conductive layer to fill the via, wherein the conductive layer is disposed over the dielectric layer and the portion of the via sidewalls. In an example, the dielectric layer is an oxide layer.

Abstract: Adhesive layers residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Adhesion layers are formed by depositing a precursor layer of metal-containing material (e.g., material containing Al, Ti, Ca, Mg, etc.) over an exposed copper line, and converting the precursor layer to a passivated layer (e.g., nitridized layer). For example, a substrate containing exposed copper line having exposed Cu—O bonds is contacted with trimethylaluminum to form a precursor layer having Al—O bonds and Al—C bonds on copper surface. The precursor layer is then treated to remove residual organic substituents and to form Al—N, Al—H bonds or both. The treatment can include direct plasma treatment, remote plasma treatment, UV-treatment, and thermal treatment with a gas such as NH3, H2, N2, and mixtures thereof. A dielectric diffusion barrier layer is then deposited.

Abstract: An interconnect structure and method for forming a multi-layered seed layer for semiconductor interconnections are disclosed. Specifically, the method and structure involves utilizing sequential catalytic chemical vapor deposition, which is followed by annealing, to form the multi-layered seed layer of an interconnect structure. The multi-layered seed layer will improve electromigration resistance, decrease void formation, and enhance reliability of ultra-large-scale integration (ULSI) chips.

Abstract: The invention provides a method of forming a film stack on a substrate, comprising performing a silicon containing gas soak process to form a silicon containing layer over the substrate, reacting with the silicon containing layer to form a tungsten silicide layer on the substrate, depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer.

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

Abstract: A method of forming a semiconductor device is disclosed. A dielectric layer having a opening therein is formed on a semiconductor substrate. An inner surface of the opening is treated by plasma. A barrier metal layer is formed on the plasma-treated inner surface of the opening. A seed layer is formed on the barrier metal layer. A metal bulk layer is formed on the seed layer. High quality semiconductor devices can be fabricated by using these methods, which may stably fill the opening formed in the dielectric layer.

Abstract: A copper interconnection structure includes an insulating layer, an interconnection body including copper and a barrier layer surrounding the interconnection body. The barrier layer includes a first barrier layer formed between a first portion of the interconnection body and the insulating layer. The first portion of the interconnection body is part of the interconnection body that faces the insulating layer. The barrier layer also includes a second barrier layer formed on a second portion of the interconnection body. The second portion of the interconnection body is part of the interconnection body not facing the insulating layer. Each of the first and the second barrier layers is formed of an oxide layer including manganese, and each of the first and the second barrier layers has a position where the atomic concentration of manganese is maximized in their thickness direction of the first and the second barrier layers.

Abstract: In a film forming method for forming a Co film on a substrate provided in a processing chamber, gaseous Co4(CO)12 as a single film forming material is supplied into the processing chamber. Then, the gaseous Co4(CO)12 is thermally decomposed on the substrate to form the Co film on the substrate.

Abstract: A semiconductor process is described. A substrate with at least one conductive region is provided, on which a dielectric layer is formed. An opening is formed in the dielectric layer, such that the conductive region is exposed. A first conductive layer is conformally formed on the surface of the opening. A first cleaning step is conducted using a first cleaning solution. A baking step is conducted after the first cleaning step. Afterwards, the opening is filled with a second conductive layer.

Abstract: A metal thin film forming method includes depositing a Ti film on an insulating film formed on a substrate and depositing a Co film on the Ti film. The film forming method further includes modifying a laminated film of the Ti film and the Co film on the insulating film to a metal thin film containing Co3Ti alloy by heating the laminated film in an inert gas atmosphere or a reduction gas atmosphere.

Abstract: A method of fabricating a semiconductor device is provided. The method may include preparing a substrate having a first surface and a second surface, forming a via hole exposing at least a portion of the substrate from the first surface of the substrate, forming a first insulating film on an inner wall of the via hole, forming a conductive connection part filling an inside of the via hole including the first insulating film, polishing the second surface of the substrate until the conductive connection part is exposed, and selectively forming a second insulating film on the second surface of the substrate using an electrografting method to expose the conductive connection part.

Abstract: When a barrier film is formed on an exposed surface of an interlayer insulation film on a substrate, the interlayer insulation film having a recess formed therein, and a metal wiring to be electrically connected to a metal wiring in a lower layer is formed in the recess, a barrier film having an excellent step coverage can be formed and increase of a wiring resistance can be restrained. An oxide film on a surface of the lower copper wiring exposed to a bottom surface of the interlayer insulation film is reduced or edged so as to remove oxygen on the surface of the copper wiring. Then, by supplying an organic metal compound containing manganese and containing no oxygen, generation of manganese oxide as a self-forming barrier film is selectively allowed on an area containing oxygen, such as a sidewall of the recess and a surface of the interlayer insulation film, while generation of the manganese oxide is not allowed on the surface of the copper wiring. Thereafter, copper is embedded in the recess.

Abstract: A method of processing a microfeature workpiece generally includes depositing a first conducting layer, at least partially reducing oxides on the first conducting layer to provide a reduced first conducting layer, and exposing the reduced first conducting layer to a substantially oxygen-free environment to provide a passivated first conducting layer. A microfeature workpiece generally includes a first conducting layer, a monolayer directly on the first conducting layer, and a second conducting layer.

Abstract: The disclosure provides mechanisms of performing metal chemical-mechanical polishing (CMP) without significant loss of copper and a dielectric film of damascene structures. The mechanisms use a metal CMP stop layer made of a low-k dielectric film with a porogen, which significantly reduces the removal rate of the metal CMP stop layer by metal CMP. The metal CMP stop layer is converted into a porous low-k dielectric film after a cure (or curing) to remove or convert the porogen. The low-k value, such as equal to or less than about 2.6, of the metal CMP stop layer makes the impact of using of the metal CMP stop layer on RC delay from minimum to none. Further the CMP stop layer protects the porous low-k dielectric film underneath from exposure to water, organic compounds, and mobile ions in the CMP slurry.

Abstract: On a surface of an object to be treated, a Mn-containing thin film or CuMn-containing alloy thin film is formed by heat treatment (CVD or ALD) by using a Mn-containing source gas (or Mn-containing source gas and a Cu-containing gas) and an oxygen-containing gas (for instance, water vapor) as a processing gas. The Mn-containing thin film or the CuMn-containing alloy thin film can be formed with high step coverage in a fine recess formed on the surface of the object to be treated.

Abstract: A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier layer is located within an opening that is located within a dielectric material and it is between a diffusion barrier layer and a conductive material which are also present within the opening. The redundant diffusion barrier includes a single layered or multilayered structure comprising Ru and a Co-containing material including pure Co or a Co alloy including at least one of N, B and P.

Abstract: To provide a technology capable of preventing corrosion of a Cu wiring and thereby improving a production yield of a semiconductor device, a manufacturing method of a semiconductor device includes the steps of: removing a portion of a Cu film other than that in a wiring trench in a semiconductor substrate by CMP using a polishing slurry, removing a portion of a barrier metal film other than that in the, wiring trench by CMP using a polishing slurry containing an anticorrosive, polishing the surface of the Cu film and the surface of the barrier metal film by CMP using pure water, thereafter cleaning the semiconductor substrate with pure water without applying an anticorrosive thereto or without cleaning it with a chemical liquid, and thereafter cleaning the semiconductor substrate with a chemical liquid without applying an anticorrosive thereto.

Abstract: In a formation process of a semi-global interconnect in a Cu damascene multilayer wiring structure, it is the common practice, upon formation of the damascene wiring structure, to remove an etch stop insulating film from a via bottom by dry etching and then carry out nitrogen plasma treatment to reduce carbon deposits on the surface of the via bottom. Study by the present inventors has revealed that when a sequence of successive discharging for the removal of electrostatic charge by using nitrogen plasma and transportation of the wafer is performed, a Cu hollow is generated on the via bottom at the end of the via chain coupled to a pad lead interconnect having a length not less than a threshold value.

Abstract: In a copper-based metallization system of a semiconductor device the contact pad, such as a bond pad, is formed on the basis of two lithography steps by depositing the cap metal layer stack directly on any exposed copper surface areas of the last metallization layer. After patterning of the cap layer stack therefore reliable confinement of any exposed metal region is accomplished on the basis of a conductive barrier material, while the actual passivation materials are formed and patterned subsequently, thereby avoiding any negative influence on these materials, as may be the case in some conventional approaches. Moreover, superior mechanical integrity of the contact pad in combination with superior electrical performance of any metal region in the last metallization layer is achieved.

Abstract: According to an embodiment, a semiconductor device includes a first wiring member, an opening portion and an electrode terminal portion. The first wiring member is provided on a first interlayer insulating film on a semiconductor substrate and used as a wiring layer. The opening portion is provided in a second interlayer insulating film on the first wiring member. The electrode terminal portion is provided on the opening portion and the second interlayer insulating film around the opening portion. In the electrode terminal portion, a barrier metal film in contact with the first wiring member, a seed metal film and a second wiring member are stacked and thus formed in such a manner as to cover the opening portion, and a coating metal film is formed on an upper portion and a side surface of the second wiring member.

Abstract: A rewiring is formed by forming a Cu seed layer of copper over an opening and insulating films, forming a photoresist film over the Cu seed layer, a step of forming copper film by plating-growth over the Cu seed layer, and forming a Ni film. After forming an Au film in an opening (pad region) over the rewiring, the photoresist film is removed and passivation processing is performed on the Ni film. Then, the Cu seed layer other than the formation region of the rewiring is etched. According to these steps, a passivation film is formed on the surface of the Ni film and the reduction in film thickness of the Ni film by the etching can be reduced. Furthermore, it is possible to reduce trouble due to distortion of a substrate resulting from an increase in thickness of the Ni film in view of reduction in film thickness.

Abstract: A method of forming a Cu wiring in a trench or hole formed in a substrate is provided. The method includes forming a barrier film on the surface of the trench or hole, forming a Ru film on the barrier film, and embedding copper in the trench or hole by forming a Cu film on the Ru film using PVD while heating the substrate such that migration of copper into the trench or hole occurs.

Abstract: A method of forming a semiconductor device includes, but is not limited to, the following processes. A first interlayer insulating film is formed. A hole is formed in the first interlayer insulating film. A second interlayer insulating film is formed, which buries the hole and covers the first interlayer insulating film. An interconnect groove is formed by selectively etching the second interlayer insulating film to leave the second interlayer insulating film in the hole. The second interlayer insulating film in the hole is removed.

Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

Abstract: Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad.

Abstract: An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.

Abstract: A method for filling a gap includes: providing a semiconductor substrate, at least having an metal interconnect layer and an insulating dielectric layer on top of the underlying metal interconnect layer, the insulating dielectric layer having a gap; forming a diffusion bather layer and a seed layer sequentially in the gap and on a surface of the insulating dielectric layer outside the gap; forming a mask layer on a surface of the seed layer outside of the gap; and depositing a metal layer on the semiconductor substrate with the mask layer, the metal layer filling the gap.

Abstract: A method for manufacturing a semiconductor device is disclosed in which, after semiconductor function regions and patterns of interlayer insulating films including required contact holes are formed on one main surface side of a semiconductor substrate, an aluminum film or an aluminum alloy film which is thick is formed all over the main surface side of the semiconductor substrate and brought into conductive contact with the surface of the semiconductor substrate including bottom surfaces of the contact holes so as to form a required electrode film. Formation of the aluminum film or the aluminum alloy film is divided into a plurality of steps so that the thickness of the aluminum film or the aluminum alloy film is formed gradually, and between every two of the plurality of steps of forming the aluminum film or the aluminum alloy film, there is provided a step of performing isotropic etching to flatten irregularities in a surface of the aluminum film or the aluminum alloy film formed in the previous step.

Abstract: In sophisticated semiconductor devices, superior contact resistivity may be accomplished for a given contact configuration by providing hybrid contact elements, at least a portion of which may be comprised of a highly conductive material, such as copper. To this end, a well-established contact material, such as tungsten, may be used as buffer material in order to preserve integrity of sensitive device areas upon depositing the highly conductive metal.

Abstract: Semiconductors are electrochemically etched in solutions containing sources of bifluoride and nickel ions. The electrochemical etching may form pores in the surface of the semiconductor in the nanometer range. The etched semiconductor is then nickel plated.

Abstract: An interconnect structure for integrated circuits incorporates manganese silicate and manganese silicon nitride layers that completely surrounds copper wires in integrated circuits and methods for making the same are provided. The manganese silicate forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The manganese silicate and manganese silicon nitride also promote strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use. The strong adhesion at the copper-manganese silicate and manganese silicon nitride interfaces also protect against failure by electromigration of the copper during use of the devices. The manganese-containing sheath also protects the copper from corrosion by oxygen or water from its surroundings.

Abstract: To provide a display device which can be manufactured with higher efficiency in the use of material through a simplified manufacturing process, and a method for manufacturing the display device. Another object is to provide a technique by which patterns of a wiring the like which constitutes the display device can be formed to a desired shape with good control. In a method for forming a pattern according to the present invention, a mask is formed over a light-transmitting substrate; a first region including a photocatalyst is formed over the substrate and the mask; the photocatalyst is irradiated with light through the substrate to modify a part of the first region; a second region is formed; and a composition containing a pattern forming material is discharged to the second region, thus, a pattern is formed. The mask does not transmit light.

Abstract: A thick metal layer is formed on a semiconductor integrated circuit in multiple different deposition chambers. A first portion of the metal layer is formed in a first deposition chamber, the first thickness being approximately half the target thickness. The substrate is then removed from the first chamber and transported to a second chamber. The deposition of the same metal layer continues in a second chamber, having the same grain structure and orientation. The second portion of the metal layer is grown to achieve the final thickness. By using two different deposition chambers to form the single metal layer, layers in excess of 25,000 angstroms in thickness can be obtained.

Abstract: A method for improving the within die uniformity of the metal plug CMP process in the gate last route is provided. Before performing the CMP process for forming the metal plug, a metal etching process is applied, so that the step height between the metal layers in the contact hole area and the non-contact hole area is greatly reduced. Therefore, the relatively small step height will exert a significantly less effect on the following CMP process, so that the step height will be limitedly transferred to the top of metal plug after finishing CMP process. In this way, the recess on top of the metal plug is largely reduced, so that a flat top of the metal plug is obtained, and within die uniformity and electrical properties the device are improved.

Abstract: A through substrate via (TSV) die includes a substrate including a topside semiconductor surface having active circuitry. The die includes a plurality of TSVs that each include an inner metal core that extend from the topside semiconductor surface to protruding TSV tips that extend out from the bottomside surface. A metal cap is on the protruding TSV tips that includes at least one metal layer that has a metal that is not in the inner metal core. A plurality of protruding warpage control features are on the bottomside surface lateral to the protruding TSV tips, wherein the plurality of protruding warpage control features do not have the protruding TSV tips thereunder. The plurality of protruding warpage control features can include the same metal layer(s) used for the metal cap.

Abstract: A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous.

Abstract: An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating.