Abstract: A semiconductor device having metamorphic high electron mobility transistor (HEMT)-heterojunction bipolar transistor (HBT) integration on a semiconductor substrate. An example semiconductor device generally includes a semiconductor substrate, a bipolar junction transistor (BJT) disposed above the semiconductor substrate and comprising indium, and a HEMT disposed above the semiconductor substrate and comprising indium.

Abstract: An integrated circuit die having a substrate with a first device stack disposed upon the substrate and a second device stack spaced from the first device stack and disposed upon the substrate is disclosed. The second device stack includes a first portion of a channel layer and a threshold voltage shift layer disposed between the first portion of the channel layer and the substrate, wherein the threshold voltage shift layer is configured to set a threshold voltage that is a minimum device control voltage required to create a conducting path within the first portion of the channel layer.

Abstract: A field-effect transistor with protection diodes includes: a field-effect transistor; and a two-terminal electrostatic protection circuit connected between a gate and a source of the field-effect transistor, wherein the two-terminal electrostatic protection circuit comprises: a first diode that is positioned on a reverse-biased side when a voltage lower than a potential of the source is applied to the gate and has a reverse withstand voltage lower than a reverse withstand voltage between the gate and the source of the field-effect transistor; a second diode that is positioned on a forward-biased side when a voltage lower than a potential of the source is applied to the gate and is connected in anti-series to the first diode; and a resistor that is connected in series to a diode pair comprising the first diode and the second diode and formed using a same channel layer as that of the field-effect transistor.

Abstract: A heterojunction bipolar transistor (HBT) thermal sensing device includes a well structure as a layer between an HBT sub-collector and an HBT substrate. In one instance, the HBT sub-collector contacts an emitter, a collector, and a base of the HBT thermal sensing device. The HBT thermal sensing device also includes a first side electrode in electrical contact with the quantum well structure and a second side electrode in electrical contact with the quantum well structure.

Abstract: A semiconductor device includes a quantum well-modulated bipolar junction transistor (QW-modulated BJT) having a base with an area for a modulatable quantum well in the base. The QW-modulated BJT includes a quantum well (QW) control node which is capable of modulating a quantity and level of energy levels of the quantum well. A recombination site abuts the area for the quantum well with a contact area of at least 25 square nanometers. The semiconductor device may be operated by providing a reference node such as ground to the emitter and a power source to the collector. A bias voltage is provided to the gate to form the quantum well and a signal voltage is provided to the gate, so that the collector current includes a component which varies with the signal.

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract: In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed.

Abstract: An intermediate layer composed of i-AlN is formed between a channel layer and an electron donor layer, a first opening is formed in an electron donor layer, at a position where a gate electrode will be formed later, while using an intermediate layer as an etching stopper, a second opening is formed in the intermediate layer so as to be positionally aligned with the first opening, by wet etching using a hot phosphoric acid solution, and a gate electrode is formed so that the lower portion thereof fill the first and second openings while placing a gate insulating film in between, and so that the head portion thereof projects above the cap structure.

Abstract: A method for manufacturing a plurality light emitting diodes includes providing a gallium nitride containing bulk crystalline substrate material configured in a non-polar or semi-polar crystallographic orientation, forming an etch stop layer, forming an n-type layer overlying the etch stop layer, forming an active region, a p-type layer, and forming a metallization. The method includes removing a thickness of material from the backside of the bulk gallium nitride containing substrate material. A plurality of individual LED devices are formed from at least a sandwich structure comprising portions of the metallization layer, the p-type layer, active layer, and the n-type layer. The LED devices are joined to a carrier structure.

Abstract: A gallium nitride crystal with a polyhedron shape having exposed {10-10} m-planes and an exposed (000-1) N-polar c-plane, wherein a surface area of the exposed (000-1) N-polar c-plane is more than 10 mm2 and a total surface area of the exposed {10-10} m-planes is larger than half of the surface area of (000-1) N-polar c-plane. The GaN bulk crystals were grown by an ammonothermal method with a higher temperature and temperature difference than is used conventionally, and using an autoclave having a high-pressure vessel with an upper region and a lower region. The temperature of the lower region of the high-pressure vessel is at or above 550° C., the temperature of the upper region of the high-pressure vessel is set at or above 500° C., and the temperature difference between the lower and upper regions is maintained at or above 30° C. GaN seed crystals having a longest dimension along the c-axis and exposed large area m-planes are used.

Abstract: Provided are an image sensor and a method of sensing the same. The image sensor includes: a light receiving device; a signal conversion unit including a transfer transistor having a plurality of transfer gates and for converting photocharges generated by the light receiving device into a voltage to output the voltage; and a sensing control unit for generating at least two reset signals and/or at least two transfer signals applied to the transfer gates of the transfer transistor during a one-time photosensing cycle. The image sensor is obtained by changing the structure and driving method of a transfer transistor of a typical 4-transistor CMOS image sensor and employs a deep depletion operation and a multiple reset operation, thereby reducing an image lag and increasing the well capacity of the light receiving device.

Abstract: A method of fabricating a light emitting diode array, comprising: providing a temporary substrate; forming a first light emitting stack and a second light emitting stack on the temporary substrate; forming a first insulating layer covering partial of the first light emitting stack; forming a wire on the first insulating layer and electrically connecting to the first light emitting stack and the second light emitting stack; forming a second insulating layer fully covering the first light emitting stack, the wire and partial of the second light emitting stack; forming a metal connecting layer on the second insulating layer and electrically connecting to the second light emitting stack; forming a conductive substrate on the metal connecting layer; removing the temporary substrate; and forming a first electrode connecting to the first light emitting stack.

Abstract: An MMIC 100 is a semiconductor device which includes an FET formed on a GaAs substrate 10 and an MIM capacitor having a dielectric layer 20b arranged between a lower electrode 18b and an upper electrode 22b. A method for manufacturing the MMIC 100 is provided, in which a source electrode 16a and a drain electrode 16b of the FET are formed and then a gate electrode 18a of the FET and a lower electrode 18b of the MIM capacitor are formed simultaneously by the lift-off method.

Abstract: Ge/Si and other nonsilicon film heterostructures are formed by hydrogen-induced exfoliation of the Ge film which is wafer bonded to a cheaper substrate, such as Si. A thin, single-crystal layer of Ge is transferred to Si substrate. The bond at the interface of the Ge/Si heterostructures is covalent to ensure good thermal contact, mechanical strength, and to enable the formation of an ohmic contact between the Si substrate and Ge layers. To accomplish this type of bond, hydrophobic wafer bonding is used, because as the invention demonstrates the hydrogen-surface-terminating species that facilitate van der Waals bonding evolves at temperatures above 600° C. into covalent bonding in hydrophobically bound Ge/Si layer transferred systems.

Abstract: A substrate with a nitride semiconductor layer is cleaved to form resonator end faces, on which a coating film is formed so as to make a nitride semiconductor laser bar. This is divided into nitride semiconductor laser elements. Prior to forming the coating film on the resonator end face, the resonator end face is exposed to a plasma atmosphere generated from the gas containing nitrogen gas.

Abstract: A method of making a nitride semiconductor substrate having the steps of providing a free-standing substrate that is of a nitride semiconductor and has one of a penetrating pit and a penetrating crack that penetrate from a top surface to a back surface of the free-standing substrate, attaching a metal to the penetrating pit or the penetrating crack, the metal being adapted to be nitrided, and nitriding the metal to form a nitride that seals the penetrating pit or the penetrating crack. A nitride semiconductor substrate has a free-standing substrate that is formed of a nitride semiconductor and has one of a penetrating pit and a penetrating crack that penetrate from a top surface to a back surface of the free-standing substrate, and a metal nitride that seals the penetrating pit or the penetrating crack. The metal nitride is formed of GaN, InN and AlN.

Abstract: A wafer comprising at least one high Ft HBT and at least one high BVceo HBT having various collector profiles on a common III-V compound semiconductor based wafer. The N+ implant in the collector varies the collector profiles of individual HBTs on the wafer. The method for preparing the device comprises forming of HBT layers up to and including collector layer on non-silicon based substrate, performing ion implantation, annealing for implant activation, and forming remaining HBT layers.

Abstract: A compound semiconductor substrate manufacturing method suitable for manufacturing a compound semiconductor element having high electrical characteristics. The compound semiconductor substrate manufacturing method is a method for manufacturing a compound semiconductor substrate having pn junction, including an epitaxial growing process, a selective growing process and other discretionary processes after the epitaxial growing process. The highest temperatures in the selective growing process and other discretionary processes after the epitaxial growing process are lower than that in the epitaxial growing process prior to the selective growing process.

Abstract: To increase the lattice constant of AlInGaP LED layers to greater than the lattice constant of GaAs for reduced temperature sensitivity, an engineered growth layer is formed over a substrate, where the growth layer has a lattice constant equal to or approximately equal to that of the desired AlInGaP layers. In one embodiment, a graded InGaAs or InGaP layer is grown over a GaAs substrate. The amount of indium is increased during growth of the layer such that the final lattice constant is equal to that of the desired AlInGaP active layer. In another embodiment, a very thin InGaP, InGaAs, or AlInGaP layer is grown on a GaAs substrate, where the InGaP, InGaAs, or AlInGaP layer is strained (compressed). The InGaP, InGaAs, or AlInGaP thin layer is then delaminated from the GaAs and relaxed, causing the lattice constant of the thin layer to increase to the lattice constant of the desired overlying AlInGaP LED layers. The LED layers are then grown over the thin InGaP, InGaAs, or AlInGaP layer.

Abstract: A gallium nitride crystal with a polyhedron shape having exposed {10-10} m-planes and an exposed (000-1) N-polar c-plane, wherein a surface area of the exposed (000-1) N-polar c-plane is more than 10 mm2 and a total surface area of the exposed {10-10} m-planes is larger than half of the surface area of (000-1) N-polar c-plane. The GaN bulk crystals were grown by an ammonothermal method with a higher temperature and temperature difference than is used conventionally, and using an autoclave having a high-pressure vessel with an upper region and a lower region. The temperature of the lower region of the high-pressure vessel is at or above 550° C., the temperature of the upper region of the high-pressure vessel is set at or above 500° C., and the temperature difference between the lower and upper regions is maintained at or above 30° C. GaN seed crystals having a longest dimension along the c-axis and exposed large area m-planes are used.

Abstract: Affords methods of surface treating a substrate and of manufacturing Group III-V compound semiconductors, in which a substrate made of a Group III-V semiconductor compound is rendered stoichiometric, and microscopic roughness on the surface following epitaxial growth is reduced. The methods include preparing a substrate made of a Group III-V semiconductor compound (S10), and cleaning the substrate with a cleaning solution whose pH has been adjusted to an acidity of 2 to 6.3 inclusive, and to which an oxidizing agent has been added (S20).

Abstract: An MMIC 100 is a semiconductor device which includes an FET formed on a GaAs substrate 10 and an MIM capacitor having a dielectric layer 20b arranged between a lower electrode 18b and an upper electrode 22b. A method for manufacturing the MMIC 100 is provided, in which a source electrode 16a and a drain electrode 16b of the FET are formed and then a gate electrode 18a of the FET and a lower electrode 18b of the MIM capacitor are formed simultaneously by the lift-off method.

Abstract: A method of making a nitride semiconductor substrate having the steps of providing a free-standing substrate that is of a nitride semiconductor and has one of a penetrating pit and a penetrating crack that penetrate from a top surface to a back surface of the free-standing substrate, attaching a metal to the penetrating pit or the penetrating crack, the metal being adapted to be nitrided, and nitriding the metal to form a nitride that seals the penetrating pit or the penetrating crack. A nitride semiconductor substrate has a free-standing substrate that is formed of a nitride semiconductor and has one of a penetrating pit and a penetrating crack that penetrate from a top surface to a back surface of the free-standing substrate, and a metal nitride that seals the penetrating pit or the penetrating crack. The metal nitride is formed of GaN, InN and AlN.