Manufacture Or Treatment Of Devices Consisting Of Plurality Of Solid-state Components Or Integrated Circuits Formed In, Or On, Common Substrate (epo) Patents (Class 257/E21.598)

  • Patent number: 8963307
    Abstract: Various embodiments related to a compact device package are disclosed herein. In some arrangements, a flexible substrate can be coupled to a carrier having walls angled relative to one another. The substrate can be shaped to include two bends. First and second integrated device dies can be mounted on opposite sides of the substrate between the two bends in various arrangements.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: February 24, 2015
    Assignee: Analog Devices, Inc.
    Inventor: David Bolognia
  • Patent number: 8835223
    Abstract: An assembly and method of making same are provided. The assembly can be formed by juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element. An opening can be formed extending through the conductive pad of the second semiconductor element and exposing a surface of the first conductive element. The opening may alternatively be formed extending through the first conductive element. A second electrically conductive element can be formed extending at least within the opening and electrically contacting the conductive pad and the first conductive element. A third semiconductor element can be positioned in a similar manner with respect to the second semiconductor element.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: September 16, 2014
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Piyush Savalia
  • Patent number: 8829653
    Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Yuan Su, Chung-Yi Lin
  • Patent number: 8802464
    Abstract: A method for fabricating a process substrate includes: providing a first substrate; providing a substrate and an auxiliary substrate; contacting the substrate and the auxiliary substrate with each other in a vacuum state, thereby forming micro spaces of a vacuum state between the substrate and the auxiliary substrate; and increasing a pressure at the outside of the contacted substrate and auxiliary substrate to attach the substrate and the auxiliary substrate to each other by a pressure difference between the micro spaces and the outside of the contacted substrate and auxiliary substrate.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: August 12, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Jae-Won Lee, Ki-Yong Kim, Jae Young Oh, Yong-Su An, Sung-Ki Kim, Gi-Sang Hong, Jin-Bok Lee, Sang-Hyuk Won, Dong-Kyu Lee
  • Patent number: 8778741
    Abstract: Disclosed herein is a device package that comprises a device having a top substrate that is disposed on a supporting surface of a package substrate. A package frame contacts the top surface of the top substrate and top surface of the package substrate, and hermetically seals the device between the top surfaces of the top substrate and package substrate. The device can be a semiconductor device, a microstructure such as a microelectromechanical device, or other devices.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: July 15, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Duboc, Terry Tarn
  • Patent number: 8753952
    Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: June 17, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Scott Robert Summerfelt, John A. Rodriguez, Huang-Chun Wen, Steven Craig Bartling
  • Patent number: 8736015
    Abstract: An embodiment is an integrated circuit (IC) structure. The structure comprises a deep n well in a substrate, a first pickup device in the deep n well, a first signal device in the deep n well, a dissipation device in the substrate, a second signal device in the substrate, a first electrical path between the first pickup device and the dissipation device, and a second electrical path between the first signal device and the second signal device. The dissipation device is outside of the deep n well, and the second signal device is outside of the deep n well. A highest point of the first electrical path is lower than a highest point of the second electrical path.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Jen Tsai, Chih-Fu Chang, Chih-Kang Chuang, Yee-Ren Wuang, David Yen, Yuan-Jen Liao, Shih-Che Fang, Hung-Che Hsueh, Chih Mou Huang
  • Patent number: 8722477
    Abstract: A cascoded junction field transistor (JFET) device comprises a first stage high voltage JFET cascoded to a second stage low voltage JFET wherein one of the first and second stages JFET is connected to a drain electrode of another JFET stage.
    Type: Grant
    Filed: January 14, 2012
    Date of Patent: May 13, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Hideaki Tsuchiko
  • Patent number: 8715802
    Abstract: The invention provides a transferring apparatus for a flexible electronic device and method for fabricating a flexible electronic device. The transferring apparatus for the flexible electronic device includes a carrier substrate. A release layer is disposed on the carrier substrate. An adhesion layer is disposed on a portion of the carrier substrate, surrounding the release layer and adjacent to a sidewall of the release layer. A flexible electronic device is disposed on the release layer and the adhesion layer, wherein the flexible electronic device includes a flexible substrate.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: May 6, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Pao-Ming Tsai, Liang-You Jiang, Yu-Yang Chang, Hung-Yuan Li
  • Patent number: 8685793
    Abstract: An assembly and method of making same are provided. The assembly can be formed by juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element. An opening can be formed extending through the conductive pad of the second semiconductor element and exposing a surface of the first conductive element. The opening may alternatively be formed extending through the first conductive element. A second electrically conductive element can be formed extending at least within the opening and electrically contacting the conductive pad and the first conductive element. A third semiconductor element can be positioned in a similar manner with respect to the second semiconductor element.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: April 1, 2014
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Piyush Savalia
  • Patent number: 8664042
    Abstract: A method to construct configurable systems, the method including: providing a first configurable system including a first die and a second die, where the connections between the first die and the second die include through-silicon-via (“TSV”), where the first die is diced from a first wafer using first dice lines; providing a second configurable system including a third die and a fourth die, where the connections between the third die and the fourth die include through-silicon-via (“TSV”), where the third die is diced from a third wafer using third dice lines; and processing the first wafer and the third wafer utilizing at least 20 masks that are the same; where the first dice lines are substantially different than the third dice lines, and where the second die includes a configurable I/O to connect the first configurable system to external devices.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: March 4, 2014
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong
  • Publication number: 20130328068
    Abstract: Radiation-transducer devices, e.g., lighting-emitting devices, including radiation transducers, e.g., light-emitting diodes, and associated devices, systems, and methods are disclosed herein. A radiation-transducer device configured in accordance with a particular embodiment includes a base structure including a first lead, a cap structure including a second lead, and a plurality of radiation transducers irregularly distributed between the base structure and the cap structure. The radiation transducers are non-uniformly oriented relative to the first and second leads and the device is configured to intermittently power the radiation transducers using an alternating current. A method for manufacturing radiation-transducer devices in accordance with a particular embodiment includes distributing a plurality of radiation transducers onto a base structure or a cap structure without individually handling the radiation transducers.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 12, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Martin F. Schubert
  • Patent number: 8592876
    Abstract: A micro-electro-mechanical system (MEMS), methods of forming the MEMS and design structures are provided. The method comprises forming a coplanar waveguide (CPW) comprising a signal electrode and a pair of electrodes on a substrate. The method comprises forming a first sacrificial material over the CPW, and a wiring layer over the first sacrificial material and above the CPW. The method comprises forming a second sacrificial material layer over the wiring layer, and forming insulator material about the first sacrificial material and the second sacrificial material. The method comprises forming at least one vent hole in the insulator material to expose portions of the second sacrificial material, and removing the first and second sacrificial material through the vent hole to form a cavity structure about the wiring layer and which exposes the signal line and pair of electrodes below the wiring layer. The vent hole is sealed with sealing material.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Hanyi Ding, Qizhi Liu, Anthony K. Stamper
  • Patent number: 8563376
    Abstract: A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a bulk CMOS device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the bulk CMOS device on the same SOI substrate.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Leland Chang, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8557676
    Abstract: A first substrate of single-crystal silicon within which is formed an embrittled layer and over a surface of which is formed a first insulating film is provided; a second insulating film is formed over a surface of a second substrate; at least one surface of either the first insulating film or the second insulating film is exposed to a plasma atmosphere or an ion atmosphere, and that surface of the first insulating film or the second insulating film is activated; the first substrate and the second substrate are bonded together with the first insulating film and the second insulating film interposed therebetween; a single-crystal silicon film is separated from the first substrate at an interface of the embrittled layer of the first substrate, and a thin film single-crystal silicon film is formed over the second substrate with the first insulating film and the second insulating film interposed therebetween.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: October 15, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideto Ohnuma
  • Patent number: 8466012
    Abstract: Hybrid bulk finFET and SOI finFET devices and methods for fabrication thereof are provided. In one aspect, a method for fabricating a CMOS circuit having SOI finFET and bulk finFET devices includes the following steps. A wafer is provided having an active layer separated from a substrate by a BOX. Portions of the active layer and BOX are removed in a second region of the wafer so as to expose the substrate. An epitaxial material is grown in the second region of the wafer templated from the substrate. Fins are etched in the active layer and in the epitaxial material using fin lithography hardmasks. Gate stacks are formed covering portions of the fins which serve as channel regions of the SOI finFET/bulk finFET devices. An epitaxial material is grown on exposed portions of the fins which serves as source and drain regions of the SOI finFET/bulk finFET devices.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: June 18, 2013
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Leland Chang, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8426231
    Abstract: An object of an embodiment of the disclosed invention is to provide a semiconductor device including a photoelectric conversion element with excellent characteristics. An object of an embodiment of the disclosed invention is to provide a semiconductor device including a photoelectric conversion device with excellent characteristic through a simple process. A semiconductor device is provided, which includes a light-transmitting substrate; an insulating layer over the light-transmitting substrate; and a photoelectric conversion element over the insulating layer.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: April 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Noriko Harima, Noriko Matsumoto, Akihisa Shimomura, Kosei Noda, Kazuko Yamawaki, Yoshiyuki Kurokawa, Takayuki Ikeda, Takashi Hamada
  • Publication number: 20130075868
    Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming a generally planar weakened zone within the first donor structure defined by implanted ions therein. At least one of a concentration of the implanted ions and an elemental composition of the implanted ions may be formed to vary laterally across the generally planar weakened zone. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.
    Type: Application
    Filed: September 27, 2011
    Publication date: March 28, 2013
    Applicant: SOITEC
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 8395191
    Abstract: A semiconductor device including a first single crystal layer with first transistors and a first alignment mark; at least one metal layer overlying the first single crystal layer, wherein the at least one metal layer includes copper or aluminum; and a second layer including activated dopant regions, the second layer overlying the at least one metal layer, wherein the second layer includes second transistors, wherein the second transistors are processed aligned to the first alignment mark with less than 100 nm alignment error, and the second transistors include mono-crystal, horizontally-oriented transistors.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: March 12, 2013
    Assignee: MonolithIC 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong, Deepak C. Sekar, Zeev Wurman
  • Publication number: 20130058147
    Abstract: The present invention discloses a three-dimensional writable printed memory (3D-wP). It comprises at least a printed memory array and a writable memory array. The printed memory array stores contents data, which are recorded with a printing means; the writable memory array stores custom data, which are recorded with a writing means. The writing means is preferably direct-write lithography. To maintain manufacturing throughput, the total amount of custom data should be less than 1% of the total amount of content data.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 7, 2013
    Applicant: CHENGDU HAICUN IP TECHNOLOGY LLC
    Inventor: Guobiao ZHANG
  • Publication number: 20130049218
    Abstract: A method for forming signal conduits before encapsulation for incorporation as through vias in a semiconductor device package is provided. One or more signal conduits are formed through photolithography and metal deposition on a metal film or substrate. After removing photoresistive material, the semiconductor device package is built by encapsulating the signal conduits along with any semiconductor die and other parts of the package. The ends of the signal conduits are exposed and the signal conduits can then be used as through vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package, and electrical contacts of the semiconductor die. Using this method, signal conduits can be provided in a variety of geometric placings in the semiconductor device package. A semiconductor device package including the signal conduits made from the above method is also provided.
    Type: Application
    Filed: August 31, 2011
    Publication date: February 28, 2013
    Inventors: Zhiwei Gong, Navjot Chhabra, Glenn G. Daves, Scott M. Hayes
  • Publication number: 20130050055
    Abstract: A phased array antenna includes a semiconductor wafer, with radio frequency (RF) circuitry fabricated on top side of the semiconductor wafer. There is an array of antenna elements above the top side of the semiconductor wafer, and a coaxial coupling arrangement coupling the RF circuitry and the array of antenna elements. The coaxial coupling arrangement may include a plurality of coaxial connections, each having an outer conductor, an inner conductor, and a dielectric material therebetween. The dielectric material may be air.
    Type: Application
    Filed: August 30, 2011
    Publication date: February 28, 2013
    Applicant: Harris Corporation
    Inventors: Louis R. Paradiso, Sean Ortiz, Donald Franklin Hege, James J. Rawnick, Lora A. Theiss, Jerry B. Schappacher
  • Patent number: 8378349
    Abstract: An organic light emitting display apparatus and a method of manufacturing the same. The display apparatus includes first, second, and third sub-pixels formed on a substrate. The first sub-pixel includes a first pixel electrode, a first transmissive conductive layer formed on the first pixel electrode, a second transmissive conductive layer formed on the first transmissive conductive layer, a first organic light emitting layer formed on the second transmissive conductive layer, and a counter electrode formed on the first organic light emitting layer. The second sub-pixel includes a second pixel electrode, the first transmissive conductive layer formed on the second pixel electrode, a first protector covering an edge of the first transmissive conductive layer, a second organic light emitting layer electrically connected to the first transmissive conductive layer, and the counter electrode formed on the second organic light emitting layer.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: February 19, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Moo-Soon Ko, Jae-Ho Yoo, Gyoo-Chul Jo
  • Publication number: 20130038881
    Abstract: Optical apparatus includes a beam source, which is configured to generate an optical beam having a pattern imposed thereon. A projection lens is configured to receive and project the optical beam so as to cast the pattern onto a first area in space having a first angular extent. A field multiplier is interposed between the projection lens and the first area and is configured to expand the projected optical beam so as to cast the pattern onto a second area in space having a second angular extent that is at least 50% greater than the first angular extent.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 14, 2013
    Applicant: PRIMESENSE LTD.
    Inventors: Benny Pesach, Zafrir Mor, Shimon Yalov, Alexander Shpunt
  • Patent number: 8367468
    Abstract: An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: February 5, 2013
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Yasuhiro Yamaji, Tokihiko Yokoshima, Masahiro Aoyagi, Hiroshi Nakagawa, Katsuya Kikuchi
  • Patent number: 8354290
    Abstract: An efficient deposition process is provided for fabricating reliable RF MEMS capacitive switches with multilayer ultrananocrystalline (UNCD) films for more rapid recovery, charging and discharging that is effective for more than a billion cycles of operation. Significantly, the deposition process is compatible for integration with CMOS electronics and thereby can provide monolithically integrated RF MEMS capacitive switches for use with CMOS electronic devices, such as for insertion into phase array antennas for radars and other RF communication systems.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: January 15, 2013
    Assignee: UChicago Argonne, LLC
    Inventors: Anirudha V. Sumant, Orlando H. Auciello, Derrick C. Mancini
  • Publication number: 20120319250
    Abstract: In one embodiment, a semiconductor is provided comprising a substrate and a plurality of wiring layers and dielectric layers formed on the substrate, the wiring layers implementing a circuit. The dielectric layers separate adjacent ones of the plurality of wiring layers. A first passivation layer is formed on the plurality of wiring layers. A first contact pad is formed in the layer and connected to the contact pad. A through silicon via (TSV) is formed through the substrate, the plurality of wiring and dielectric layers, and the passivation layer. The TSV is electrically connected to the wire formed on the passivation layer. The TSV is electrically isolated from the wiring layers except for the connection provided by the metal wire formed on the passivation layer.
    Type: Application
    Filed: June 14, 2011
    Publication date: December 20, 2012
    Inventors: Florian Schmitt, Michael Ziesmann
  • Patent number: 8324739
    Abstract: A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: December 4, 2012
    Assignee: Infineon Technologies AG
    Inventor: Ralf Otremba
  • Publication number: 20120299126
    Abstract: Disclosed is an integrated circuit (IC) comprising a substrate (10) carrying a plurality of circuit elements; a metallization stack (12, 14, 16) interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising at least one sensor electrode portion (20) and a bond pad portion (22), at least the at least one sensor electrode portion of said patterned upper metallization layer being covered by a moisture barrier film (23); a passivation stack (24, 26, 28) covering the metallization stack, said passivation stack comprising a first trench (32) exposing the at least one sensor electrode portion and a second trench (34) exposing the bond pad portion; said first trench being filled with a sensor active material (36). A method of manufacturing such an IC is also disclosed.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 29, 2012
    Applicant: NXP B.V.
    Inventors: Roel Daamen, Casper Juffermans, Josephus Franciscus Antonius Maria Guelen, Robertus Antonius Maria Wolters
  • Publication number: 20120302040
    Abstract: Methods of fabrication of three-dimensional integrated devices and three-dimensional integrated devices fabricated therefrom are described. A device side of a donor wafer is coated with a polymer film and exposure of a substrate side to an oxidizing plasma creates a continuous SiO2 film. Portions of the substrate side are selectively coated with a polymer film and etching of uncoated areas removes at least a substantial portion of the crystalline substrate. A plasma etch tool etches a crystalline substrate to within a pre-determined thickness. The silicon portions of the substrate side are etched by exposure to TMAH. After etching, the donor semiconductor wafer is supported by portions of the substrate that were not etched. The supporting structure allows flexing of the donor semiconductor wafer within the etched areas to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.
    Type: Application
    Filed: August 9, 2012
    Publication date: November 29, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas C. LA TULIPE, JR., Sampath PURUSHOTHAMAN, James VICHICONTI
  • Patent number: 8309465
    Abstract: A system produces devices that include a semiconductor part and a non-semiconductor part. A front end is configured to receive a semiconductor part and to process the semiconductor part. A back end is configured to receive the processed semiconductor part and to assemble the processed semiconductor part and a non-semiconductor part into a device. A transfer device is configured to automatically handle the semiconductor part in the front end and to automatically transfer the processed semiconductor part to the back end.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: November 13, 2012
    Assignee: Infineon Technologies AG
    Inventors: Oskar Neuhoff, Tobias Gamon, Norbert Martin Haueis, Dirk Pikorz, Michael Wolfgang Larisch, Franz Reithner
  • Patent number: 8310036
    Abstract: A microelectronic unit is provided in which front and rear surfaces of a semiconductor element may define a thin region which has a first thickness and a thicker region having a thickness at least about twice the first thickness. A semiconductor device may be present at the front surface, with a plurality of first conductive contacts at the front surface connected to the device. A plurality of conductive vias may extend from the rear surface through the thin region of the semiconductor element to the first conductive contacts. A plurality of second conductive contacts can be exposed at an exterior of the semiconductor element. A plurality of conductive traces may connect the second conductive contacts to the conductive vias.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: November 13, 2012
    Assignee: DigitalOptics Corporation Europe Limited
    Inventors: Belgacem Haba, Kenneth Allen Honer, David B. Tuckerman, Vage Oganesian
  • Patent number: 8283192
    Abstract: Provided is a method of forming a pattern including the steps of forming a first pattern including a depressed or protruding alignment mark on a substrate; forming a flattening layer on the first pattern; removing a part of the flatting layer above the alignment mark; forming a processed layer on the flattening layer to cover the alignment mark; performing alignment by optically detecting a position of the alignment mark from above the processed layer, using light; and forming a second pattern by patterning the processed layer on the basis of the alignment.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: October 9, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kyouhei Watanabe
  • Publication number: 20120235254
    Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.
    Type: Application
    Filed: May 31, 2012
    Publication date: September 20, 2012
    Applicants: STMICROELECTRONICS ASIA PACIFIC PTE, LTD., STMICROELECTRONICS, INC.
    Inventors: Venkatesh Mohanakrishnaswamy, Olivier Le Neel, Loi N. Nguyen
  • Publication number: 20120208319
    Abstract: A method of manufacturing a semiconductor package includes embedding a semiconductor chip in an encapsulant. First contact pads are formed on a first main face of the semiconductor package and second contact pads are formed on a second main face of the semiconductor package opposite the first main face. A diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d?(8/25)x+142 ?m, where x is a pitch of the second contact pads in micrometers.
    Type: Application
    Filed: April 23, 2012
    Publication date: August 16, 2012
    Applicant: Infineon Technologies AG
    Inventors: Thorsten Meyer, Rainer Leuschner, Gerald Ofner, Reinhard Hess, Recai Sezi
  • Patent number: 8241978
    Abstract: A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: August 14, 2012
    Assignee: Anpec Electronics Corporation
    Inventors: Wei-Chieh Lin, Li-Cheng Lin, Hsin-Yu Hsu, Ho-Tai Chen, Jen-Hao Yeh, Guo-Liang Yang, Chia-Hui Chen, Shih-Chieh Hung
  • Publication number: 20120193684
    Abstract: An efficient deposition process is provided for fabricating reliable RF MEMS capacitive switches with multilayer ultrananocrystalline (UNCD) films for more rapid recovery, charging and discharging that is effective for more than a billion cycles of operation. Significantly, the deposition process is compatible for integration with CMOS electronics and thereby can provide monolithically integrated RF MEMS capacitive switches for use with CMOS electronic devices, such as for insertion into phase array antennas for radars and other RF communication systems.
    Type: Application
    Filed: April 5, 2011
    Publication date: August 2, 2012
    Applicant: UChicago Argonne, LLC
    Inventors: Anirudha V. Sumant, Orlando H. Auciello, Derrick C. Mancini
  • Patent number: 8216933
    Abstract: A method of depositing a bilayer of tungsten over tungsten nitride by a plasma sputtering process in which krypton is used as the sputter working gas during the tungsten deposition. Argon may be used as the sputtering working gas during the reactive sputtering deposition of tungsten nitride. The beneficial effect of reduction of tungsten resistivity is increased when the thickness of the tungsten layer is less than 50 nm and further increased when less than 35 nm. The method may be used in forming a gate stack including a polysilicon layer over a gate oxide layer over a silicon gate region of a MOS transistor in which the tungsten nitride acts as a barrier. A plasma sputter chamber in which the invention may be practiced includes gas sources of krypton, argon, and nitrogen.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: July 10, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Wei D. Wang, Srinivas Gandikota, Kishore Lavu
  • Publication number: 20120146202
    Abstract: A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls.
    Type: Application
    Filed: December 14, 2010
    Publication date: June 14, 2012
    Inventors: Yan Xun Xue, Yueh-Se Ho, Hamza Yilmaz, Anup Bhalla, Jun Lu, Kal Liu
  • Publication number: 20120142149
    Abstract: A cascoded junction field transistor (JFET) device comprises a first stage high voltage JFET cascoded to a second stage low voltage JFET wherein one of the first and second stages JFET is connected to a drain electrode of another JFET stage.
    Type: Application
    Filed: January 14, 2012
    Publication date: June 7, 2012
    Inventor: Hideaki Tsuchiko
  • Patent number: 8193044
    Abstract: A method of manufacturing an integrated circuit (IC), comprising: defining a plurality of continuous active areas; forming conducting lines extending over the active areas; and using the conducting lines as a mask, introducing dopant into the active areas. Connections are provided between doped regions and conducting lines to form first and second circuit portions, at least one active area being continuous between those portions. In that active area, connections are provided between doped regions and conducting lines to form a pair of diode-connected transistors in reverse bias to one another between the first and second circuit portions, connected so as to leave a shared, unconnected doped region between the pair. The present invention also relates to a corresponding IC.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: June 5, 2012
    Assignee: Icera Inc.
    Inventor: Trevor Monk Kenneth
  • Patent number: 8153499
    Abstract: A method of manufacturing a semiconductor wafer, the method including: providing a base wafer including a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of the metal layers, wherein the monocrystalline layer includes second alignment marks; and performing a lithography using at least one of the first alignment marks and at least one of the second alignment marks.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: April 10, 2012
    Assignee: MonolithIC 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong
  • Publication number: 20120074502
    Abstract: Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts.
    Type: Application
    Filed: September 28, 2010
    Publication date: March 29, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin, Robert R. Robison
  • Patent number: 8138016
    Abstract: Methods for integrating quartz-based resonators with electronics on a large area wafer through direct pick-and-place and flip-chip bonding or wafer-to-wafer bonding using handle wafers are described. The resulting combination of quartz-based resonators and large area electronics wafer solves the problem of the quartz-electronics substrate diameter mismatch and enables the integration of arrays of quartz devices of different frequencies with the same electronics.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: March 20, 2012
    Assignee: HRL Laboratories, LLC
    Inventors: David T. Chang, Randall L. Kubena
  • Publication number: 20120061648
    Abstract: Disclosed is a method to construct a device that includes a plurality of nanowires (NWs) each having a core and at least one shell. The method includes providing a plurality of radially encoded NWs where each shell contains one of a plurality of different shell materials; and differentiating individual ones of the NWs from one another by selectively removing or not removing shell material within areas to be electrically coupled to individual ones of a plurality of mesowires (MWs). Also disclosed is a nanowire array that contains radially encoded NWs, and a computer program product useful in forming a nanowire array.
    Type: Application
    Filed: November 21, 2011
    Publication date: March 15, 2012
    Inventors: Andre DEHON, Charles M. Lieber, John E. Savage, Eric Rachlin
  • Patent number: 8129255
    Abstract: The invention relates to a process for and an arrangement of the connection of processed semiconductor wafers (1, 2) wherein, in addition to the firm connection, there is an electric connection (5) between the semiconductor wafers and/or the electronic structures (3) supporting them. For this purpose, low-melting structured intermediate glass layers (6; 6a) are used as insulating layers and as an electric connection in the form of electrically conductive solder (5) on a glass basis in order to achieve a firm connection.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: March 6, 2012
    Assignee: X-Fab Semiconductors Foundries AG
    Inventor: Roy Knechtel
  • Patent number: 8129810
    Abstract: A vertically-integrated image sensor is proposed with the performance characteristics of single crystal silicon but with the area coverage and cost of arrays fabricated on glass. The image sensor can include a backplane array having readout elements implemented in silicon-on-glass, a frontplane array of photosensitive elements vertically integrated above the backplane, and an interconnect layer disposed between the backplane array and the image sensing array. Since large area silicon-on-glass backplanes are formed by tiling thin single-crystal silicon layers cleaved from a thick silicon wafer side-by-side on large area glass gaps between the tiled silicon backplane would normally result in gaps in the image captured by the array. Therefore, embodiments further propose that the pixel pitch in both horizontal and vertical directions of the frontplane be larger than the pixel pitch of the backplane, with the pixel pitch difference being sufficient that the frontplane bridges the gap between backplane tiles.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: March 6, 2012
    Assignee: Carestream Health, Inc.
    Inventor: Timothy J. Tredwell
  • Publication number: 20120038431
    Abstract: The invention relates to a microelectromechanical resonators and a method of manufacturing thereof. The resonator comprises at least two resonator elements made from semiconductor material, the resonator elements being arranged laterally with respect to each other as an array, at least one transducer element coupled to said resonator elements and capable of exciting a resonance mode to the resonator elements. According to the invention, said at least one transducer element is a piezoelectric transducer element arranged laterally with respect to the at least two resonator elements between the at least two resonator elements and adapted to excite to the resonator elements as said resonance mode a resonance mode whose resonance frequency is dependent essentially only on the c44 elastic parameter of the elastic modulus of the material of the resonator elements. By means of the invention, electrostatic actuation and problems associated therewith can be avoided and accurate resonators can be manufactured.
    Type: Application
    Filed: August 12, 2011
    Publication date: February 16, 2012
    Applicant: TEKNOLOGIAN TUTKIMUSKESKUS VTT
    Inventors: Antti JAAKKOLA, Tuomas PENSALA, Jyrki KIIHAMÄKI
  • Publication number: 20120012982
    Abstract: Capacitors and methods of forming semiconductor device capacitors are disclosed. Trenches are formed to define a capacitor bottom plate in a doped upper region of a semiconductor substrate, a dielectric layer is formed conformally over the substrate within the trenches, and a polysilicon layer is formed over the dielectric layer to define a capacitor top plate. A guard ring region of opposite conductivity and peripheral recessed areas may be added to avoid electric field crowding. A central substrate of lower doping concentration may be provided to provide a resistor in series below the capacitor bottom plate. A series resistor may also be provided in a resistivity region of the polysilicon layer laterally extending from the trenched area region. Contact for the capacitor bottom plate may be made through a contact layer formed on a bottom of the substrate.
    Type: Application
    Filed: July 18, 2011
    Publication date: January 19, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jacek Korec, Shuming Xu, Jun Wang, Boyi Yang
  • Publication number: 20110309466
    Abstract: The semiconductor device includes a first-conductivity-type region (an N-type well region, for example) and a first second-conductivity-type region (a P-type semiconductor substrate, for example) positioned to cover a lower surface of the first-conductivity-type region, a second second-conductivity-type region (a P-type well region, for example) that is positioned to surround the side faces of the first-conductivity-type region and is in contact with the first second-conductivity-type region, a guard ring that is electrically connected to the second second-conductivity-type region and is also electrically connected to a fixed potential terminal, an insulating film positioned to cover an upper surface of the first-conductivity-type region, and an analog element (a resistor element, for example) placed on the insulating film.
    Type: Application
    Filed: June 21, 2011
    Publication date: December 22, 2011
    Inventor: Hiroaki NANBA