Abstract: A composite wafer includes a first substrate having a first vertical thickness and a top surface, the top surface being prepared in a state for subsequent semiconductor material epitaxial deposition. A carrier substrate is disposed beneath the first substrate. The carrier substrate has a second vertical thickness greater than the first vertical thickness. An interlayer bonds the first substrate to the carrier substrate.

Abstract: The present invention is a method for producing a group III nitride semiconductor layer in which a single crystal group III nitride semiconductor layer (103) is formed on a substrate (101), the method including: a substrate processing step of forming, on the (0001) C-plane of the substrate (101), a plurality of convex parts (12) of surfaces (12c) not parallel to the C-plane, to thereby form, on the substrate, an upper surface (10) that is composed of the convex parts (12) and a flat surface (11) of the C-plane; and an epitaxial step of epitaxially growing the group III nitride semiconductor layer (103) on the upper surface (10), to thereby embed the convex parts (12) in the group III nitride semiconductor layer (103).

Abstract: A composite wafer includes a first substrate having a first vertical thickness and a top surface, the top surface being prepared in a state for subsequent semiconductor material epitaxial deposition. A carrier substrate is disposed beneath the first substrate. The carrier substrate has a second vertical thickness greater than the first vertical thickness. An interlayer bonds the first substrate to the carrier substrate.

Abstract: A method for manufacturing a semiconductor element of the present invention, has: a laser irradiation step of focusing a pulsed laser beam inside of a substrate constituting a wafer, thereby forming a plurality of isolated processed portions along an intended dividing line inside of the substrate, and creating a fissure that runs from the processed portions at least to the surface of the substrate and links adjacent processed portions; and a wafer division step of dividing the wafer along the intended dividing line.

Abstract: An epitaxial substrate having preferable two dimensional electron gas characteristic and contact characteristic is provided in the present invention. A channel layer is formed on a base substrate with GaN. A spacer layer is formed on the channel layer with AlN. A barrier layer is formed on the spacer layer with group III nitride having a composition of InXAlyGazN (wherein x+y+z=1) and at least including In, Al, and Ga such that the composition of the barrier layer is within the range surrounded with four lines defined in accordance with the composition on a ternary phase diagram with InN, AlN, and GaN as vertexes.

Abstract: A method of forming a vertical structure light emitting diode with a heat exhaustion structure, comprising the steps of: providing a sapphire substrate; producing a number of recesses on the sapphire substrate, each of which has a depth of p; forming a buffer layer having a number of protrusions, each of which has a height of q smaller than p so that when the protrusions of the buffer layer are accommodated within the recesses of the sapphire substrate, a number of gaps are formed therebetween for heat exhaustion; growing a number of luminescent layers on the buffer layer, having a medium layer formed between the luminescent layers and the buffer layer; etching through the luminescent layers and the buffer layer to form a duct for heat exhaustion; removing the sapphire substrate by excimer laser lift-off (LLO); roughening the medium layer; and depositing electrodes on the roughened medium layer.

Abstract: Non-polar or semi-polar (Al, Ga, In)N substrates are fabricated by re-growth of (Al, Ga, In)N crystal on (Al, Ga, In)N seed crystals, wherein the size of the seed crystal expands or is increased in the lateral and vertical directions, resulting in larger sizes of non-polar and semi-polar substrates useful for optoelectronic and microelectronic devices. One or more non-polar or semi-polar substrates may be sliced from the re-grown crystal. The lateral growth rate may be greater than the vertical growth rate. The seed crystal may be a non-polar seed crystal. The seed crystal may have crystalline edges of equivalent crystallographic orientation.

Abstract: Methods of fabricating low temperature semiconductor thin film switching devices are described.

Abstract: In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.

Abstract: The present invention provides an SOS wafer comprising a non-transparent polysilicon layer provided on a back surface of a sapphire substrate, a silicon nitride layer which protects the polysilicon layer, and a stress relaxing film which cancels stress produced in the silicon nitride layer, wherein the silicon nitride layer and the stress relaxing film are provided on the back surface side.