Substrate Is Nonsemiconductor Body, E.g., Insulating Body (epo) Patents (Class 257/E21.7)
  • Patent number: 10141361
    Abstract: A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: November 27, 2018
    Assignee: Sony Corporation
    Inventors: Taku Umebayashi, Hiroshi Takahashi, Reijiroh Shohji
  • Patent number: 8927349
    Abstract: A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: January 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8895413
    Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: November 25, 2014
    Assignee: Luxtera, Inc.
    Inventors: Thierry Pinguet, Steffen Gloeckner, Peter De Dobbelaere, Sherif Abdalla, Daniel Kucharski, Gianlorenzo Masini, Kosei Yokoyama, John Guckenberger, Attila Mekis
  • Patent number: 8877570
    Abstract: An array substrate having a wiring of a pad region formed without an insulating film or without an insulating film and an organic film to reduce abnormal operations due to an increase in resistance caused by a contact margin at a high temperature, and a method for manufacturing the same are provided. The array substrate includes: an insulating substrate including a pad region and a thin film transistor (TFT) formation region; a first electrode layer formed in the pad region of the substrate; and a second electrode formed on the first electrode layer in an overlapping manner.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: November 4, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: JongWoo Kim, ChangHo Oh, WonHyung Yoo, SangYoon Paik, JunKi Kang, JongHoon Kim
  • Patent number: 8859348
    Abstract: A method for fabricating field effect transistors patterns a strained silicon layer formed on a dielectric layer of a substrate into at least one NFET region including at least a first portion of the strained silicon layer. The strained silicon layer is further patterned into at least one PFET region including at least a second portion of the strained silicon layer. A masking layer is formed over the first portion of the strained silicon layer. After the masking layer has been formed, the second strained silicon layer is transformed into a relaxed silicon layer. The relaxed silicon layer is transformed into a strained silicon germanium layer.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Kangguo Cheng, Bruce Doris, Ali Khakifirooz, Devendra K. Sadana
  • Patent number: 8790998
    Abstract: Example embodiments relate to a method of forming a core-shell structure. According to a method, a region in which the core-shell structure will be formed is defined on a substrate, and a core and a shell layer may be sequentially stacked in the defined region. A first shell layer may further be formed between the substrate and the core. When the core and the shell layer are sequentially stacked in the core-shell region, the method may further include forming a groove on the substrate, forming the first shell layer covering surfaces of the groove, forming the core in the groove of which surfaces are covered by the first shell layer, and forming a second shell layer covering the core.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-ha Hong, Kyoung-won Park, Jai-kwang Shin, Jong-seob Kim, Hyuk-soon Choi
  • Patent number: 8704380
    Abstract: Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging microfeature devices in accordance with an embodiment of the invention can include releasably attaching a plurality of first known good microelectronic dies to a carrier substrate in a desired arrangement. In several embodiments, for example, the first dies can be releasably attached to an attachment feature on the carrier substrate. The method can also include attaching one or more second known good microelectronic dies to the individual first dies in a stacked configuration to form a plurality of stacked devices. The method further includes at least partially encapsulating the stacked devices and separating the stacked devices from each other.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood
  • Patent number: 8691639
    Abstract: Embodiments of the disclosed technology disclose manufacture methods of a thin film transistor and an array substrate and a mask therefor are provided. The manufacture method of the thin film transistor comprises: patterning a wire layer by using a exposure machine and a mask with a first exposure amount larger than a normal exposure amount during formation of source and drain electrodes; forming a semiconductor layer on the patterned wire layer; patterning the semiconductor layer by using the exposure machine and the mask with a second exposure amount smaller than the first exposure amount. The mask comprises a source region for forming the source electrode, a drain region for forming the drain electrode and a slit provided between the source region and the drain region, and the width of the slit is smaller than the resolution of the exposure machine.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: April 8, 2014
    Assignee: Boe Technology Group Co., Ltd.
    Inventors: Weifeng Zhou, Jianshe Xue
  • Publication number: 20140061794
    Abstract: A finFET with self-aligned punchthrough stopper and methods of manufacture are disclosed. The method includes forming spacers on sidewalls of a gate structure and fin structures of a finFET device. The method further includes forming a punchthrough stopper on exposed sidewalls of the fin structures, below the spacers. The method further includes diffusing dopants from the punchthrough stopper into the fin structures. The method further includes forming source and drain regions adjacent to the gate structure and fin structures.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita
  • Publication number: 20140030876
    Abstract: A method for fabricating an integrated circuit having a FinFET structure includes providing a semiconductor substrate comprising silicon and a high carrier mobility material, forming one or more fin structures on the semiconductor substrate, and subjecting the substrate to a condensation process for the condensation of the high carrier mobility material. The condensation process results in the formation of condensed fin structures formed substantially entirely of the high carrier mobility material and a layer of silicon oxide formed over the condensed fin structures. The method further includes removing the silicon oxide formed over the condensed fin structures so as to expose the condensed fin structures.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen
  • Patent number: 8633065
    Abstract: The present invention relates to a method for manufacturing a mother substrate, the mother substrate comprising: a substrate comprising at least one display region and pre-cutting regions in a periphery of the display region, wherein the display region comprises gate scanning lines and data scanning lines, the pre-cutting regions comprise a gate-line connecting line and a data-line connecting line electrically connected to each other, and the gate-line connecting line is electrically connected to all of the gate scanning lines in the display region, and the data-line connecting line is electrically connected to all of the data scanning lines in the display region substrate.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: January 21, 2014
    Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.
    Inventors: Huafeng Liu, Hongxi Xiao, Shunkang Su, Ping Wu, Hanting Ding
  • Patent number: 8633532
    Abstract: A semiconductor memory device having a floating body capacitor. The semiconductor memory device can perform a memory operation using the floating body capacitor. The semiconductor memory device includes an SOI substrate having a staked structure in which a base substrate having a conducting surface, a buried insulating layer and a device-forming layer are staked, a transistor formed in a portion of the device-forming layer, having a gate, a source region and a drain region, and a capacitor formed by the buried insulating layer, the conducting surface of the base substrate, and accumulated holes generated in the device-forming layer when the transistor is driven.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: January 21, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jong Su Kim
  • Publication number: 20140015564
    Abstract: A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE.
    Type: Application
    Filed: July 16, 2012
    Publication date: January 16, 2014
    Inventors: Ethan Cannon, Salim Rabaa, Josh Mackler
  • Publication number: 20140011328
    Abstract: A method for fabricating field effect transistors patterns a strained silicon layer formed on a dielectric layer of a substrate into at least one NFET region including at least a first portion of the strained silicon layer. The strained silicon layer is further patterned into at least one PFET region including at least a second portion of the strained silicon layer. A masking layer is formed over the first portion of the strained silicon layer. After the masking layer has been formed, the second strained silicon layer is transformed into a relaxed silicon layer. The relaxed silicon layer is transformed into a strained silicon germanium layer.
    Type: Application
    Filed: July 9, 2012
    Publication date: January 9, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. BEDELL, Kangguo CHENG, Bruce DORIS, Ali KHAKIFIROOZ, Devendra K. SADANA
  • Patent number: 8603868
    Abstract: A method includes providing a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate; etching a V-shaped groove through the silicon surface between the first and second adjacent gate structures, where the V-shaped groove extends substantially from an edge of the first gate structure to an opposing edge of the second gate structure; implanting a source/drain region into the V-shaped groove; and siliciding the implanted source/drain region. The etching step is preferably performed by using a HCl-based chemical vapor etch (CVE) that stops on a Si(111) plane of the silicon substrate (e.g., a SOI layer). A structure containing FETs that is fabricated in accordance with the method is also disclosed.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Guillorn, Gen Pei Lauer, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8581332
    Abstract: The invention provides a semiconductor device and its manufacturing method in which a memory transistor and a plurality of thin film transistors that have gate insulating films with different thicknesses are fabricated over a substrate. The invention is characterized by the structural difference between the memory transistor and the plurality of thin film transistors. Specifically, the memory transistor and some of the plurality of thin film transistors are provided to have a bottom gate structure while the other thin film transistors are provided to have a top gate structure, which enables the reduction of characteristic defects of the transistor and simplification of its manufacturing process.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: November 12, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tamae Takano, Tetsuya Kakehata, Shunpei Yamazaki
  • Publication number: 20130285063
    Abstract: The present invention discloses a thin-film transistor (TFT) array substrate and a manufacturing method thereof. Depositing a transparent conductive layer and a first metal layer on a substrate, which is patterned by a multi-tone mask (MTM) to form a gate, a common electrode and a reflecting layer; depositing a gate insulation layer, which is patterned by a first mask to remain the gate insulation layer on the gate; depositing a semiconductor layer, which is patterned by a second mask to remain the semiconductor layer on the gate; and depositing a second metal layer, which is patterned by a third mask to form a source and a drain.
    Type: Application
    Filed: May 9, 2012
    Publication date: October 31, 2013
    Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Hua Huang, Pei Jia
  • Patent number: 8535996
    Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: September 17, 2013
    Assignee: SOITEC
    Inventors: Mohamad Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karin Landry, Carlos Mazure
  • Publication number: 20130175594
    Abstract: An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.
    Type: Application
    Filed: July 18, 2012
    Publication date: July 11, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Bruce B. Doris, Terence B. Hook, Ali Khakifirooz, Pranita Kulkarni, Tenko Yamashita, Chun-Chen Yeh
  • Publication number: 20130168668
    Abstract: A thin film transistor (TFT) array substrate includes a substrate, a gate electrode layer disposed on the substrate, an insulating layer, an oxide semiconductor layer disposed on the insulating layer, a source/drain electrode layer, an organic-acrylic photoresist layer, a passivation layer and an electrically conductive layer. The insulating layer is disposed on the gate electrode layer and the substrate. The source/drain electrode layer is disposed on the insulating layer and the oxide semiconductor layer, and a gap is formed through the source/drain electrode layer for exposing the oxide semiconductor layer therethrough. The organic-acrylic photoresist layer covers the source/drain electrode layer. The passivation layer is disposed on the substrate, the oxide semiconductor layer and the organic-acrylic photoresist layer.
    Type: Application
    Filed: September 14, 2012
    Publication date: July 4, 2013
    Applicant: E INK HOLDINGS INC.
    Inventors: Wei-Chou LAN, Ted-Hong SHINN, Hsing-Yi WU
  • Publication number: 20130154006
    Abstract: FinFETS and methods for making FinFETs with a vertical silicide structure. A method includes providing a substrate with a plurality of fins, forming a gate stack above the substrate wherein the gate stack has at least one sidewall and forming an off-set spacer adjacent the gate stack sidewall. The method also includes growing an epitaxial film which merges the fins to form an epi-merge layer, forming a field oxide layer adjacent to at least a portion of the off-set spacer and removing a portion of the field oxide layer to expose a portion of the epi-merge-layer. The method further includes removing at least part of the exposed portion of the epi-merge-layer to form an epi-merge sidewall and an epi-merge spacer region and forming a silicide within the epi-merge sidewall to form a silicide layer and two silicide sidewalls.
    Type: Application
    Filed: October 11, 2012
    Publication date: June 20, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: International Business Machines Corporation
  • Publication number: 20130157440
    Abstract: A composite wafer includes a first substrate having a first vertical thickness and a top surface, the top surface being prepared in a state for subsequent semiconductor material epitaxial deposition. A carrier substrate is disposed beneath the first substrate. The carrier substrate has a second vertical thickness greater than the first vertical thickness. An interlayer bonds the first substrate to the carrier substrate.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Applicant: Power Integrations, Inc.
    Inventors: Alexei Koudymov, Jamal Ramdani, Kierthi Swaminathan
  • Publication number: 20130153971
    Abstract: A method includes providing a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate; etching a V-shaped groove through the silicon surface between the first and second adjacent gate structures, where the V-shaped groove extends substantially from an edge of the first gate structure to an opposing edge of the second gate structure; implanting a source/drain region into the V-shaped groove; and siliciding the implanted source/drain region. The etching step is preferably performed by using a HCl-based chemical vapor etch (CVE) that stops on a Si(111) plane of the silicon substrate (e.g., a SOI layer). A structure containing FETs that is fabricated in accordance with the method is also disclosed.
    Type: Application
    Filed: December 19, 2011
    Publication date: June 20, 2013
    Applicant: International Business Machines Corporation
    Inventors: Michael A. Guillorn, Gen Pei Lauer, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8465992
    Abstract: A method of manufacturing a flexible display device is provided. The method includes: preparing a first flexible substrate on which a display unit is formed; forming an encapsulation unit including a base substrate, a second flexible substrate formed on the base substrate, and a barrier layer formed on the second flexible substrate; combining the encapsulation unit with the display unit; and separating the base substrate from the second flexible substrate by using a difference between a coefficient of thermal expansion of the base substrate and a coefficient of thermal expansion of the second flexible substrate, by applying a heated solution between the base substrate and the second flexible substrate. The flexible display device is easily manufactured since the base substrate and the second flexible substrate, which have different coefficients of thermal expansion and are coupled to each other, are separable from each other by applying the heated solution.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: June 18, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung-Hun Kim, Hoon-Kee Min, Dong-Un Jin, Sang-Joon Seo, Sung-Guk An, Young-Gu Kim, Hyung-Sik Kim, Young-Ji Kim
  • Patent number: 8455277
    Abstract: A thin film transistor array panel is provided, which includes a plurality of gate lines, a plurality of common electrodes, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer, a plurality of drain electrodes formed on the semiconductor layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn is not produced on the surfaces of the common electrode.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: June 4, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Je-Hun Lee, Sung-Jin Kim, Hee-Joon Kim, Chang-Oh Jeong
  • Patent number: 8431451
    Abstract: A semiconductor substrate is formed into a regular hexagon or a shape similar to the regular hexagon. The semiconductor substrate is bonded to and separated from a large-area substrate. Moreover, layout is designed so that a boundary of bonded semiconductors is located in a region which is removed by etching when patterning is performed by photolithography or the like.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: April 30, 2013
    Assignee: Semicondutor Energy Laboratory Co., Ltd.
    Inventors: Yasunori Yoshida, Akihisa Shimomura, Yurika Sato
  • Patent number: 8420467
    Abstract: A semiconductor device has a semiconductor substrate, a semiconductor fin which is formed on the semiconductor substrate, which has a long side direction and a short side direction, and which has a carbon-containing silicon film including an impurity and a silicon film formed on the carbon-containing silicon film, a gate electrode which is formed to face both side surfaces of the semiconductor fin in the short side direction, source and drain regions which are respectively formed in the semiconductor fin located in the direction of both sides in the long side direction of the semiconductor fin so as to sandwich the gate electrode, and an element isolation insulating film which is formed on the side surface of the semiconductor fin and between the gate electrode and the semiconductor substrate.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: April 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Izumida, Nobutoshi Aoki
  • Patent number: 8409926
    Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: April 2, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng, Xusheng Bao
  • Publication number: 20130071973
    Abstract: A method of fabricating a thin film transistor array substrate is disclosed.
    Type: Application
    Filed: September 19, 2012
    Publication date: March 21, 2013
    Applicant: LG Display Co., Ltd.
    Inventor: LG Display Co., Ltd.
  • Publication number: 20130062696
    Abstract: The present invention provides an SOI semiconductor structure with a hybrid of coplanar germanium (Ge) and III-V, and a method for preparing the same. A heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material coplanar on an insulator includes at least one Ge substrate formed on the insulating layer, and the other substrate is a group III-V semiconductor material formed on the Ge semiconductor.
    Type: Application
    Filed: May 16, 2012
    Publication date: March 14, 2013
    Applicant: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
    Inventors: Zengfeng Di, Jiantao Bian, Miao Zhang, Xi Wang
  • Publication number: 20130056834
    Abstract: A microelectronic device includes a plurality of disconnected similar semiconducting portions, electrically isolated from each other and forming a semiconductor layer, at a spacing by a constant distance and with a shape parallel to the other portions. The microelectronic device also includes two electrodes arranged in contact with the semiconductor layer such that a maximum distance separating the two electrodes is less than the largest dimension of one of the semiconductor portions. The shape and dimensions of the semiconductor portions, the spacing between the semiconductor portions, the shape and dimensions of the electrodes and the layout of the electrodes relative to the semiconductor portions are such that at least one of the semiconductor portions electrically connects the two electrodes to each other. The largest dimensions of the semiconductor portions are perpendicular to the largest dimension of the electrodes, the electrodes being similar.
    Type: Application
    Filed: May 3, 2011
    Publication date: March 7, 2013
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Romain Gwoziecki, Romain Coppard
  • Publication number: 20130049116
    Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, an insulating buried layer, and a semiconductor layer, wherein the insulating buried layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the insulating buried layer; adjacent MOSFETs formed in the SOI wafer, wherein each of the adjacent MOSFETs comprises a back gate formed in the semiconductor substrate and a back gate isolation region formed under the back gate; and a shallow trench isolation, wherein the shallow trench isolation is formed between the adjacent MOSFETs to isolate the adjacent MOSFETs from each other, wherein a PN junction is formed between the back gate and the back gate isolation region of each of the adjacent MOSFETs. According to embodiments of the present disclosure, a PN junction is formed between the back gate isolation regions of the adjacent MOSFETs.
    Type: Application
    Filed: November 18, 2011
    Publication date: February 28, 2013
    Inventors: Huilong Zhu, Qingqing Liang, Zhijiong Luo, Haizhou Yin
  • Patent number: 8377761
    Abstract: A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: February 19, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andreas Gehring, Jan Hoentschel, Andy Wei
  • Publication number: 20130037886
    Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.
    Type: Application
    Filed: August 10, 2011
    Publication date: February 14, 2013
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chih-Chien Liu, Chin-Cheng Chien, Chin-Fu Lin
  • Patent number: 8362522
    Abstract: In a semiconductor film having a heterojunction structure, for example a semiconductor film including a SiGe layer and a Si layer formed on the SiGe layer, impurity concentration is controlled in such a manner that the concentration of impurity in the lower, SiGe layer becomes higher than that in the upper, Si layer by exploiting the fact that there is a difference between the SiGe layer and the Si layer in the diffusion coefficient of the impurity. The impurity contained in the semiconductor film 11 is of the conductivity type opposite to that of the transistor (p-type in the case of an n-type MOS transistor whereas n-type in the case of a p-type MOS transistor). In this way, the mobility in a semiconductor device including a semiconductor film having a heterojunction structure with a compression strain structure is increased, thereby improving the transistor characteristics and reliability of the device.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: January 29, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masashi Shima
  • Publication number: 20130017673
    Abstract: A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming first and second nanowire channels connected at each end to semiconductor pads at first and second wafer regions, respectively, with second nanowire channel sidewalls being misaligned relative to a crystallographic plane of the semiconductor more than first nanowire channel sidewalls and displacing the semiconductor toward an alignment condition between the sidewalls and the crystallographic plane such that thickness differences between the first and second nanowire channels reflect the greater misalignment of the second nanowire channel sidewalls.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 17, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sarunya Bangsaruntip, Guy M. Cohen, Jeffrey W. Sleight
  • Publication number: 20130015526
    Abstract: The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention comprises: a substrate which comprises a base layer, an insulating layer on the base layer, and a semiconductor layer on the insulating layer; and a first transistor and a second transistor formed on the substrate, the first and second transistors being isolated from each other by a trench isolation structure formed in the substrate. Wherein at least a part of the base layer under at least one of the first and second transistors is strained, and the strained part of the base layer is adjacent to the insulating layer. The semiconductor device according to the invention increases the speed of the device and thus improves the performance of the device.
    Type: Application
    Filed: August 9, 2011
    Publication date: January 17, 2013
    Inventors: Qingqing Liang, Huilong Zhu, Huicai Zhong
  • Patent number: 8344454
    Abstract: An object of the invention is to provide a semiconductor device having improved performance, high reliability, and a reduced chip size, in particular, to provide a semiconductor device having an MOSFET over an SOI substrate capable of maintaining its reliability while controlling the potential of a well below a gate electrode and preventing generation of parasitic capacitance. Generation of parasitic capacitance is prevented by controlling the potential of a well below a gate electrode by using a well contact plug passing through a hole portion formed in a gate electrode wiring. Generation of defects in a gate insulating film is prevented by making use of a gettering effect produced by causing an element isolation region to extend along the gate electrode.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: January 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kyoya Nitta, Yutaka Hoshino
  • Publication number: 20120313169
    Abstract: FIN-FET ICs with adjustable FIN-FET channel widths are formed from a semiconductor layer (42). Fins (36) may be etched from the layer (42) and then some (46) locally shortened or the layer (42) may be locally thinned and then fins (46) of different fin heights etched therefrom. Either way provides fins (46) and FIN-FETs (40) with different channel widths W on the same substrate (24). Fin heights (H) are preferably shortened by implanting selected ions (A, B, C, etc.) through a mask (90, 90?, 94, 94?, 97, 97?) to locally enhance the etch rate of the layer (42) or some of the fins (36). The implant(s) (A, B, C, etc.) is desirably annealed and then differentially etched. This thins part(s) (42-i) of the layer (42) from which the fins (46) are then etched or shortens some of the fins (46) already etched from the layer (42). For silicon, germanium is a suitable implant ion.
    Type: Application
    Filed: June 9, 2011
    Publication date: December 13, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jeremy Wahl, Kingsuk Maitra
  • Patent number: 8329517
    Abstract: A method for manufacturing a pixel structure includes providing a substrate including a transistor region and a pixel region, forming at least one gate electrode on the transistor region, forming an insulating layer on the substrate to overlay the gate electrode, and forming a patterned semi-conductive layer on the surface of a portion of the insulating layer disposed on the transistor region and the pixel region. A patterned first protective layer is formed on a portion of the patterned semi-conductive layer corresponding to the gate electrode, and the patterned semi-conductive layer is doped without being overlaid by the patterned first protective layer.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: December 11, 2012
    Assignee: Chimei Innolux Corporation
    Inventor: Po-Ching Hsu
  • Patent number: 8309952
    Abstract: One embodiment of the present invention is a thin film transistor, including: an insulating substrate; a gate electrode and a gate insulator being formed on the insulating substrate, in this order; a source electrode and a drain electrode formed on the gate insulator, surface preparation of the source electrode and the drain electrode being performed with a compound having a functional group with an electron-withdrawing property; and a semiconductor film formed on the gate insulator, the film being formed between the source electrode and the drain electrode.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: November 13, 2012
    Assignee: Toppan Printing Co., Ltd.
    Inventors: Ryohei Matsubara, Mamoru Ishizaki
  • Patent number: 8309379
    Abstract: A method for fabricating a flexible display device including the steps of preparing a glass substrate, forming a flexible substrate on the glass substrate, the flexible substrate being formed by forming a semiconductor layer on the glass substrate, forming a first flexible layer on the semiconductor layer, forming an adhesive layer on the first flexible layer, and forming a second flexible layer on the adhesive layer, forming a thin film array on the flexible substrate, forming a display device on the thin film array, and separating the glass substrate from the semiconductor layer of the flexible substrate.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: November 13, 2012
    Assignee: LG Display Co., Ltd.
    Inventors: Dong-sik Park, Juhn-Suk Yoo, Soo-Young Yoon
  • Publication number: 20120261672
    Abstract: A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor.
    Type: Application
    Filed: April 12, 2011
    Publication date: October 18, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dureseti Chidambarrao, Ramachandran Muralidhar, Philip J. Oldiges, Viorel Ontalus
  • Publication number: 20120252175
    Abstract: A complementary metal-oxide semiconductor (CMOS) structure includes a substrate and a P-type field effect transistor (FET) and an N-type FET disposed adjacent to one another on the substrate. Each FET includes a silicon-on-insulator (SOI) region, a gate electrode disposed on the SOI region, a source stressor, and a drain stressor disposed across from the source stressor relative to the gate electrode, wherein proximities of the source stressor and the drain stressor to a channel of a respective FET are substantially equal.
    Type: Application
    Filed: March 19, 2012
    Publication date: October 4, 2012
    Applicant: International Business Machines Corporation
    Inventors: Amlan Majumdar, XINHUI WANG
  • Patent number: 8278720
    Abstract: A switching device has an input node, an output node, and a control node. The device includes: a substrate having a first side and a second side with a ground plane on the first side of the substrate and a mesa on the second side of the substrate. The mesa is made of a normally-conductive semiconductor material, and an isolation region substantially surrounds the mesa. A field effect transistor (FET) is on the mesa. The FET has an input terminal connected to the input node, an output terminal connected to the output node, and a gate. A capacitor is connected in series between the output terminal of the FET and the gate, and a resistor is connected in series between the control node and the gate. A gate electrode is directly connected to the gate. The gate electrode is disposed substantially entirely on the mesa.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: October 2, 2012
    Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: Ray Parkhurst, Shyh-Liang Fu
  • Patent number: 8274098
    Abstract: Provided are a field effect transistor, a logic circuit including the same and methods of manufacturing the same. The field effect transistor may include an ambipolar layer that includes a source region, a drain region, and a channel region between the source region and the drain region, wherein the source region, the drain region, and the channel region may be formed in a monolithic structure, a gate electrode on the channel region, and an insulating layer separating the gate electrode from the ambipolar layer, wherein the source region and the drain region have a width greater than that of the channel region in a second direction that crosses a first direction in which the source region and the drain region are connected to each other.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: September 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-jong Chung, Ran-ju Jung, Sun-ae Seo, Dong-chul Kim, Chang-won Lee
  • Publication number: 20120208329
    Abstract: Disclosed is an integrated circuit device having series-connected planar or non-planar field effect transistors (FETs) with integrated voltage equalization and a method of forming the device. The series-connected FETs comprise gates positioned along a semiconductor body to define the channel regions for the series-connected FETs. Source/drain regions are located within the semiconductor body on opposing sides of the channel regions such that each portion of the semiconductor body between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor. Integrated voltage equalization is achieved through a conformal conductive layer having a desired resistance and positioned over the series-connected FETs such that it is electrically isolated from the gates, but in contact with the source/drain regions within the semiconductor body.
    Type: Application
    Filed: April 25, 2012
    Publication date: August 16, 2012
    Applicant: International Business Machines Corporation
    Inventors: Andres Bryant, Edward J. Nowak
  • Publication number: 20120199909
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively.
    Type: Application
    Filed: April 19, 2012
    Publication date: August 9, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Schulz, Hongfa Luan
  • Patent number: 8236628
    Abstract: A method of manufacturing an array substrate comprising: forming a data line and a gate line which are crossed with each other and a gate electrode on a base substrate, and the data line is discontinuously disposed so as to be separated from the gate line or the gate line is discontinuously disposed so as to be separated from the data line; forming an active layer and a gate insulating layer including bridge via holes and a source electrode via hole on the base substrate, and the bridge via holes are located at positions respectively corresponding to adjacent discontinuous sections of the data line or adjacent discontinuous sections of the gate line, and the source electrode via hole is located at a position corresponding to the data line; and forming a pixel electrode, a source electrode, a drain electrode and a bridge line on the base substrate, and the pixel electrode and the drain electrode are formed integrally, and the source electrode is connected to the data line through the source electrode via hole,
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: August 7, 2012
    Assignee: Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Xiang Liu, Zhenyu Xie, Xu Chen
  • Patent number: 8236667
    Abstract: Ion injection is performed to a single crystal silicon wafer to form an ion injection layer, with the ion injection surface of the single crystal silicon wafer and/or the surface of the transparent insulation substrate are/is processed using plasma and/or ozone. The ion injection surface of the single crystal silicon wafer and the surface of the transparent insulation substrate are bonded to each other by bringing them into close contact with each other at room temperature. A silicon on insulator (SOI) wafer is obtained by mechanically peeling the single crystal silicon wafer by giving an impact to the ion injection layer, to form an SOI layer on the transparent insulation substrate, and thermal processing for flattening the SOI layer surface is performed to the SOI wafer, under an atmosphere of an inert gas, a hydrogen gas, and a mixture gas of them.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: August 7, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Atsuo Ito, Yoshihiro Kubota, Kiyoshi Mitani