Abstract: In an embodiment an apparatus includes a receptacle configured to receive a wafer, a light port configured to emit light from a source of light so as to shine the light on an edge of the wafer, wherein the light port is an opening located on a surface of the receptacle and a light sensitive element configured to receive light that passed the edge of the wafer and to form a detection signal based on the received light, wherein the light port is located underneath the wafer.

Abstract: A display panel has a substrate structure in which a short bar connected to a gate line of an electrostatic discharge protection transistor in a non-display area is also used as a repair line for reparing disconnection in a data line. The display panel is capable of protecting a driving circuit of the display panel from static electricity that may occur during a manufacturing process and has a reduced size of the non-display area by using the short bar as the repair line.

Abstract: Semiconductor structure and methods for manufacturing the same are disclosed.

Abstract: Disclosed are a field effect transistor structure and a method of forming the structure. A gate stack is formed on the wafer above a designated channel region. Spacer material is deposited and anisotropically etched until just prior to exposing any horizontal surfaces of the wafer or gate stack, thereby leaving relatively thin horizontal portions of spacer material on the wafer surface and relatively thick vertical portions of spacer material on the gate sidewalls. The remaining spacer material is selectively and isotropically etched just until the horizontal portions of spacer material are completely removed, thereby leaving only the vertical portions of the spacer material on the gate sidewalls. This selective isotropic etch removes the horizontal portions of spacer material without damaging the wafer surface. Raised epitaxial source/drain regions can be formed on the undamaged wafer surface adjacent to the gate sidewall spacers in order to tailor source/drain resistance values.

Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.

Abstract: A semiconductor device has a semiconductor substrate, a semiconductor fin which is formed on the semiconductor substrate, which has a long side direction and a short side direction, and which has a carbon-containing silicon film including an impurity and a silicon film formed on the carbon-containing silicon film, a gate electrode which is formed to face both side surfaces of the semiconductor fin in the short side direction, source and drain regions which are respectively formed in the semiconductor fin located in the direction of both sides in the long side direction of the semiconductor fin so as to sandwich the gate electrode, and an element isolation insulating film which is formed on the side surface of the semiconductor fin and between the gate electrode and the semiconductor substrate.

Abstract: Disclosed is a method of fabricating a semiconductor chip. The method includes forming a silicon layer; forming a first layer formed on the silicon layer and including a first seal ring surrounding a first chip area and a second seal ring surrounding a second chip area; and forming a second layer formed on the first layer and including a metal interconnection connecting one of the first and second chip areas and an external terminal.

Abstract: An integrated circuit on a semiconductor substrate has logic gates comprising FDSOI-type transistors made on said substrate, including at least one first transistor comprising a gate with a first work function, and including a transistor comprising a second work function, a memory including memory cells, each memory cell comprising FDSOI type transistors, including at least one third nMOS transistor with a gate presenting a third work function, the third transistor comprising a buried insulating layer and a ground plane at least one fourth pMOS transistor with a gate presenting said third work function, the fourth transistor comprising a buried insulating layer and a ground plane, the ground planes of the third and fourth transistors being made in a same well separating these ground planes from said substrate.

Abstract: Technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of the material constituting a wiring substrate is provided. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first board-on-chip-structure having a first integrated circuit die mounted over a substrate and the substrate having a substrate cavity; mounting a second board-on-chip-structure over the first board-on-chip-structure, the second board-on-chip-structure having a second integrated circuit die mounted under an interposer and the interposer having an interposer cavity; connecting the first board-on-chip-structure to the second board-on-chip-structure with an internal interconnect; and encapsulating the first board-on-chip-structure, the second board-on-chip-structure, and the internal interconnect with an encapsulation.

Abstract: A fabrication method of a chip scale package is provided, which includes forming a protection layer on the active surface of a chip and fixing the inactive surface of the chip to a transparent carrier; performing a molding process; removing the protection layer from the chip and performing a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the wiring layer formed in the RDL process and the chip electrode pads and even waste product as a result. Further, the transparent carrier employed in the invention can be separated by laser and repetitively used in the process to help reduce the fabrication cost.

Abstract: Embodiments of the present invention include a method of packaging semiconductor devices. The method comprises the steps of molding a surface of a wafer, sawing the wafer into individual devices, attaching the individual semiconductor device to an adhesive surface, molding the exposed surface, and sawing the wafer into individual semiconductor devices. The step of molding forms a continuous molded layer. The step of sawing results in each individual semiconductor having a molded layer. This molded layer corresponds to a portion of the continuous molded layer. The step of attaching includes attaching the molded layer of the individual semiconductor devices to the adhesive surface. The step of molding the exposed area includes molding an exposed area above the adhesive surface. This forms a solid expanse of material. The step of sawing the wafer into individual semiconductor devices includes sawing the solid expanse of material.

Abstract: A semiconductor device includes a semiconductor chip including a first conducting element, and a second conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a first location. It further includes a third conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a second location, and a fourth conducting element arranged outside the semiconductor chip. An encapsulating body encapsulates the semiconductor chip. A vertical projection of the fourth conducting element on the chip crosses the first conducting element between the first location and the second location. At least one of the second conducting element, third conducting element, and fourth conducting element extend over the semiconductor chip and the encapsulating body.

Abstract: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, metal layers are deposited everywhere except where a block of stop electroplating material exists. The stop electroplating material is obliterated, and a barrier layer is formed above the entire remaining structure. A sacrificial metal element is added above the barrier layer, and then the substrate is removed. After the semiconductor material between the individual dies is eradicated, any desired bonding pads and patterned circuitry are added to the semiconductor surface opposite the sacrificial metal element, a passivation layer is added to this surface, and then the sacrificial metal element is removed. Tape is added to the now exposed barrier layer, the passivation layer is removed, the resulting structure is flipped over, and the tape is expanded to separate the individual dies.

Abstract: To provide a technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of components of the material constituting a wiring substrate. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.

Abstract: This method for making complementary p and n MOSFET transistors with Schottky source and drain electrodes controlled by a gate electrode, comprising: making source and drain electrodes from a single silicide for both p and n transistors; segregating first impurities from groups II and III of the periodic table at the interface between the silicide and the channel of the p transistor, the complementary n transistor being masked; and segregating second impurities from groups V and VI of the periodic table, at the interface between the silicide and the channel of the n transistor, and the complementary p transistor being masked.

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Abstract: A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, the semiconductor packages may be at least partially singulated from the panel by making one or more cuts through the panel to define one or more edges of the semiconductor package. The one or more edges may be smoothed by applying a laminate to the edges. The edges receiving the laminate may include any edge between a top and bottom surface of the package.

Abstract: A fabricating method for a semiconductor device includes forming a heat spreading material on rear surface of the semiconductor wafer. The semiconductor wafer has a plurality of device areas and scribe lines which are arranged between the device areas. After the heat spreading material is formed on rear surface of the semiconductor wafer, the semiconductor wafer is separated at the scribe lines.

Abstract: A semiconductor device includes a base plate, at least one first conductive layer carried by the base plate, and a semiconductor constructing body formed on or above the base plate, and having a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base plate around the semiconductor constructing body. A plurality of second conductive layers are formed on the insulating layer and electrically connected to the external connecting electrodes of the semiconductor constructing body. A vertical conducting portion is formed on side surfaces of the insulating film and base plate, and electrically connects the first conductive layer and at least one of the second conductive layers.

Abstract: High-voltage device structures, methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes, and design structures for high-voltage circuits. The planar device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a semiconductor body positioned between two gate electrodes. The gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrent with a process forming device isolation regions.

Abstract: Methods and systems for imaging and cutting semiconductor wafers and other microelectronic device substrates are disclosed herein. In one embodiment, a system for singulating microelectronic devices from a substrate includes an X-ray imaging system having an X-ray source spaced apart from an X-ray detector. The X-ray source can emit a beam of X-rays through the substrate and onto the X-ray detector, and X-ray detector can generate an X-ray image of at least a portion of the substrate. A method in accordance with another embodiment includes detecting spacing information for irregularly spaced dies of a semiconductor workpiece. The method can further include automatically controlling a process for singulating the dies of the semiconductor workpiece, based at least in part on the spacing information. For example, individual dies can be singulated from a workpiece via non-straight line cuts and/or multiple cutter passes.

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Abstract: A specially designed mask controls the arrangement of conductive materials that form a source and drain of a transistor. Designing the mask can be costly and time-consuming, which means that the testing of a circuit involving a transistor can also be costly, time consuming and a barrier towards efficient circuit development and testing. Accordingly, the present invention provides a pre-fabricated, general-purpose pattern comprising an array of conductive islands. The pattern is used as a source and a drain terminal for the formation of a thin-film transistor and as a conductive source for the formation of other electrical components upon the array.

Abstract: A semiconductor device includes an element isolation region formed in a semiconductor substrate, an active region surrounded by the element isolation region, and a gate electrode formed in one direction to cross the active region. The semiconductor substrate includes two gate trenches formed in parallel to a major axis direction of the active region in the active region, and a fin-shaped part which is located between the two gate trenches. The gate electrode is buried in the two gate trenches and formed on the fin-shaped part. The fin-shaped part serves as a channel region. A fin field effect transistor in which a width of the channel region is smaller than a gate length is thereby obtained.

Abstract: An all-optical cross-connect switching system provides optical switching that may reduce processing requirements by three orders of magnitude over conventional techniques by associating at least one optical detector with an optical beam steering element. In one embodiment, a first beam steering element, having a reflective surface in optical association with a first optical fiber array, and a second beam steering element, having a reflective surface in optical association with a second optical fiber array, are optically arranged to direct an optical beam from a first optical fiber in the first optical fiber array to a second optical fiber in the second optical fiber array. The optical detector provides information about a first position of the optical beam on the second beam steering element. Based on this information, the angle of the first beam steering element may be adjusted to cause the optical beam to change to a second position on the second beam steering element.

Abstract: Disclosed is a flat panel display which comprises a substrate; a gate line formed on the substrate along a predetermined direction; and a gate electrode electrically connected to the gate line, and having a sheet resistance different from the gate line. With this configuration, a wiring resistance of the gate line can be lowered with minimizing the change of the process and without increasing the thickness of the gate line.

Abstract: An LED package and method for producing the same are described. The LED package has an LED die with a conductive region-forming surface and a plurality of conductive regions disposed on the conductive region-forming surface. An insulation layer is formed on the conductive region-forming surface of the LED die, and has a plurality of openings corresponding to the conductive regions, respectively. A conductive member fills a respective opening, and is electrically connected a respective conductive regions to an exterior circuit.