Abstract: A substrate for a semiconductor package having a reinforcing member that prevents or minimizes distortions is presented. The substrate for the semiconductor package includes a substrate body, an insulation layer, and a reinforcing member. The substrate body has a first region having a plurality of chip mount regions, a second region disposed along a periphery of the first region, a circuit pattern disposed in each chip mount region and a dummy pattern disposed along the second region. The insulation layer covers the first and second regions and has an opening exposing some portion of each circuit pattern. The reinforcing member is disposed in the second region and prevents deflection of the substrate body.

Abstract: An object of the present invention is to provide a ferroelectric element having excellent properties, which includes a monocrystalline film of ?-Al2O3 formed as a buffer layer on a silicon substrate. The monocrystalline ?-Al2O3 film 6 is formed on the silicon substrate 4 which is the lowermost layer of an MFMIS structure 2. On the monocrystalline ?-Al2O3 film 6, there is formed an electrically conductive oxide in the form of a LaNiO3 film 8 as a lower electrode. On the LaNiO3 film 8, there is formed a PZT thin film 10 which is a ferroelectric material. ON the PZT thin film 10, there is formed a Pt film as an upper electrode.

Abstract: Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. A first die and a first through-casing interconnects are electrically coupled to the first interposer substrate. A first casing at least partially encapsulates the first device such that a portion of each first interconnect is accessible at a top portion of the first casing. A second known good packaged microelectronic device is coupled to the first device in a stacked configuration. The second device can include a second interposer substrate having a plurality of second interposer pads and a second die electrically coupled to the second interposer substrate. The exposed portions of the first interconnects are electrically coupled to corresponding second interposer pads.

Abstract: A method for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: lithographically forming, in a first lithographically processable material disposed on the surface portion of the semiconductor wafer, device exposing openings to expose the devices and electrical contact pad openings to expose electrical contact pads for devices; and mounting a support having a rigid dielectric layer formed on a selected portion of the support, such rigid dielectric layer comprising a second lithographically processable material, such rigid material being suspended over the device exposing openings and removed from portions of the support disposed over the electrical contacts pads openings in the first lithographically processable material. The support is released and removed from the second lithographically processable material, leaving the second photolithographically processable material bonded to the first photolithographically processable material.

Abstract: A collective substrate (1) is produced by firing a ceramic green sheet and forming through-holes (11) in the resulting substrate. The through-holes (11) each have an interior surface including taper surfaces (11b, 11c) which are tapered as having an opening size progressively decreasing from a main surface (21) and an external connection surface (22) toward a minimum size hole portion (11a). The taper surfaces (11b, 11c) respectively form obtuse angles ?1, ?2 with the main surface (21) and the external connection surface (22). A semiconductor element mount (BL) includes an insulative member (2) cut out of the collective substrate (1). An imaging device (PE2) includes an imaging element (PE1) mounted in a region surrounded by a frame (4) which is bonded to the main surface (21) of the insulative member (2) and closed by a cover (FL).

Abstract: The present invention provides a semiconductor module having: a semiconductor device (10) having a contact device (11) for making electrical contact with a connection device (17; 20) via a rewiring device (15, 15?, 15?); and a carrier device (12, 13, 14) for mechanically coupling the semiconductor device (10) to a connection device (17), the carrier device (12, 13, 14) having a gradient between a first modulus of elasticity at the semiconductor device (10) and a second, higher modulus of elasticity at the connection device (17; 20). The present invention likewise provides a method for producing a semiconductor module.

Abstract: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Abstract: A method for fabricating bonded substrate structures, e.g., silicon on silicon. In a specific embodiment, the method includes providing a thickness of single crystal silicon material transferred from a first silicon substrate coupled to a second silicon substrate. In a specific embodiment, the second silicon substrate has a second surface region that is joined to a first surface region from the thickness of single crystal silicon material to form of an interface region having a first characteristic including a silicon oxide material between the thickness of single crystal silicon material and the second silicon substrate. The method includes subjecting the interface region to a thermal process to cause a change to the interface region from the first characteristic to a second characteristic.

Abstract: A structure for sufficiently alleviating the thermal stress between an LSI and substrate and allowing the LSI to be detached from a substrate easily is provided. In a flip-chip type assembly according to the present invention, an interposer made of silicon intervenes between the device and the substrate. The LSI and the interposer are connected with a solder and, the interposer and the substrate are connected with a conductive resin. The conductive resin alleviates the thermal stress between the substrate and the interposer. The LSI can be detached easily by heating the solder. The thermal stress between the LSI and the interposer can be reduced because both of them are made of silicon.

Abstract: One aspect includes an electronic device including an integrated component with a substrate. An electrically conductive first layer region is arranged at the substrate, wherein the layer thickness of the first layer region is greater than 10 micrometers or greater than 50 micrometers.

Abstract: The present invention includes a base, a rectification chip, a conductive element and a coupling collar. The base has an installation pedestal to hold the rectification chip surrounded by an insulation portion. The conductive element has a root portion to connect the rectification chip. The root portion is extended to form a buffer section. The coupling collar is located at one end of the base to hold the package. The installation pedestal and the inner rim of the base are interposed by a gap. At least one hook portion is formed between the installation pedestal and the bottom of the gap. Thus the base does not turn against the package. The coupling collar has two ends formed an area different from any cross section area of the inner wall thereof.

Abstract: A composite substrate is disclosed. In one aspect, the substrate has a stretchable and/or flexible material. The substrate may further have patterned features embedded in the stretchable and/or flexible material. The patterned features have one or more patterned conducting layers.

Abstract: A stacked semiconductor package including a number of solder ball pads formed on a lower surface of an interposing print circuit board, which is smaller than that of solder ball pads formed on an upper surface thereof, a pitch of the solder ball pads formed on the lower surface of the interposing print circuit board is greater than a pitch of the solder ball pads formed on the upper interposing print circuit board.

Abstract: A method of manufacturing semiconductor devices by applying a pattern of adhesive pads on an active surface of a semiconductor wafer, the semiconductor wafer product so made and a stacked die package in which an adhesive wall leaves an air gap atop a bottom die. The wall may be in the form of a ring of adhesive about a central hollow area. The wafer carrying the pattern of adhesive pads on its active surface is singulated into individual dies, each die having an adhesive pad thereon. The bottom die is attached to a base with an adhesive which cures without curing the adhesive pad.

Abstract: This invention moderates the difficulty in chip formation or packaging which accompanies thinning of a semiconductor region where an integrated circuit is formed. An integrated circuit chip manufacturing method includes a first bonding step of bonding a first support member to a first surface of a semiconductor substrate which has the first surface and a second surface and has a semiconductor region including an integrated circuit on a first surface side thereof, a thinning step of removing a second surface-side portion of the semiconductor substrate bonded to the first support member to leave the semiconductor region, thereby thinning the semiconductor substrate, a second bonding step of bonding a second support member to the second surface side of the thinned semiconductor substrate, and a chip forming step of forming chips by cutting the semiconductor region.

Abstract: A semiconductor plastic package and a method of fabricating the semiconductor plastic package are disclosed. A method of fabricating a semiconductor plastic package can include: providing a core board, which includes at least one pad, and which has a coefficient of thermal expansion of 9 ppm/° C. or lower; stacking a build-up insulation layer over the core board; forming an opening by removing a portion of the build-up insulation layer such that the pad is exposed to the exterior; and placing a semiconductor chip in the opening and electrically connecting the semiconductor chip with the pad. This method can be utilized to provide higher reliability in the connection between the semiconductor chip and the circuit board.

Abstract: A method of fabricating a substrate core structure, and a substrate core structure formed according to the method. The method includes: laser drilling a first set of via openings through a starting insulating layer; filling the first set of via openings with a conductive material to provide a first set of conductive vias; providing first and second patterned conductive layers on opposite sides of the starting insulating layer; providing a supplemental insulating layer onto the first patterned conductive layer; laser drilling a second set of via openings through the supplemental insulating layer; filling the second set of via openings with a conductive material to provide a second set of conductive vias; and providing a supplemental patterned conductive layer onto an exposed side of the supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer and the supplemental patterned conductive layer at opposite sides thereof.

Abstract: A method of producing a leadframe is provided, the method including the steps of providing a substrate, plating the substrate with a layer of tin, plating a layer of nickel over the layer of tin, and thereafter plating one or more protective layers over the layer of nickel. The leadframe may thereafter be heated to produce one or more intermetallic layers comprising tin, which impedes the out-diffusion of copper from a base material of the leadframe to the surface thereof.

Abstract: A substrate having a bending region and conductive paths formed therethrough is provided. In one embodiment, conductive paths are formed from a first region on the bottom surface of the substrate, through the bending region and to a second region on the top surface of the substrate. Methods of using the flexible substrate are also provided.

Abstract: Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages.

Abstract: A wiring board has a base insulating film. The base insulating film has a thickness of 20 to 100 ?m and is made of a heat-resistant resin which has a glass-transition temperature of 150° C. or higher and which contains reinforcing fibers made of glass or aramid. The base insulating film has the following physical properties (1) to (6) when an elastic modulus at a temperature of T° C. is given as DT (GPa) and a breaking strength at a temperature of T° C. is given as HT (MPa). (1) A coefficient of thermal expansion in the direction of thickness thereof is 90 ppm/K or less. (2) D23?5 (3) D150?2.5 (4) (D?65/D150)?3.0 (5) H23?140 (6) (H?65/H150)?2.

Abstract: The semiconductor device includes a plurality of semiconductor chips, and a circuit substrate having a substantially rectangular outer shape. The semiconductor device is an MCM having an MCM packaging structure in which the plurality of semiconductor chips are juxtaposed on the semiconductor chip mounting surface of the circuit substrate, and the semiconductor chip mounting surface is covered by a sealing resin along an outer edge of the circuit substrate so that the plurality of semiconductor chips are sealed.

Abstract: A ball attaching apparatus for respectively attaching solder balls onto a plurality of ball lands of a material which has mold caps formed between the ball lands. The apparatus includes an indexer on which the material is seated and fixed; a holder located above the indexer such that it can be raised and lowered; an attachment plate installed on a lower surface of the holder, having projections at positions corresponding to the mold caps of the material, and defined with grooves at positions corresponding to the ball lands of the material, in which the solder balls are placed; and eject pins arranged in the respective grooves of the attachment plate for conveying and dropping the solder balls through introduction and removal of vacuum.

Abstract: An explanation is given of, inter alia, an electronic device (10), comprising: an integrated component (12) with a substrate, an electrically conductive first layer region (14), arranged at the substrate, wherein the layer thickness of the first layer region is greater than 10 micrometres or greater than 50 micrometres.

Abstract: A collective substrate (1) is produced by firing a ceramic green sheet and forming through-holes (11) in the resulting substrate. The through-holes (11) each have an interior surface including taper surfaces (11b, 11c) which are tapered as having an opening size progressively decreasing from a main surface (21) and an external connection surface (22) toward a minimum size hole portion (11a). The taper surfaces (11b, 11c) respectively form obtuse angles ?1, ?2 with the main surface (21) and the external connection surface (22). A semiconductor element mount (BL) includes an insulative member (2) cut out of the collective substrate (1). An imaging device (PE2) includes an imaging element (PE1) mounted in a region surrounded by a frame (4) which is bonded to the main surface (21) of the insulative member (2) and closed by a cover (FL).

Abstract: An integrated circuit product includes a die and an insulation layer. The insulation layer is operatively coupled to the die. The insulation layer includes a plurality of bump apertures. The insulation layer also includes an underfill anchor structure. Methods for making such an integrated circuit product are also described.

Abstract: There is provided a semiconductor package including: a substrate having a plurality of electrode pads on a surface thereof; a semiconductor chip mounted on the substrate, the semiconductor chip electrically connecting with the plurality of electrode pads; and a stiffener arranged on the substrate so as to surround the semiconductor chip. The stiffener includes: an insulating material layer; and a rigid plate mounted substantially parallel to a surface of the substrate in the insulating material layer, the rigid plate having formed therein a plurality of through holes, at least a part of the through holes being filled with the insulating material.

Abstract: A resin-sealed semiconductor device includes a metal frame, an electronic substrate, an adhesive agent, a molded resin, and a bonding agent. The electronic substrate includes a first surface having a circuit element wiring part, a second surface facing the metal frame, and a side surface arranged approximately perpendicularly to the first surface and the second surface. The adhesive agent is disposed between the metal frame and the second surface to cover the second surface and a portion of the side surface adjacent to the second surface. The molded resin covers the metal frame and the electronic substrate, and holds the other portion of the side surface adjacent to the first surface. The bonding agent is disposed between the circuit element wiring part and the molded resin so that the molded resin holds the circuit element wiring part through the bonding agent.

Abstract: The specification describes a multi-chip module (MCM) that contains an integrated passive device (IPD) as the carrier substrate (IPD MCM). Parasitic electrical interactions are controlled at one or both interfaces of the IPD either by eliminating metal from the interfaces, or by selective use of metal in parts of the MCM that are remote from the sensitive device components. The sensitive device components are primarily analog circuit components, especially RF inductor elements. In the IPD layout, the sensitive components are segregated from other components. This allows implementation of the selective metal approach. It also allows parasitic interactions on top of the IPD substrate to be reduced by selective placement of IC semiconductor chips and IC chip ground planes. In preferred embodiments of the IPD MCM of the invention, the IPD substrate is polysilicon, to further minimize RF interactions. The various methods of assembling the module may be adapted to keep the overall thickness within 1.0 mm.

Abstract: A member for a semiconductor device of low price, capable of forming a high quality plating layer on a surface, having heat conductivity at high temperature (100° C.) of more than or equal to 180 W/m·K and toughness that will not cause breaking due to screwing, and will not cause solder breaking due to heat stress when it is bonded to other member with solder, and a production method thereof are provided. A member for a semiconductor device (1) having a coefficient of thermal expansion ranging from 6.5×10?6/K to 15×10?6/K inclusive, and heat conductivity at 100° C.

Abstract: An electronic module with an integrated electromagnetic shield using surface mount shield wall components has been disclosed. Each surface mount shield wall component provides side shielding of circuitry within the overmolded electronic module and provides an exposed conductive shield wall section to which a top conductive shield can be applied. By including the shield structure as part of the overmolded electronic module, the need for a separate shield and separate process steps for installing the separate shield can be eliminated. Each surface mount shield wall component comprises a non-conductive portion that provides stability during a reflow soldering process, but at least a sacrificial portion of the non-conductive portion can be removed to reduce the amount of area occupied by the overmoldable shield structure.

Abstract: One aspect of the invention relates to a semiconductor device including a housing and a semiconductor chip partly embedded in a plastic housing composition. Another aspect relates to a method for producing the same. The plastic housing composition has at least one host component having a softening temperature and an incorporated component having a phase change temperature. In this case, the softening temperature of the host component is greater than the phase change temperature of the incorporated component.

Abstract: A high-density electrical package utilizing an array of high performance demountable electrical contacts such as UEC, T-Spring, F-Spring and their equivalent contained in a carrier in the form of an interposer between one or more components and a substrate. The carrier is made of a thermally conductive metal or contains thermally conductive metal to provide heat-spreading or dissipation functions in addition to the function of the retention and alignment of the electrical contacts. The above interposer is used for chip attach for a single chip or a stack of chips in the package. The interposer provides electrical connections through individual electrical contact to another chip or to the substrate of the package. It provides also the heat spreading or dissipation function to the chips connected thermally to a particular interposer. The interposer can further be connected thermally to an external heat spreader when necessary.

Abstract: A method of sealing and leading out an electrode for an MEMS device such as an angular velocity sensor, an acceleration sensor, or a combined sensor is provided. A fixed portion is formed within a device forming region surrounded with a base support, a beam is connected to the fixed portion, and a movable portion is connected to the beam. Further, a detection portion for detecting the displacement of the movable portion is disposed within the device forming region. An interconnection is connected to the movable portion and the detection portion, and the interconnection extends from the hermetically sealed device forming region to the external region at the outside. The interconnection penetrates the base support and is connected with the terminal. A hole is formed between the interconnection and the base support, and an insulating film is formed in the hole. The interconnection and the base support are insulated by an insulating film buried in the hole.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: A Chip on Flexible Printed Circuit (COF) type semiconductor package may include a flexible film, a semiconductor IC chip on the flexible film, and a heating pad on the flexible film.

Abstract: It is to provide a wiring board for a semiconductor integrated circuit package, which exhibits an excellent signal property and a high effect for decreasing the switching noise at the time of mounting an LSI of an area-array structure. In a multilayer wiring board for a package, which comprises, on a wiring layer of an LSI chip mount surface, a ground pad, a power supply pad, and a signal pad for mounting LSI chip, and a ground plane that extends around a group of those pads, the ground pad disposed on the inner side, among the above-described pads, is connected to the ground plane that surrounds the pad group through a connecting wiring.

Abstract: A method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper.

Abstract: A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (302) and a plurality of lead segments (303). Covering the base metal are, consecutively, a continuous nickel layer (201) on the base metal, a layer of palladium on the nickel, wherein the palladium layer (203) on the chip side of the structure is thicker than the palladium layer (202) opposite the chip, and a gold layer (204) on the palladium layer (202) opposite the chip. A semiconductor chip (310) is attached to the chip mount pad and conductive connections (312) span from the chip to the lead segments. Polymeric encapsulation compound (320) covers the chip, the connections, and portions of the lead segments, but leaves other segment portions available for solder reflow attachment to external parts.

Abstract: A die structural support apparatus and method are disclosed, in which a die component is provided. A support element can be configured for use with the die component, wherein said support element surrounds said die component, thereby strengthening said die component to provide a surrounding die support structure thereof. The die component preferably constitutes a SAW die, and may be formed from, for example, quartz. The support element can be molded, stamped, cast, machined and so forth and is preferably located with respect to the SAW die after the SAW die is formed.

Abstract: Disclosed are a wafer level stacked package and its manufacturing method. As one example, in such a wafer level stacked package, a first semiconductor die is electrically connected to an upper surface of a substrate and a second semiconductor die is electrically connected to a lower surface of the substrate. That is, with respect to one substrate, semiconductor dies can be stacked on upper and lower surfaces of the substrate. Also, underfill is formed between the respective semiconductor dies and the substrate, thereby enhancing bonding forces between the respective semiconductor dies and the substrate. In addition to stacking the semiconductor dies, packages can be stacked with each other. That is, it is possible to stack a plurality of completed wafer level packages with each other in an up-and-down direction.