Abstract: A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone.

Abstract: Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.

Abstract: There is provided a semiconductor device substrate including: a multi-layer wiring layer; a first capacitor pad which is provided on an uppermost layer of the multi-layer wiring layer, and which includes a first power supply pad connected to a power supply layer of the multi-layer wiring layer through a first via and a first ground pad connected to a ground layer of the multi-layer wiring layer through a second via; and a second capacitor pad which is provided on the uppermost layer of the multi-layer wiring layer, and which includes a second power supply pad connected to the first power supply pad through a first wire and a second ground pad connected to the first ground pad through a second wire.

Abstract: A semiconductor device comprises a semiconductor substrate; an element-forming region that includes semiconductor elements formed on the semiconductor substrate; a buried electrode plug formed so as to penetrate through the semiconductor substrate; and a trench-type electrode that is buried in a trench within the semiconductor substrate positioned between the element-forming region and the buried electrode plug.

Abstract: There is provided a semiconductor device and a method of fabricating the same. The method of fabricating a semiconductor device according to the present invention comprises: forming a transistor structure including a gate, and source and drain regions on a semiconductor substrate; carrying out a first silicidation to form a first metal silicide layer on the source and drain regions; depositing a first dielectric layer on the substrate, the top of the first dielectric layer being flush with the top of the gate region; forming contact holes at the portions corresponding to the source and drain regions in the first dielectric layer; and carrying out a second silicidation to form a second metal silicide at the gate region and in the contact holes, wherein the first metal silicide layer is formed to prevent silicidation from occurring at the source and drain regions during the second silicidation.

Abstract: At a semiconductor device, an integrated circuit including an optoelectronic conversion device is formed on a front face of a sensor chip. A rewiring layer, which leads from pad electrodes, and post electrodes, on the rewiring layer, are formed on the sensor chip. At least a portion of surroundings of the rewiring layer and the post electrodes is sealed with sealing resin, so as to be open above the integrated circuit face. A light-transmissive substrate is disposed over the sealed sensor chip. Penetrating electrodes, corresponding with positions of the post electrodes disposed on the sensor chip, are formed in the light-transmissive substrate, and external terminals such as solder balls or the like are formed so as to electrically connect with the penetrating electrodes.

Abstract: A method (112) of forming a sensor panel (146) that includes an array (144) of sensor structures (22, 24) encapsulated in a mold material (148) and forming a controller panel (158) that includes an array (156) of controller dies (26) encapsulated in a mold material (160). The arrays (144, 156) are arranged so that locations of the sensor structures (22, 24) correspond with locations of the controller dies (26). The controller panel (158) is bonded (162) to the sensor panel (146) to form a stacked panel structure (164). After bonding, methodology (112) entails forming (178) conductive elements (84) on the controller dies (26), removing (174) material sections (126, 142, 168) from the controller panel 158 and the sensor panel (146) to expose bond pads (42, 58), forming (178) electrical interconnects (80), applying (182) packaging material (90), and singulating (196) the stacked panel structure (164) to produce sensor packages (20, 104).

Abstract: A system and method for forming a TSV contact is presented. A preferred embodiment includes a TSV in contact with a portion of the uppermost metal layer of a semiconductor die. The interface between the TSV conductor and the contact pad is preferably characterized by a non-planar zigzag pattern that forms a grid pattern of contacts. Alternatively, the contacts may form a plurality of metal lines that make contact with the contact pad.

Abstract: A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

Abstract: An object of the present invention is to sufficiently supply power to three-dimensionally stacked LSI chips and to dispose common through vias in chips of different types. Also, another object is to propose a new test method for power-supply through silicon vias.

Abstract: An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads.

Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.

Abstract: The invention discloses a package structure with at least one portion of a first conductive element disposed in a through-opening of a first substrate. A conductive structure is disposed on the first substrate and the first conductive element, wherein the conductive structure is electrically connected to the first substrate and said at least one first I/O terminal of the first conductive element. The conductive structure comprises at least one of a second conductive element, a second substrate or a conductive pattern.

Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.

Abstract: A semiconducting multi-layer structure comprising a plurality of first conductive layers, a plurality of first insulating layers and a second conductive layer is disclosed. The first conductive layers are separately disposed. Each of the first conductive layers has an upper surface, a bottom surface opposite to the upper surface and a lateral surface. The first insulating layers surround the peripherals of the first conductive layers. Each of the first insulating layers covers at least a part of the upper surface of each of the first conductive layers, at least a part of the bottom surface of each of the first conductive layers and the two lateral surface of each of the first conductive layers. The second conductive layer covers the first conductive layers and the first insulating layers.

Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer.

Abstract: A semiconductor package is provided, which includes: a soft layer having opposite first and second surfaces and first conductive through hole vias; a chip embedded in the soft layer and having an active surface exposed from the first surface of the soft layer; a support layer formed on the second surface of the soft layer and having second conductive through hole vias in electrical connection with the first conductive through hole vias; a first RDL structure formed on the first surface of the soft layer and electrically connected to the active surface of the chip; and a second RDL structure formed on the support layer and electrically connected to the first RDL structure through the first and second conductive through hole vias. The invention prevents package warpage by providing the support layer, and allows disposing of other packages or electronic elements by electrically connecting the RDL structures through the conductive through hole vias.

Abstract: Wafer-scale packaging structures and methods are provided for integrally packaging antenna structures with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems for millimeter wave (mmWave) and Terahertz (THz) applications. For example, a chip package includes an RFIC chip, an antenna structure and an interface layer. The RFIC chip includes a semiconductor substrate having an active surface and an inactive surface, and a BEOL (back end of line) structure formed on the active surface of the semiconductor substrate. The antenna structure includes an antenna substrate and a planar antenna radiator formed on a surface of the antenna substrate, wherein the antenna substrate is formed of a low loss semiconductor material. The interface layer connects the antenna structure to the BEOL structure of the RFIC chip.

Abstract: Conductive lines are deposited on a substrate to produce traces for conducting electricity between electronic components. A patterned metal layer is formed on the substrate, and then a layer of material having a low thermal conductivity is coated over the patterned metal layer and the substrate. Vias are formed through the layer of material having the low thermal conductivity thereby exposing portions of the patterned metal layer. A film of conductive ink is then coated over the layer of material having the low thermal conductivity and into the vias to thereby coat the portions of the patterned metal layer, and then sintered. The film of conductive ink coated over the portion of the patterned metal layer does not absorb as much energy from the sintering as the film of conductive ink coated over the layer of material having the low thermal conductivity. The layer of material having the low thermal conductivity may be a polymer, such as polyimide.

Abstract: Among other things, a semiconductor seal ring and method for forming the same are provided. The semiconductor seal ring comprises a plurality of dielectric layers formed over a semiconductor substrate upon which a semiconductor device is formed. A plurality of conductive layers is arranged among at least some of the plurality of dielectric layers. An upper conductive layer is formed over the plurality of dielectric layers. An upper passivation layer is formed over the upper conductive layer to isolate the upper conductive layer from conductive debris resulting from a die saw process along a die saw cut line. In an example, a first columnar region comprising a first portion of the conductive layers is electrically isolated from the semiconductor device because the first columnar region is disposed relatively close to the die saw cut line and thus can be exposed to conductive debris which can cause undesired short circuits.

Abstract: A method of fabricating a semiconductor package is provided, including: disposing a semiconductor element on a carrier; forming an encapsulant on the carrier to encapsulant the semiconductor element; forming at least one through hole penetrating the encapsulant; forming a hollow conductive through hole in the through hole and, at the same time, forming a circuit layer on an active surface of the semiconductor element and the encapsulant; forming an insulating layer on the circuit layer; and removing the carrier. By forming the conductive through hole and the circuit layer simultaneously, the invention eliminates the need to form a dielectric layer before forming the circuit layer and dispenses with the conventional chemical mechanical polishing (CMP) process, thus greatly improving the fabrication efficiency.

Abstract: A microelectronic package includes first and second encapsulated microelectronic elements, each of which includes a semiconductor die having a front face and contacts thereon. An encapsulant contacts at least an edge surface of each semiconductor die and extends in at least one lateral direction therefrom. Electrically conductive elements extend from the contacts and over the front face to locations overlying the encapsulant. The first and second microelectronic elements are affixed to one another such that one of the front or back surfaces of one of the first and second semiconductor dies is oriented towards one of the front or back surfaces of the other of the first and second semiconductor dies. A plurality of electrically conductive interconnects extend through the encapsulants of the first and second microelectronic elements and are electrically connected with at least one semiconductor die of the first and second microelectronic elements by the conductive elements.

Abstract: A method, and the resulting structure, to make a thinned substrate with backside redistribution wiring connected to through silicon vias of varying height. The method includes thinning a backside of a substrate to expose through silicon vias. Then a thick insulator stack, including an etch stop layer, is deposited and planarized. With a planar insulating surface in place, openings in the insulator stack can be formed by etching. The etch stop layer in the dielectric stack accommodates the differing heights vias. The etch stop is removed and a conductor having a liner is formed in the opening. The method gives a unique structure in which a liner around the bottom of the through silicon via remains in tact. Thus, the liner of the via and a liner of the conductor meet to form a double liner at the via/conductor junction.

Abstract: A structure for an integrated circuit with reduced contact resistance is disclosed. The structure includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the cap layer, and a trench embedded in the dielectric layer. The trench includes an atomic layer deposition (ALD) TaN or a chemical vapor deposition (CVD) TaN deposited on a side wall of the trench, a physical vapor deposition (PVD) Ta or a combination of the PVD Ta and a PVD TaN deposited on the ALD TaN or CVD TaN, and a Cu deposited on the PVD Ta or the combination of the PVD Ta and the PVD TaN deposited on the ALD TaN or the CVD TaN. The structure further includes a via integrated into the trench at bottom of the filled trench.

Abstract: Semiconductor devices and methods for forming a semiconductor device are disclosed. The semiconductor device includes a die. The die includes a die substrate having first and second major surfaces. The semiconductor device includes a power module disposed below the second major surface of the die substrate. The power module is electrically coupled to the die through through silicon via (TSV) contacts.

Abstract: An apparatus is disclosed for the examination and inspection of integrated devices such as integrated circuits. X-rays are transmitted through the integrated device, and are incident on a photoemissive structure that absorbs x-rays and emits electrons. The electrons emitted by the photoemissive structure are shaped by an electron optical system to form a magnified image of the emitted electrons on a detector. This magnified image is then recorded and processed. In some embodiments, the integrated device and photoemissive structure are independently mounted and controlled. In other embodiments, the photoemissive device is deposited directly onto the integrated device. In some embodiments, the incidence angle of the x-rays is varied to allow internal three-dimensional structures of the integrated device to be determined. In other embodiments, the recorded image is compared with a reference data to enable inspection for manufacturing quality control.

Abstract: The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.

Abstract: Disclosed herein is a method of manufacturing a bonded substrate, including the steps of: forming a first bonding layer on a surface on one side of a semiconductor substrate; forming a second bonding layer on a surface on one side of a support substrate; adhering the first bonding layer and the second bonding layer to each other; a heat treatment for bonding the first bonding layer and the second bonding layer to each other; and thinning the semiconductor substrate from a surface on the other side of the semiconductor substrate to form a semiconductor layer.

Abstract: Devices and systems for insulating integrated circuits from ultraviolet (“UV”) light are described. The device includes a conductive feature, a first and second UV blocking layer, a first and second insulating laver, and a conductive structure. The first insulating layer overlays the first UV blocking layer. A via opening extends through the first insulating layer and the first UV blocking layer. The second UV blocking layer overlays the first insulating laver. The second insulating layer overlays the second UV blocking layer. An interconnect trench is defined in the second insulating layer and second UV blocking layer. The conductive structure is electrically connected to the conductive feature and extends into the via opening and along the interconnect trench.

Abstract: Stress barrier structures for semiconductor chips, and methods of fabrication thereof are described. In one embodiment, the semiconductor device includes a semiconductor substrate that includes active circuitry and an interconnect metallization structure over the active circuitry, wherein the interconnect metallization structure includes a layer of low-k insulating layer. A first metal bump is disposed over the semiconductor substrate and coupled to the active circuitry of the semiconductor substrate. A first stress barrier structure is disposed under the metal bump, and disposed over the low-k insulating layer, and a second substrate is disposed over the first metal bump.

Abstract: An opening such as a small-diameter via is formed in a semiconductor substrate such as a monocrystalline silicon chip or wafer by a high etch rate process which leaves the opening with a rough interior surface. A smoothing layer such as a polysilicon layer is applied over the interior surfaces of the openings. The smoothing layer presents a surface smoother than the original interior surface. An insulating layer is formed over the smoothing layer or formed from the smoothing layer, and a conductive element such as a metal is formed in the opening. In a variant, a glass-forming material such as BPSG is applied in the opening. The glass-forming material is reflowed to form a glassy insulating layer which presents a smooth surface. The interface between the metal conductive element and the insulating or glassy layer is smooth, which improves mechanical and electrical properties.

Abstract: A semiconductor device includes a word line, a bit line crossing the word line, an active region arranged in an oblique direction at the word line and the bit line, and a contact pad contacting the active region, where the contact pad extends in the oblique direction.

Abstract: This disclosure describes systems and methods for increasing the usable surface area of electrical contacts within a device, such as a thin film solid state device, through the implementation of electrically conductive interconnects. Embodiments described herein include the use of a plurality of electrically conductive interconnects that penetrate through a top contact layer, through one or more multiple layers, and into a bottom contact layer. The plurality of conductive interconnects may form horizontal and vertical cross-sectional patterns. The use of lasers to form the plurality of electrically conductive interconnects from reflowed layer material further aids in the manufacturing process of a device.

Abstract: A package for a microelectronic element, such as a semiconductor chip, has a dielectric mass overlying the package substrate and microelectronic element and has top terminals exposed at the top surface of the dielectric mass. Traces extending along edge surfaces of the dielectric mass desirably connect the top terminals to bottom terminals on the package substrate. The dielectric mass can be formed, for example, by molding or by application of a conformal layer.

Abstract: A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N?1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W?1 contact openings to create extended contact openings extending to W?1 conductive layers; 2n?1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.

Abstract: A substrate (1) of semiconductor material is provided with a contact pad (7). An opening (9) is formed through the semiconductor material from an upper surface to the contact pad, the opening forming an edge (18) at or near the upper surface. A dielectric layer (10) is applied on the semiconductor material in the opening. A metallization (11) is applied, which contacts the contact pad and is separated from the substrate by the dielectric layer. A top-metal (12) is applied, which contacts the metallization at or near the edge. A protection layer (13) is applied, which covers the top-metal and/or the metallization at least at or near the edge, and a passivation (15) is applied.

Abstract: A semiconductor device is provided to check through silicon via (TSV) connectivity at a wafer level. The semiconductor device includes a first metal layer formed over a through silicon via (TSV), a second metal layer and a third metal layer formed at both sides of the first metal layer to be electrically coupled to the TSV, and a fourth metal layer formed over the first metal layer to be electrically coupled to the first metal layer.

Abstract: A stacked semiconductor device and method of manufacturing a stacked semiconductor device are described. The semiconductor device may include a reconstituted base layer having a plurality of embedded semiconductor chips. A first redistribution layer may contact the electrically conductive contacts of the embedded chips and extend beyond the boundary of one or more of the embedded chips, forming a fan-out area. Another chip may be stacked above the chips embedded in the base layer and be electrically connected to the embedded chips by a second redistribution layer. Additional layers of chips may be included in the semiconductor device.

Abstract: Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform.

Abstract: A stacked redistribution layer (RDL) die assembly package includes a substrate, a first level RDL die assembly mounted to the substrate and a second level RDL die assembly mounted to the first level RDL die assembly. The first level RDL die assembly includes a first die comprising bond pads, a first fan out support extending outwardly from sides of the first die, and first traces electrically connected to the bond pads, the first traces being supported by the first fan out support. Similarly, the second level RDL die assembly includes a second die comprising bond pads, a second fan out support extending outwardly from sides of the second die, and second traces electrically connected to the bond pads of the second die, the second traces being supported by the second fan out support.

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Abstract: A MOSFET power chip includes a first vertical MOSFET and a second vertical MOSFET. The first vertical MOSFET includes a semiconductor body having a first surface defining a source and a second surface defining a drain and a gate structure formed in the semiconductor body near the second surface. A via is formed within the semiconductor body and is substantially perpendicular to the first surface and the second surface. The via has a first end electrically coupled to the first surface and a second end electrically coupled to the gate structure. The second vertical MOSFET includes a semiconductor body having a first surface defining a source, a second surface defining a drain and a gate structure formed in the semiconductor body near the first surface.

Abstract: A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.

Abstract: A method for manufacturing a through substrate via (TSV) structure, a TSV structure, and a control method of a TSV capacitance are provided. The method for manufacturing the TSV structure includes: providing a substrate having a first surface and a second surface; forming a trench in the first surface of the substrate; filling a low resistance material into the trench; forming an insulating layer on the first surface of the substrate; forming at least one opening in the first surface of the substrate, wherein the opening is located differently the trench; forming an oxide liner layer, a barrier layer and a conductive seed layer on a sidewall and a bottom of the opening and on the insulating layer of the first surface; and filling a conductive material into the opening, wherein the opening is used to form at least one via.

Abstract: A through-substrate via structure including a substrate, a conductive layer, and a parasitic capacitance modulation layer is provided. The substrate has at least one opening. The opening is filled with the conductive layer. The parasitic capacitance modulation layer is disposed between the conductive layer and the substrate. The parasitic capacitance modulation layer is placed around the through-substrate via to reduce the depletion capacitance and further reduce the parasitic capacitance of the through-substrate via. Therefore, during transmission of signals with high frequency, the parasitic capacitance around the through-substrate via is rather small and thereby the operation speed of devices is increased.

Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.

Abstract: A method comprises fabricating an interconnect structure comprising a plurality of conductive interconnects encased in a dielectric structure and coupling each of the conductive interconnects to a corresponding bond pad of a package substrate and bond pad of a die. A device package comprises a substrate having a first plurality of bond pads disposed at a first surface of the substrate and a die having a first surface facing the first surface of the substrate and a second surface opposite the first surface, the die comprising a second plurality of bond pads disposed at the second surface. The device package further comprises an interconnect structure comprising a plurality of conductive interconnects encased in a dielectric structure, each of the conductive interconnects coupled to a corresponding bond pad of the first plurality of bond pads and to a corresponding bond pad of the second plurality of bond pads.

Abstract: A through-hole electrode substrate related to an embodiment of the present invention is arranged with a semiconductor substrate having a plurality of through-holes, an insulating layer formed with an insulating material on the inner walls of the plurality of through-holes and on at least one surface of the semiconductor substrate, a plurality of through-hole electrodes formed with a metal material inside the through-hole, and a plurality of gas discharge parts formed to contact with each of the plurality of through-hole electrodes which is exposed on at least one surface of the semiconductor substrate, the plurality of gas discharge parts externally discharges gas which is discharged from the inside of the plurality of through-hole electrodes.

Abstract: An opening (9) is made in the substrate (1) over a terminal pad (7). A dielectric layer (10), a metallization (11), a compensation layer (13) and a passivation layer (15) are deposited so that the passivation layer is separated from the metallization by the compensation layer at least within the opening. A material that is suitable for reducing a mechanical stress between the metallization and the passivation layer is chosen for the compensation layer.

Abstract: An interconnect is provided in a first insulating layer and the upper surface of the interconnect is higher than the upper surface of the first insulating layer. An air gap is disposed between the interconnect and the first insulating layer. A second insulating layer is formed at least over the first insulating layer and the air gap. The second insulating layer does not cover the interconnect. An etching stopper film is formed at least over the second insulating layer. The etching stopper film is formed over the second insulating layer and the interconnect. A third insulating layer is formed over the etching stopper film. A via is provided in the third insulating layer so as to be connected to the interconnect.