Abstract: A microelectronic unit includes a semiconductor element having a front surface to which a packaging layer is attached, and a rear surface remote from the front surface. The element includes a light detector including a plurality of light detector element arranged in an array disposed adjacent to the front surface and arranged to receive light through the rear surface. The semiconductor element also includes an electrically conductive contact at the front surface connected to the light detector. The conductive contact includes a thin region and a thicker region which is thicker than the thin region. A conductive interconnect extends through the packaging layer to the thin region of the conductive contact, and a portion of the conductive interconnect is exposed at a surface of the microelectronic unit.

Abstract: A semiconductor chip includes: a first substrate having a first surface and a second surface facing away from the first surface; a first test through silicon via (TSV) passing through the first substrate from the first surface to the second surface; and a conductive protrusion coupled to the first test TSV and protruding from the second surface.

Abstract: A semiconductor device comprising a substrate, a power bus, a heat source circuit, a heat sensitive circuit, and a plurality of electrically and thermally conductive through-silicon-vias (TSVs) in the substrate. The TSVs are electrically coupled to the power bus and positioned between the heat source circuit and the heat sensitive circuit to absorb heat from the heat source circuit.

Abstract: A method for fabricating a copper interconnect structure is disclosed. A substrate having a conductive region is provided. An insulating layer with a via opening is formed on the substrate. The via opening exposes the conductive region. A copper layer is formed on the first insulating layer and fills the via opening by sequentially performing deposition and reflowing processes. A masking layer is formed on the copper layer to cover the via opening. The copper layer uncovered by the masking layer is anisotropically oxidized. The masking layer and the oxidized copper layer are removed by a wet etching process, to form a copper plug in the via opening and a copper wire line on the copper plug. A copper interconnect structure is also disclosed.

Abstract: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.

Abstract: Interposers for use in the fabrication of electronic devices include semiconductor-on-insulator structures having fluidic microchannels therein. The interposers may include a multi-layer body in which a semiconductor material is bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel may extend in a lateral direction through at least one of the layer of dielectric material and the semiconductor material. The interposers may include redistribution layers and electrical contacts on opposing sides thereof. Semiconductor structures include one or more semiconductor devices coupled with such interposers. Such interposers and semiconductor structures may be formed by fabricating a semiconductor-on-insulator type structure using a direct bonding method and defining one or more fluidic microchannels at a bonding interface during the direct bonding process.

Abstract: Semiconductor structures are fabricated that include a semiconductor material bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel extends in a lateral direction through the layer of dielectric material between the semiconductor material and the substrate. The at least one fluidic microchannel includes at least one laterally extending section having a transverse cross-sectional shape entirely surrounded by the layer of dielectric material.

Abstract: An interposer having decaps formed in blind-vias, a packaged semiconductor structure having decaps formed in blind-vias, and methods for forming the same are provided. In one embodiment, an interposer is provided that includes an interconnect layer disposed on a substrate. A plurality of through-vias are formed through the substrate in an isolated region of the substrate. At least one of the plurality of conductive vias are electrically coupled to at least one of a plurality of top wires formed in the interconnect layer. A plurality of blind-vias are formed through the substrate in a dense region of the substrate during a common etching step with the through-vias. At least one blind-via includes (a) a dielectric material lining the blind-vias, and (b) a conductive material filling the lined blind-vias and forming a decoupling capacitor.

Abstract: A cavity wafer for flip chip stacking includes an electrostatic (ESC) chuck wafer with a plurality of cavities, and a bonding layer on a surface of the ESC chuck wafer. The bonding layer is configured to receive a through-silicon-via (TSV) interposer with solder bumps. The plurality of cavities are configured to receive the solder bumps at the TSV interposer. The bonding layer is configured to receive an electrostatic bias for bonding the ESC chuck wafer to the TSV interposer with the solder bumps.

Abstract: A carrier-free semiconductor package includes a circuit structure having an insulating layer and a circuit layer embedded in the insulating layer and having a plurality of conductive traces and RF (radio frequency) traces, a chip disposed on a first surface of the insulating layer and electrically connected to the conductive traces, an encapsulant covering the chip and the circuit layer, a ground layer formed on a second surface of the insulating layer opposite to the first surface, and a plurality of solder balls disposed on the conductive traces or terminals on the conductive traces, wherein portions of the solder balls electrically connect the ground layer so as to allow the RF traces and the ground layer to form a microstrip line having an RF function, thus obtaining a single-layer carrier-free semiconductor package having low cost and simplified RF design.

Abstract: Certain embodiments pertain to local interconnects formed by subtractive patterning of blanket layer of tungsten or other conductive material. The grain sizes of tungsten or other deposited metal can be grown to relatively large dimensions, which results in increased electrical conductivity due to, e.g., reduced electron scattering at grain boundaries as electrons travel from one grain to the next during conduction.

Abstract: An interconnect sensor for detecting delamination due to coefficient of thermal expansion mismatch and/or mechanical stress. The sensor comprises a conductive path that includes a via disposed between two back end of line metal layers separated by a dielectric. The via is coupled between a first probe structure and a second probe structure and mechanically coupled to a stress inducing structure. The via is configured to alter the conductive path in response to mechanical stress caused by the stress inducing structure. The stress inducing structure can be a through silicon via or a solder ball. The dielectric material can be a low-k dielectric material. In another embodiment, a method of forming an interconnect sensor is provided for detecting delamination.

Abstract: A method of fabricating a through silicon via (TSV) structure is provided, in which, a first dielectric layer is formed on the substrate, the first dielectric layer is patterned to have at least one first opening, a via hole is formed in the first dielectric layer and the substrate, a second dielectric layer is conformally formed on the first dielectric layer, the second dielectric layer has at least one second opening corresponding to the at least one first opening, and the second dielectric layer covers a sidewall of the via hole. A conductive material layer is formed to fill the via hole and the second opening. The conductive material layer is planarized to form a TSV within the via hole. A TSV structure is also provided, in which, the second dielectric layer is disposed within the first opening and on the sidewall of the via hole.

Abstract: Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a method of forming a semiconductor construction. Features are formed over a base. Each feature has a first type sidewall and a second type sidewall. The features are spaced from one another by gaps. Some of the gaps are first type gaps between first type sidewalls, and others of the gaps are second type gaps between second type sidewalls. Masking material is formed to selectively fill the first type gaps relative to the second type gaps. Excess masking material is removed to leave a patterned mask. A pattern is transferred from the patterned mask into the base.

Abstract: A semiconductor device has a first layer formed on a substrate. A mask layer is formed and patterned above the first layer. The first layer is etched partially through. A second layer is formed over the first layer. The first and second layers are etched by a non-lithography process.

Abstract: A chip arrangement is provided. The chip arrangement including: a chip including at least one electrically conductive contact; a passivation material formed over the at least one electrically conductive contact; an encapsulation material formed over the passivation material; one or more holes formed through the encapsulation material and the passivation material, wherein the passivation material at least partially surrounds the one or more holes; and electrically conductive material provided within the one or more holes, wherein the electrically conductive material is electrically connected to the at least one electrically conductive contact.

Abstract: A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer.

Abstract: A microelectronic assembly tolerant to misplacement of microelectronic elements therein may include a molded structure containing a plurality of microelectronic elements. Each microelectronic element has elements contacts having first and second dimensions in respective first and second directions that are transverse to each other, where the first dimension is at least twice the second dimension. In addition, the assembly may include a conductive redistribution layer including conductive vias extending through a dielectric layer to the element contacts of the respective microelectronic elements, where the conductive vias have a third dimension in a third direction and a fourth dimension in a fourth direction, and where the fourth direction is transverse to the third and first directions and the fourth dimension is greater than the third dimension.

Abstract: A through silicon via with sidewall roughness and methods of manufacturing the same are disclosed. The method includes forming a via in a substrate and roughening a sidewall of the via by depositing material within the via. The method further includes removing a backside of the substrate to form a through via with a roughened sidewall structure.

Abstract: A semiconductor memory device of the present invention includes a first dielectric layer located on an upper surface of a semiconductor substrate including contact area and a non-contact area, an etching stop layer pattern formed to expose the first dielectric layer in the non-contact area and cover the first dielectric layer in the contact area, a contact hole extended to the semiconductor substrate of the contact area through the etching stop layer pattern and the first dielectric layer, a contact plug located in the contact hole, and a conductive line connected to the contact plug.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a bottom integrated circuit having bottom through silicon vias with a bottom via pitch; mounting outer interconnects over the bottom integrated circuit; and mounting a top integrated circuit between the outer interconnects, the top integrated circuit having top through silicon vias with a top via pitch less than the bottom via pitch.

Abstract: A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches. The method allows the formation of an extremely low-k dielectric layer for the second level of the dual damascene structure while avoiding damage to that layer by such processes as trench etching and trench metal deposition. The method has the additional advantage of avoiding an etch stop layer between the via level dielectric and the trench level dielectric.

Abstract: A semiconductor device includes: a semiconductor substrate, first and second internal electrodes provided on a surface of the semiconductor substrate; a first through electrode which penetrates through the semiconductor substrate in a thickness direction and is electrically connected to the first internal electrode; and a second through electrode connected to the second internal electrode, and the second internal electrode is thinner than the first internal electrode. The second through electrode may penetrate through the second internal electrode.

Abstract: A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

Abstract: The present invention provides a semiconductor structure having a lateral TSV and a manufacturing method thereof. The semiconductor structure includes a chip having an active side, a back side disposed opposite to the active side, and a lateral side disposed between the active side and the back side. The chip further includes a contact pad, a lateral TSV and a patterned conductive layer. The contact pad is disposed on the active side. The lateral TSV is disposed on the lateral side. The patterned conductive layer is disposed on the active side and is electrically connected to the lateral TSV and the contact pad.

Abstract: Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.

Abstract: A semiconductor device includes a semiconductor substrate, first and second penetration electrodes each penetrating the semiconductor substrate, a multi-level wiring structure formed on the semiconductor substrate, the multi-level wiring structure including a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring, a first wiring pad formed as the lower-level wiring and electrically connected to the first penetration electrode, a second wiring pad formed as the upper-level wiring, a plurality of first through electrodes each formed in the interlayer insulating film to form an electrical connection between the first and second wiring pads, a third wiring pad formed as the lower-level wiring and electrically connected to the second penetration electrode, a fourth wiring pad formed as the upper-level wiring, and a plurality of second through electrodes each formed in the interlayer insulating film.

Abstract: A semiconductor includes a plurality of active regions that are separated from each other on a substrate by a device isolation layer and extend in a first direction, the active regions having two opposite ends and a center region; wordlines that are buried in and cross the active regions and extend in a second direction, which is different from the first direction, wherein a wordline that crosses an active region crosses between one of the two opposite ends and the center region of the active region; first contact plugs on the two opposite ends of the active regions, each contact plug overlapping a border between the active region and the device isolation layer; and second contact plugs formed on the first contact plugs.

Abstract: The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.

Abstract: A semiconductor memory device includes: a first n-type transistor; a first p-type transistor; a first wiring layer having a first interconnecting portion for connecting a drain of the first n-type transistor and a drain of the first p-type transistor; and a second wiring layer having a first conductive portion electrically connected to the first interconnecting portion.

Abstract: A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the first conductor pattern.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of bit line structures over a substrate, forming multiple layers of spacer layers with a capping layer interposed therebetween over the bit line structures, exposing a surface of the substrate by selectively etching the spacer layers, forming air gaps and capping spacers for covering upper portions of the air gaps by selectively etching the capping layer, and forming storage node contact plugs between the bit line structures.

Abstract: Methods and apparatus are disclosed for the back end of line process for fabrication of integrated circuits (ICs). The inter-metal dielectric (IMD) layer between two metal layers may comprise an etching stop layer over a metal layer, a low-k dielectric layer over the etching stop layer, a dielectric hard mask layer over the low-k dielectric layer, an nitrogen free anti-reflection layer (NFARL) over the dielectric hard mask layer, and a metal-hard-mask (MHM) layer of a thickness in a range from about 180 ? to about 360 ? over the NFARL. The MHM layer thickness is optimized at the range from about 180 ? to about 360 ? to reduce the Cu pits while avoiding the photo overlay shifting issue.

Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.

Abstract: A method for forming a semiconductor device includes forming a sealing insulation film over a semiconductor substrate including a device isolation film and an active region, forming a bit line contact plug that protrudes from an upper part of the sealing insulation film and is coupled to the active region, forming a spacer over a sidewall of the protruded bit line contact plug, and forming a bit line coupled to an upper part of the bit line contact plug.

Abstract: A semiconductor device includes a substrate having a top surface. A semiconductor circuit defines a circuit area on the top surface of the substrate. An interconnect is spaced apart from the circuit area and extends from the top surface into the substrate. The interconnect includes a sidewall formed of an electrically insulating material. An opening is provided in the sidewall.

Abstract: A heterogeneous stack structure is provided which includes one or more optical signal-based chips and multiple electrical signal-based chips. The optical chip(s) and the electrical chip(s) are different layers of the stack structure, and the optical chip(s) includes optical signal paths extending at least partially laterally within the optical chip(s). Electrical signal paths are provided extending between and coupling the optical chip(s) and the electrical chips. The electrical signal paths include one or more through substrate vias (TSVs) through one or more electrical chips of the multiple electrical chips in the stack structure. In one embodiment, the optical chip(s) is configured laterally to locally distribute, via one or more paths of the electrical signal paths, a timing reference signal for one or more electrical chips in the stack. Conversion between optical and electrical signals within the stack structure occurs within the optical chip(s).

Abstract: A semiconductor device includes a substrate, a conductive material, and a material layer. The substrate includes a through hole. The conductive material fills the through hole. The material layer is formed in the conductive material, wherein an electrical resistance of the conductive material is lower than an electrical resistance of the material layer.

Abstract: A method of forming a through-substrate via includes forming a through-substrate via opening at least partially through a substrate from one of opposing sides of the substrate. A first material is deposited to line and narrow the through-substrate via opening. The first material is etched to widen at least an elevationally outermost portion of the narrowed through-substrate via opening on the one side. After the etching, a conductive second material is deposited to fill the widened through-substrate via opening. Additional implementations are disclosed. Integrated circuit substrates are disclosed independent of method of manufacture.

Abstract: An integrated circuit package having a multilayer interposer has one or more metal wiring beads provided in the interposer, each of the one or more metal wiring beads has a convoluted wiring pattern that is formed in one of the multiple layers of wiring structures in the interposer, and two terminal end segments connected to the power lines in the integrated circuit package, wherein the one or more metal wiring beads operate as power noise filters.

Abstract: Three dimensional integrated circuit (3DIC) structures and hybrid bonding methods for semiconductor wafers are disclosed. A 3DIC structure includes a first semiconductor device having first conductive pads disposed within a first insulating material on a top surface thereof, the first conductive pads having a first recess on a top surface thereof. The 3DIC structure includes a second semiconductor device having second conductive pads disposed within a second insulating material on a top surface thereof coupled to the first semiconductor device, the second conductive pads having a second recess on a top surface thereof. A sealing layer is disposed between the first conductive pads and the second conductive pads in the first recess and the second recess. The sealing layer bonds the first conductive pads to the second conductive pads. The first insulating material is bonded to the second insulating material.

Abstract: An element to interconnect at least two conductors of a microelectronic circuit is disclosed that includes an initial conductor, referred to as lower conductor; a dielectric layer situated on the initial conductor; a second conductor, referred to as upper conductor, on the dielectric layer; a cavity in the dielectric layer emerging, on the one hand, on the lower conductor and, on the other hand, on the upper conductor. The upper conductor forms a bridge above the lower conductor and the cavity forms, at a level where it emerges on the upper conductor, two vents on both sides of the latter.

Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.

Abstract: A semiconductor device having a via chain circuit including a plurality of fine interconnections and an extension interconnection wider than the fine interconnections, having a first end connected to one or more of the fine interconnections and a second end located in an area of the semiconductor device external to the via chain circuit. One or more of the fine interconnections becomes wider gradually towards the connection to the extension interconnection. The extension interconnection is formed in a same layer as the one or more of the fine interconnections connected to the extension interconnection. The one or more of the fine interconnections connected to the extension interconnection is connected to the extension interconnections at a position where the fine interconnections become wider.

Abstract: A semiconductor device includes a first interconnection including a first end, a second interconnection connected to the first interconnection and including a width being gradually wider towards the first end, a third interconnection and a fourth interconnection, the third interconnection and the fourth interconnection being arranged to sandwich the second interconnection. The first interconnection, the second interconnection, the third interconnection, and the fourth interconnection are each formed in a same layer and a width of the first interconnection is wider than a width of the second interconnection.

Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.

Abstract: A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are uncovered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer.

Abstract: A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.

Abstract: Some embodiments include semiconductor constructions. The constructions have an electrically conductive post extending through a semiconductor die. The post has an upper surface above a backside surface of the die, and has a sidewall surface extending between the backside surface and the upper surface. A photosensitive material is over the backside surface and along the sidewall surface. Electrically conductive material is directly against the upper surface of the post. The electrically conductive material is configured as a cap over the post. The cap has an edge that extends laterally outwardly beyond the post and encircles the post. An entirety of the edge is directly over the photosensitive material.

Abstract: After formation of line openings in a hard mask layer, hard mask level spacers are formed on sidewalls of the hard mask layer. A photoresist is applied and patterned to form a via pattern including a via opening. The overlay tolerance for printing the via pattern is increased by the lateral thickness of the hard mask level spacers. A portion of a dielectric material layer is patterned to form a via cavity pattern by an etch that employs the hard mask layer and the hard mask level spacers as etch masks. The hard mask level spacers are subsequently removed, and the pattern of the line is subsequently transferred into an upper portion of the dielectric material layer, while the via cavity pattern is transferred to a lower portion of the dielectric material layer.