Abstract: According to one aspect, a semiconductor device includes: a buffer layer disposed on a front surface of a second semiconductor layer, and having at least one opening in plan view; and an electrode disposed over the second semiconductor layer and the buffer layer, and being in contact with the second semiconductor layer through the at least one opening, wherein the buffer layer has a higher Vickers hardness than the electrode, and a width w of each of the at least one opening satisfies w<Wth, where s is a thickness of the buffer layer, t is a thickness of the electrode, and Wth=2×(s×t?s2)0.5 holds true.

Abstract: In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface (lower surface) of a wiring board. A solder resist film (insulating layer) covering the lower surface of the wiring board has apertures formed such that multiple portions of the conductor pattern are exposed. The conductor pattern has conductor apertures. The outlines of the apertures and the conductor apertures overlap with each other, in a plan view, respectively.

Abstract: A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit.

Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.

Abstract: A semiconductor device includes an active layer, at least one source electrode, at least one drain electrode, at least one gate electrode, a first insulating layer, a first source pad, a first drain pad, at least one source plug, and at least one drain plug. The source electrode and the drain electrode are both disposed on the active layer. Projections of the source electrode and the drain electrode on the active layer form a source region and a drain region, respectively. The first source pad and the first drain pad are both disposed on the first insulating layer. A projection of the first source pad on the active layer forms a source pad region. An area of an overlapping region between the source pad region and the drain region is smaller than or equal to 40% of an area of the drain region.

Abstract: A semiconductor device includes a substrate having external connection terminals, and a semiconductor chip mounted over a semiconductor-chip mounting portion of the substrate. The external connection terminals are formed by sequentially forming an electroless nickel plating layer, an electroless gold plating layer, and an electrolytic gold plating layer on a terminal portion formed on a surface of the substrate.

Abstract: A light emitting device module is provided comprising a light emitting device package and a board including first and second dummy pads and an electrode pad arranged between the first and second dummy pads, on which the light emitting device package is disposed, wherein at least one of the first and second dummy pads has a dummy hole, and wherein the electrode pad adjacent to at least one of the first and second dummy pads has an electrode hole.

Abstract: Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond fingers may be connected together via one or more electrically conductive interconnects.

Abstract: A semiconductor device includes a semiconductor element having a main surface where an outside connection terminal pad is provided. The semiconductor element is connected to a conductive layer on a supporting board via a plurality of convex-shaped outside connection terminals provided on the outside connection terminal pad and a connection member; and the connection member commonly covers the convex-shaped outside connection terminals.

Abstract: A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

Abstract: A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.

Abstract: An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.

Abstract: Provided is an organic light-emitting display device. The organic light-emitting display device includes: a substrate; a buffer layer formed on the substrate; a gate insulating layer formed on the buffer layer; a conductive layer formed on the gate insulating layer; and a pixel defined layer exposing a portion of the conductive layer to form a pad portion connected to bumps of a drive integrated circuit (IC) chip, wherein protrusions and recesses are formed on a surface of the conductive layer.

Abstract: A semiconductor package includes a plurality of electrical connectors, a semiconductor die having core logic, at least two pairs of core logic input-power and output-power pads, and a plurality of input/output signal pads that carry signals to and from the core logic. Each pad of the semiconductor die has an electrical connector of the plurality of electrical connectors extending therefrom. The semiconductor package also includes a package substrate having at least two pairs of input-power and output-power contact pads, a plurality of input/output signal contact pads, a first metal redistribution layer, and a second metal redistribution layer. The first metal redistribution layer provides a first electrical potential to each of the input-power contact pads, and the second metal redistribution layer provides a second electrical potential to each of the output-power contact pads. Each contact pad has an electrical connector of the plurality of electrical connectors extending therefrom.

Abstract: A structure of a semiconductor chip package is provided. The semiconductor chip package includes: a substrate; a semiconductor chip mounted on a first surface of the substrate; a plurality of electrode pads on a second surface, different from the first surface, of the substrate; and an electrostatic discharge protection pad overlapping a portion of a first electrode pad and a portion of a second electrode pad among the plurality of electrode pads.

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning.

Abstract: A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

Abstract: A semiconductor package may include a substrate including a substrate pad on a top surface thereof; at least one semiconductor chip including a connection terminal electrically connected to the substrate on an active surface thereof, and mounted on the substrate; a heat release pattern formed between the substrate and the at least one semiconductor chip and configured to generate heat; and underfill resin underfilled between the substrate and the at least one semiconductor chip and comprising fillers. A semiconductor package may include a substrate including a substrate pad on a top surface thereof and a first heat release pattern configured to generate heat, and a semiconductor chip including a bonding pad formed on an active surface facing the substrate and a second heat release pattern configured to generate heat.

Abstract: A semiconductor wafer has a first conductive layer formed over its active surface. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A UBM layer is formed around a bump formation area over the second conductive layer. The UBM layer can be two stacked metal layers or three stacked metal layers. The second conductive layer is exposed in the bump formation area. A second insulating layer is formed over the UBM layer and second conductive layer. A portion of the second insulating layer is removed over the bump formation area and a portion of the UBM layer. A bump is formed over the second conductive layer in the bump formation area. The bump contacts the UBM layer to seal a contact interface between the bump and second conductive layer.

Abstract: A semiconductor device includes at least a die carried by a substrate, a plurality of bond pads disposed on the die, a plurality of conductive components, and a plurality of bond wires respectively connected between the plurality of bond pads and the plurality of conductive components. The plurality of bond pads respectively correspond to a plurality of signals, and include a first bond pad configured for transmitting/receiving a first signal and a second bond pad configured for transmitting/receiving a second signal. The plurality of conductive components include a first conductive component and a second conductive component. The first conductive component is bond-wired to the first bond pad, and the second conductive component is bond-wired to the second bond pad. The first conductive component and the second conductive component are separated by at least a third conductive component of the plurality of conductive components, and the first signal is asserted when the second signal is asserted.

Abstract: A semiconductor device including a driving region and a dummy region disposed at both side of the driving region includes a semiconductor substrate having a plurality of active regions spaced from each by equal distances in the driving region, a dummy active region in the dummy region, and a guard ring region surrounding the active regions and the dummy active regions. The distance between the dummy active region and the active region nearest to the dummy active region is substantially the same as each distance between adjacent ones of the active regions, and is smaller than the distance between the dummy active region and a portion of the guard ring region nearest to the dummy active region.

Abstract: The invention provides a semiconductor chip structure having at least one aluminum pad structure and a polyimide buffering layer under the aluminum pad structure, wherein the polyimide buffering layer is self-aligned to the aluminum pad structure, and a method of forming the same. The method includes forming a polyimide buffering layer on a substrate, forming an aluminum pad structure on the buffering layer, and, using the aluminum pad structure as a mask, etching the substrate to remove the polyimide buffering layer from the substrate everywhere except under the aluminum pad structure.

Abstract: Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond fingers may be connected together via one or more electrically conductive interconnects.

Abstract: An exemplary embodiment of the present invention discloses a light emitting diode including a lower contact layer having a first edge, a second edge opposite to the first edge, a third edge connecting the first edge to the second edge, and a fourth edge opposite to the third edge, a mesa structure arranged on the lower contact layer, the mesa structure including an active layer and an upper contact layer, a first electrode pad arranged on the lower contact layer, a second electrode pad arranged on the mesa structure, a first lower extension and a second lower extension extending from the first electrode pad towards the second edge, distal ends of the first lower extension and the second lower extension being farther away from each other than front ends thereof contacting the first electrode pad, and a first upper extension, a second upper extension, and a third upper extension extending from the second electrode pad.

Abstract: A semiconductor package including a conductive clip preferably in the shape of a can, a semiconductor die, and a conductive stack interposed between the die and the interior of the can which includes a conductive platform and a conductive adhesive body.

Abstract: In a semiconductor integrated circuit device, arrangement relationship of power source area I/O pads differs between a peripheral portion and a center portion of a gate region of a chip. That is, in two columns and two rows of the peripheral portion of the gate region, VDD area I/O pads connected to a high-voltage power source VDD and GND area I/O pads connected to a ground power source GND are alternately aligned and arranged both in a row direction and in a column direction. Moreover, in the center portion of the gate region, the same VDD area I/O pads or the same GND area I/O pads are successively aligned in the row direction, and the VDD area I/O pads and the GND area I/O pads are alternately aligned and arranged in the column direction.

Abstract: The present invention provides a semiconductor light-emitting element comprising an electrode part excellent in ohmic contact and capable of emitting light from the whole surface. An electrode layer placed on the light-extraction side comprises a metal part and plural openings. The metal part is so continuous that any pair of point-positions in the part is continuously connected without breaks, and the metal part in 95% or more of the whole area continues linearly without breaks by the openings in a straight distance of not more than ? of the wavelength of light emitted from an active layer. The average opening diameter is of 10 nm to ? of the wavelength of emitted light. The electrode layer has a thickness of 10 nm to 200 nm, and is in good ohmic contact with a semiconductor layer.

Abstract: An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.

Abstract: Provided is a wiring board wherein a circuit is not short-circuited when a IC chip is mounted on the wiring board. A wiring board (2) is provided with a substrate (4); wiring layers (5-8), which are formed on a surface of the substrate (4) and have prescribed wiring patterns; connecting terminals (9-12), which are formed on a part of the wiring layers (5-8) and electrically connected with bumps (18-21) of an integrated circuit chip (IC chip) (3); a mounting region (14), which is arranged on the surface of the substrate (4) and has the integrated circuit chip (3) mounted therein; and an insulating layer (13), which is formed on the surface of the substrate (4) so as to surround the circumference of the mounting region (14) for protecting wiring layers (5-8). A part of the insulating layer (3) is arranged inside the mounting region (14), and the thickness of the insulating layer (13) is more than that of the bumps (18-21) of the integrated circuit chip (3).

Abstract: Provided is a pad layout structure of a semiconductor chip capable of preventing lead-broken problems when packaging the semiconductor chip with a high aspect ratio in a tape carrier package (TCP). In the pad layout structure of the semiconductor chip, a plurality pads are arranged along upper, lower, left and right sides of the semiconductor chip with a high aspect ratio, and a longitudinal width of pads arranged at the left and right sides and a transverse width of pads arranged at both edges of the upper and lower sides are greater than a transverse width of pads arranged at centers of the upper and lower sides.

Abstract: A package substrate includes a core board having a through hole; a circuit layer formed on the core board; a metallic ring disposed on the core board surrounding a contour of the through hole, the metallic ring having opening portions positioned opposite to each other, making the metallic ring having a disconnected manner; and an embedded component installed in the through hole. When the embedded component is deviated in the through hole to allow the electrodes to be in contact with the metallic ring, the electrodes are prevented from coming into contact with the same section of the metallic ring to thereby avoid short circuit.

Abstract: Provided is a stacked package of a semiconductor device and a method of manufacturing the same. The stacked package of a semiconductor device may include at least one first semiconductor chip, at least one second semiconductor chip, at least one interposer between the at least one first semiconductor chip and the at least one second semiconductor chip, and a third semiconductor chip on the at least one first semiconductor chip. The at least one first semiconductor chip and the at least one second semiconductor chip may be configured to perform a first function and a second function and each may include a plurality of bonding pads. The third semiconductor chip may be configured to perform a third function which is different from the first and the second functions. The package may further include external connection leads may be configured to electrically connect the third semiconductor chip to the outside.

Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. Wettable contact pads can be formed over the carrier. A second semiconductor die is mounted over the first semiconductor die. The second die is laterally offset with respect to the first die. An electrical interconnect is formed between an overlapping portion of the first die and second die. A plurality of first conductive pillars is disposed over the first die. A plurality of second conductive pillars is disposed over the second die. An encapsulant is deposited over the first and second die and first and second conductive pillars. A first interconnect structure is formed over the encapsulant, first conductive pillars, and second die. The carrier is removed. A second interconnect structure is formed over the encapsulant, second conductive pillars, and first die. A third conductive pillar is formed between the first and second build-up interconnect structures.

Abstract: A semiconductor chip is provided comprising a semiconductor substrate on which an integrated circuit is formed. The semiconductor chip, which is provided on the semiconductor substrate in an area array, further comprises a plurality of electrodes electrically coupled with the inside of the semiconductor substrate, wherein the electrodes are arranged into a plurality of first groups respectively lined along a plurality of paralleling first straight lines and, further, into a plurality of second groups respectively lined along a plurality of second straight lines which extend so as to intersect with the first straight lines.

Abstract: A method of fabricating a semiconductor device, including forming a circuit block in a peripheral edge portion of a semiconductor chip, forming a circuit block pad on the circuit block to provide an electrical interface for the circuit block, and forming a bonding pad laterally offset from the circuit block and the circuit block pad, the bonding pad being electrically connected to the circuit block pad and providing a bonding wire pad for the circuit block.

Abstract: A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit device to the substrate; forming a stud interconnect having stacked studs, the stud interconnect on the substrate and having a contact surface and a crown surface on an end of the stud interconnect opposite the substrate; applying an encapsulation over the integrated circuit die, over the stud interconnect, and over the substrate; and forming a cavity in the encapsulation over the stud interconnect, the contact surface and the crown surface exposed in the cavity.

Abstract: A method of making a semiconductor structure includes patterning a barrier layer metallurgy (BLM) which forms an undercut beneath a solder material, and forming a repair material in the undercut and on the solder material. The method also includes removing the repair material from the solder material, and reflowing the solder material.

Abstract: A semiconductor device and a fabricating method thereof are provided. In one exemplary embodiment, a plurality of semiconductor dies are mounted on a laminating member, for example, a copper clad lamination, having previously formed conductive patterns, followed by performing operations of encapsulating, forming conductive vias, forming a solder resist and sawing, thereby fabricating a chip size package in a simplified manner. Fiducial patterns are further formed on the laminating member, thereby accurately positioning the semiconductor dies at preset positions of the laminating member.

Abstract: An integrated circuit package system includes: providing a base package of an elongated rectangular-box shape containing first electrical circuitry and including: forming a rectangular contact strip on and adjacent to a first end of the base package; and forming a base contact pad on and adjacent to a second end of the base package for connection to an electrical interconnect.

Abstract: A structure for measuring misalignment of patterns may include a first wiring and a second wiring. The first wiring may include a first lower pattern and a first upper pattern. The first upper pattern may extend in a y-direction, and a first end portion of the first upper pattern that is relatively further toward (proximal to) a negative y-direction may contact the first lower pattern. The second wiring may include a second lower pattern and a second upper pattern. The second upper pattern may extend in the y-direction, a second end portion of the second upper pattern that is relatively further toward (proximal to) a positive y-direction may contact the second lower pattern. The second wiring may be spaced apart from the first wiring along the negative y-direction.

Abstract: A semiconductor device includes a semiconductor substrate formed from compound semiconductor material and multiple conductive connecting pads. The connecting pads are symmetrically arranged on a first surface of the semiconductor substrate in an interweaving pattern. Each cleavage plane extending across the first surface of the semiconductor substrate intersects a portion of at least one connecting pad of the plurality of connecting pads.

Abstract: A semiconductor device includes a circuit block formed in a peripheral edge portion of a semiconductor chip, a circuit block pad formed on the circuit block providing an electrical connection for said circuit block, and a bonding pad laterally offset from the circuit block and the circuit block pad, the bonding pad being electrically connected to the circuit block pad and electrically connected to a lead frame by a bonding wire, the laterally offset bonding pad thereby functioning as a substitute wire bonding pad for the circuit block.

Abstract: Provided is a pad layout structure of a semiconductor chip capable of preventing lead-broken problems when packaging the semiconductor chip with a high aspect ratio in a tape carrier package (TCP). In the pad layout structure of the semiconductor chip, a plurality pads are arranged along upper, lower, left and right sides of the semiconductor chip with a high aspect ratio, and a longitudinal width of pads arranged at the left and right sides and a transverse width of pads arranged at both edges of the upper and lower sides are greater than a transverse width of pads arranged at centers of the upper and lower sides.

Abstract: A circuit substrate and the method for fabricating a packaging of the circuit substrate are provided. A plurality of electrodes are formed on the surface of the circuit substrate, the electrodes are formed with fork structures over an connection section of the circuit substrate, so that when the circuit substrate expands/contracts due to thermal processes, the probability of alignment with electrodes of an external circuit board is increased by easily detaching the fork structure overlapping an electrode of the external circuit board which is not corresponding to the fork structure of the electrode of the circuit substrate, so as to avoid short circuit. Thus, electrode misalignment due to electrode pitch variation of the traditional circuit substrate as a result of thermal deformation can be effectively eliminated.

Abstract: The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason.

Abstract: Electronic device contact structures are disclosed.

Abstract: It is described a bond pad structure and a method for producing the same, the bond pad structure (1), comprising: a substrate (3) having a surface (17) to be electrically contacted; a first isolator layer (5) contacting the surface (17) of the substrate in a first region (a); a first metal layer (9) contacting the surface (17) of the substrate (3) in a second region (b) adjacent the first region (a) and partly overlapping the first isolator layer (5); a second isolator layer (11) at least partly overlapping the first isolator layer (5) and the first metal layer (9); a second metal layer (13) at least partly overlapping the second isolator layer (11) in the second region (b); wherein a maximum thickness (U) of the second metal layer (13) perpendicular to the surface (17) of the substrate (3) is smaller than a maximum thickness (t0) of the first isolator layer (5) perpendicular to the surface (17) of the substrate (3).

Abstract: A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.

Abstract: In a substrate for a stacking-type semiconductor device including a connection terminal provided for a connection with a semiconductor chip to be stacked and an external terminal connected to the connection terminal through a conductor provided in a substrate, connection terminals of a power supply, a ground and the like, which terminals have an identical node, are electrically continuous with each other. Thus, it is possible to facilitate an inspection of electrical continuity between each connection terminal and an external terminal corresponding to each connection terminal by minimum addition of inspecting terminals. Further, it is possible to improve reliability of a stacking-type semiconductor module.