Abstract: When a thin semiconductor device is formed by grinding a wafer, it has been necessary to dice the wafer into dies and process the back surfaces of the dies separately. In the invention, a wafer 2a is half-diced from the front surface thereof to form groove portions 4 therein, and in this state, the front surface of the wafer 2a is attached to a supporting body 5 having rigidity with an adhesive layer 6. Then, the wafer 2a is ground from the back surface and diced into individual dies 2b, and then a back surface process including a heat treatment such as the formation of back surface electrodes 9a is performed in the state where the dies 2b are attached to the supporting body 5.

Abstract: Disclosed are various embodiments of systems, devices and methods for forming an hermetic seal between a lid and a submount for an electronics module or package. At least one thieving pad is connected to a metallized ring formed about or near the circumference of an upper surface of the submount. A corresponding metallized ring is disposed about the lower perimeter of the lid. Solder paste is placed between the two metallized rings and melted, preferably under a reducing atmosphere. Excess molten solder controllably flows towards the at least one thieving pattern while the lid is being hermetically sealed and soldered, avoiding the formation of undesired wayward solder balls inside the package.

Abstract: The present invention provides a semiconductor device exhibiting an improved reliability. A semiconductor device comprises a semiconductor chip having an electrode on a surface thereof and a mounting substrate, and the electrode (aluminum electrode) of the semiconductor chip is coupled to the mounting substrate through a bump (solder bump 104). A plurality of diffusion barrier films (UBM 112) for preventing a diffusion of a material composing the bump is provided between the electrode and the bump, and the diffusion barrier film is formed to have a plurality of divided portions via spacings therebetween.

Abstract: An interposer may include a base substrate supporting an array of conductive lands. The conductive land may have an identical shape and size. The conductive lands may be provided at regular intervals on the base substrate. The conductive land pitch may be determined such that adjacent conductive lands may be electrically connected by one end of an electric connection member. Alternatively, each conductive land may provide respective bonding locations to which ends of two different electric connection members may be bonded. A stacked chip package may include an interposer that may be fabricated by cutting an interposer to size. In the stacked chip package, electrical connections may be made through the interposer between an upper semiconductor chip and a package substrate, between the upper semiconductor chip and a lower semiconductor chip, and/or between the lower semiconductor chip and the package substrate.

Abstract: An IC package method capable of decreasing IR drop of a chip and associated IC apparatus is provided. The IC package method comprises forming a lead frame including a die paddle and a plurality of fingers; installing a die on the die paddle, and coupling a plurality of signal terminals of the die to the fingers; forming a power transferring unit coupled to a power supply; coupling power reception terminals of a plurality of logic units in the die to the power transferring unit; and forming a housing for encapsulating the die, the lead frame and the power transferring unit.

Abstract: Methods of forming a solder structure may include providing a wafer including a plurality of die therein, and a solder wettable pad may be formed on one of the die adjacent an edge of the die. The solder wettable pad may have a length parallel to the edge of the die and a width perpendicular to the edge of the die wherein the length parallel to the edge of the die is greater than the width perpendicular to the edge of the die. A solder bump may be plated on the solder wettable pad, and the die may be separated from the wafer along the edge of the die after plating the solder bump on the solder wettable pad. Moreover, the solder bump may be reflowed on the solder wettable pad so that the solder structure extends laterally from the solder wettable pad beyond the edge of the die after separating the die from the wafer. Related structures are also discussed.

Abstract: An integrated circuit package system includes providing a substrate having a bond finger thereon and forming a pedestal on a portion of the bond finger. A first die is mounted on the substrate and adjacent to the bond finger. A portion of the first die, a portion of the bond finger, and a portion of the pedestal are embedded in an resin layer with an exposed portion of the pedestal protruding from the resin layer. A second die is mounted on the first die and electrically coupled to the exposed portion of the pedestal.

Abstract: Bond pads for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.

Abstract: A method of fabricating a bonding pad anchoring structure comprising the following steps. Providing a substrate. Forming a series of grated metal layers over the substrate separated by an interleaving series of via plug layers having via plugs electrically connecting respective at least a portion of adjacent grated metal layers. The series of grated metal layers having an uppermost grated metal layer. Forming an uppermost via plug layer over the uppermost grated metal layer. The uppermost via plug layer having via plugs. Forming a bonding pad layer over the uppermost via plug layer so that the uppermost via plugs within the uppermost via plug layer electrically connect the bonding pad layer to at least a portion of the uppermost grated metal layer whereby the bonding pad layer is securely bonded to the substrate.

Abstract: A substrate includes a substrate; a number of pad redistribution chips stacked on the substrate and on one another after being rotated 90° in a predetermined direction relative to one another, the pad redistribution chips having a number of center pads positioned at the center thereof, a number of (+) edge pads positioned on an end thereof while corresponding to those of the center pads lying in (+) direction from a middle center pad located in the middle of the center pads, a number of (?) edge pads positioned on the other end thereof while corresponding to those of the center pads lying in (?) direction with symmetry to those of the center pads lying in the (+) direction, and a number of traces for electrically connecting the center pads to the corresponding (±) edge pads, respectively; a flexible PCB for electrically connecting the substrate to the pad redistribution chips; and an anisotropic dielectric film for electrically connecting the pad redistribution chips to the flexible PCB and the substrate to t

Abstract: When connecting a semiconductor device such as an IC chip with a circuit board by the flip-chip method, a semiconductor device is provided without forming bumps thereon, which enables highly reliable and low cost connection between the IC chip and circuit board while ensuring suppressing short-circuiting, lowering connection costs, suppressing stress concentrations at the joints and reducing damage of the IC chip or circuit board. The bumpless semiconductor device is provided with electrode pads 2 on the surface thereof and with a passivation film 3 at the periphery of the electrode pads 2, and conductive particles 4 are metallically bonded to the electric pads 2. Composite particles in which a metallic plating layer is formed at the surface of resin particles are employed as the conductive particles 4.

Abstract: A via hole having a fine hole land includes a first conductive layer formed on an inner wall of the via hole, the first conductive layer being in contact with a hole formed in an insulation layer and extendedly projected to the outside and having the same diameter as the hole in the insulation layer; a second conductive layer contacted with the first conductive layer and formed on an inner wall thereof and projected to the outside and having the same height as the first conductive layer; and a circuit line, formed on the insulation layer, to connect the first conductive layer extendedly projected to the outside of hole in the insulation layer, where the second conductive layer has the same height as the first conductive layer and the fine hole land is connected to wire bonding pad or solder ball pad through the circuit line.

Abstract: An aluminum wire is bonded to a silicon electrode by a wedge tool pressing the aluminum wire against the silicon electrode. In this way, a firmly bonded structure is obtained by sequentially stacking aluminum, aluminum oxide, silicon oxide, and silicon.

Abstract: Support structures for semiconductor devices and methods of manufacturing thereof are disclosed. In some embodiments, the support structures include a plurality of support members that is formed in a substantially annular shape beneath a wire bond region. The central region inside the substantially annular shape of the plurality of support members may be used to route functional conductive lines for making electrical contact to active areas of the semiconductor device. Dummy support structures may optionally be formed between the functional conductive lines. The support structures may be formed in one or more conductive line layers and semiconductive material layers of a semiconductor device. In other embodiments, support members are not formed in an annular shape, and are formed in insulating layers that do not comprise low dielectric constant (k) materials.

Abstract: A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insulating layer overlies the first metal layer. A second metal layer overlies the first electrically insulating layer, the second metal layer having a plurality of openings. An interconnect pad that defines an interconnect pad area overlies the second metal layer. At least a certain amount of the openings in the two metal layers are aligned to improve structural strength of the interconnect structure. The amount of alignment may differ depending upon the application and materials used. A bond wire connection or conductive bump may be used with the interconnect structure.

Abstract: The present invention relates to a nickel alloy sputtering target comprising 1 to 30 at % of Cu; 2 to 25 at % of at least one element selected from among V, Cr, Al, Si, Ti and Mo; remnant Ni and unavoidable impurities so as to inhibit the Sn diffusion between a solder bump and a substrate layer or a pad. Provided are a nickel alloy sputtering target and a nickel alloy thin film for forming a barrier layer having excellent wettability with the Pb-free Sn solder or Sn—Pb solder bump, and capable of inhibiting the diffusion of Sn being a soldering component and effectively preventing the reaction with the substrate layer upon forming a Pb-free Sn solder or Sn—Pb solder bump on a substrate such as a semiconductor wafer or electronic circuit or a substrate layer or pad of the wiring or electrode formed thereon.

Abstract: A semiconductor package comprises a substrate that utilizes one or more pins to form external interconnects. The pins are bonded to bonding pads on the substrate by solder. The pins may each has a pin head that may have a bonding surface, wherein the bonding surface may comprises a center portion and a side portion that is tapered away relative to the center portion. In some embodiments, the bonding surface may comprise a round shape. In some embodiments, a gas escape path may be provided by the shape of the bonding surface to increase pin pull strength and/or solder strength. The package may further comprise a surface finish that may comprise a palladium layer with a reduced thickness to reduce the amount of palladium based IMC precipitation into the solder.

Abstract: A bond pad structure of an integrated circuit is provided. The bond pad structure includes a conductive bond pad, a first dielectric layer underlying the bond pad, and an Mtop plate located in the first dielectric layer and underlying the bond pad. The Mtop plate is a solid conductive plate and is electrically coupled to the bond pad. The bond pad structure further includes a first passivation layer over the first dielectric layer wherein the first passivation layer has at least a portion under a middle portion of the bond pad. At least part of an active circuit is located under the bond pad.

Abstract: A semiconductor package board for mounting thereon a semiconductor chip includes a metal base having an opening for receiving therein the semiconductor chip and a multilayer wiring film layered onto the metal base. The semiconductor chip is flip-chip bonded onto the metal pads disposed on the multilayer wiring film within the opening. The surface of the metal base is flush with the top surface of the semiconductor chip received in the opening. The resultant semiconductor device has a larger number of external pins and a smaller deformation without using a stiffener.

Abstract: A pad structure 100 includes an electrode pad (a first electrically conducting film 104 and a second electrically conducting film 110) and an insulating film provided over a peripheral region of the electrode pad so as to surround the electrode pad, and the insulating film has a structure including a protective film (a cover oxide film 106) and a transparent resin film (a transparent resin 108) provided on the cover oxide film 106.

Abstract: A packaging technology for silicon chips is similar to ball grid array packaging technology of the prior art without, however, the use of printed board substrate of the prior art Instead pins are used that are part of a planar frame, the pins folded to a position 90 degrees from the plane of the frame, after which the frame is disposed in contact with the chip, pads on the frame and the chip are connected, and then entire assembly is then encapsulated. The edges of the frame are then cut off, leaving the encapsulation to maintain the configuration of the package in place.

Abstract: An integrated circuit with a monolithic semiconducting substrate formed in a chip, where the chip has a peripheral edge, a backside, and an opposing top on which circuitry is formed. A first ring of bonding pads is formed along at least a portion of the peripheral edge. At least one of the bonding pads is configured as a power pad, and at least one of the bonding pads is configured as a ground pad. An intermediate power bus is disposed interior to the first ring of bonding pads on the chip, and forms no direct electrical connections to any core devices. An intermediate ground bus is also disposed interior to the first ring of bonding pads on the chip, and forms no direct electrical connections to any core devices. A power pad wire forms an exclusive electrical connection between the power pad and the intermediate power bus. A ground pad wire forms an exclusive electrical connection between the ground pad and the intermediate ground bus.

Abstract: A semiconductor device including a semiconductor substrate, a contact pad, a passivation layer, a bump, and a seeding layer is provided. The semiconductor substrate has an active surface. The contact pad is disposed on the active surface. The passivation layer is disposed on the active surface and exposes a central part of the contact pad. The seeding layer is disposed on the exposed central part of the contact pad. The bump has a top surface, a bottom surface opposite to the top surface, and a side surface connecting the top surface and the bottom surface. The bump is disposed on the seeding layer. The bump is placed in contact with the seeding layer by the bottom surface and by part of the side surface.

Abstract: In some embodiments an integrated circuit package includes a coaxial arrangement of one or more ground via surrounding a signal via. The one or more ground via and the signal via extend through the package to allow transmission of signals between an integrated circuit and a board. Other embodiments are described and claimed.

Abstract: An integrated circuit, a circuit system and method of manufacturing such is disclosed. One embodiment provides a circuit chip including a first contact field on a chip surface; and an insulating layer on the chip surface. The insulating layer includes a flexible material. A contact pillar is coupled to the first contact field and extends from the chip surface through the insulating layer. The contact pillar includes a conductive material.

Abstract: The present invention relates to an electronic device incorporating a heat distributor. It applies more particularly to devices of the plastic package type, with one or more levels of components. According to the invention, the electronic device, for example of the package type, is provided for its external connection with pads distributed over a connection surface. It includes a thermally conducting plate lying parallel to said connection surface and having a nonuniform structure making it possible, when the device is exposed to a given external temperature, to supply a controlled amount of heat to each external connection pad according to its position on the connection surface. If the device is a package comprising a support of the printed circuit type, the conducting plate will advantageously form an internal layer of said support.

Abstract: The present invention provides a semiconductor device comprising a semiconductor substrate, and transistors formed on the semiconductor substrate, wherein control electrode terminals constituting external electrode terminals of the transistors, and first electrode terminals which transmit output signals, are provided on a main surface of the semiconductor substrate, wherein the control electrode terminals are provided at least one, and a plurality of the first electrode terminals are arranged on one side and a plurality of the first electrode terminals are arranged on the other side with the control electrode terminals being interposed therebetween, wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on one side of the control electrode terminals constitute a first transistor portion, and wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on the other side of the control electrode

Abstract: The present invention discloses a bonding pad structure disposed in a semiconductor device and a method for forming the bonding pad structure. The semiconductor device includes a substrate. The bonding pad structure includes a connection structure and an induction structure. The connection structure allows for a direct connection with a bonding wire. The induction structure is coupled with the connection structure and lowers an effective capacitance between the bonding wire and the substrate.

Abstract: A display device includes a substrate having plural signal lines connected to switching elements which are formed in an image display region, and plural terminals connected to respective ones of the signal lines. The terminals include a first group arranged at an image display region side and a second group arranged remote from the image display region side, the terminals being connected to output terminals of a driving circuit. The output terminals include a first group arranged at the image display region side and a second group arranged remote from the image display region side. The first group of terminals connect the first group of output terminals, and the second group of terminals connect the second group of output terminals. An area of a respective output terminal of the second group is larger than an area of a respective output terminal of the first group.

Abstract: Consistent with an example embodiment, an electronic device comprises a semiconductor device, particularly an integrated circuit, and a carrier substrate with conductive layers on the first side and the second side, and voltage supply and ground connections mutually arranged according to a chessboard pattern. These connections extend in a direct path through vertical interconnects and bumps to bond pads at the integrated circuit, which bond pads are arranged in a corresponding chessboard pattern. As a result, an array of direct paths is provided, wherein the voltage supply connections form as much as possible the coaxial center conductors of a coaxial structure.

Abstract: A disclosed semiconductor chip includes a first connection pad adapted to input an input signal; and a second connection pad adapted to selectively output, according to a test mode signal input to the semiconductor chip, one of the input signal and an output signal from the semiconductor chip.

Abstract: A semiconductor substrate having a body and a plurality of finger pads formed thereon is disclosed. Each of the finger pads includes two expanding portions respectively and a connecting portion formed therebetween. The finger pads are alternately arranged on the body in a manner that one of the expanding portions of one of the finger pads is disposed in position corresponding to the connecting portion of an adjacent one of the finger pads, so as to reduce pitches between the finger pads horizontally and vertically, provide sufficient spaces for wire bonding, and prevent a wire bonder from mistakenly recognizing a lead trace coupled to the finger pad as another finger pad.

Abstract: A wired circuit board having terminals that can ensure large electrical connection areas while preventing shorting of adjacent terminals, to ensure that the terminals are electrically connected with external terminals through molten metal. An insulating base layer 3 is formed on a supporting board 2 so that insulating concave portions 13 are formed at portions thereof where external connecting terminals 8 are to be formed. A conductive pattern 4 is formed on the insulating base layer 3 so that a number of lines of wire 4a, 4b, 4c, 4d, the magnetic head connecting terminals 7, and the external connecting portions 8 are integrally formed, and conductive concave portions 9 are formed in the external connecting terminals 8. Thereafter, an insulating cover layer 10 is formed on the insulating base layer 3 so that the magnetic head connecting terminals 7 and the external connecting terminals 8 are exposed from the insulating cover layer 10.

Abstract: A sensor package apparatus includes a lead frame substrate that supports one or more electrical components, which are connected to and located on the lead frame substrate. A plurality of wire bonds are also provided, which electrically connect the electrical components to the lead frame substrate, wherein the lead frame substrate is encapsulated by a thermoset plastic to protect the plurality of wire bonds and at least one electrical component, thereby providing a sensor package apparatus comprising the lead frame substrate, the electrical component(s), and the wire bonds, while eliminating a need for a Printed Circuit Board (PCB) or a ceramic substrate in place of the lead frame substrate as a part of the sensor package apparatus. A conductive epoxy can also be provided for maintaining a connection of the electrical component(s) to the lead frame substrate. The electrical components can constitute, for example, an IC chip and/or a sensing element (e.g., a magnetoresistive component) or sense die.

Abstract: A BGA package with encapsulation on substrate bottom comprises a chip, a substrate, a molding compound and a plurality of solder balls. The substrate has a SMT surface placing a plurality of ball pads. The molding compound encapsulates a solder resist layer on the SMT surface of the substrate and has a plurality of through holes exposing the ball pads respectively. The hole diameter of the through holes is greater than that of the openings of the solder resist layer on the substrate to allow the solder balls not to contact the molding compound. The solder balls are disposed in the through holes and are bonded to the exposed ball pads of the substrate thereby enhancing moisture resistance of BGA products and preventing the solder balls from falling because of contact stress of the molding compound.

Abstract: The present invention discloses a dense arrangement in the conductors of a package and the corresponding conductive pads of a circuit board. The conductors and the corresponding conductive pads are separated into at least a first group in a peripheral region of the grid array package, and a second group in another region of the grid array package. Most in the first group of conductive pads are apart at a first pitch, most in the second group of conductive pads are apart at a second pitch which is less than the first pitch. According to the shrinking in the conductive trace on a conductive layer and the shrinking in the through hole, the first pitch and the second pitch are optimized for the maximum conductors and the corresponding conductive pads.

Abstract: AN LED chip package body provides an LED chip with a pad-installed surface, a plurality of pads disposed on the pad-installed surface and a rear surface formed opposite the pad-installed surface. The LED chip package body further has a light-reflecting coating disposed on the pad-installed surface of the LED chip and a plurality of pad-exposed holes for exposure of the corresponding pads of the LED chip. The LED chip package body further comprises a light-transparent element disposed on the rear surface of the LED chip and a plurality of conductive projecting blocks. Each of the conductive projecting blocks is disposed on the corresponding pad of the LED chip.

Abstract: AN LED chip package body provides an LED chip with a pad-installed surface, a plurality of pads disposed on the pad-installed surface and a rear surface formed opposite the pad-installed surface. The LED chip package body further has a light-reflecting coating disposed on the pad-installed surface of the LED chip and a plurality of pad-exposed holes for exposure of the corresponding pads of the LED chip. The LED chip package body further comprises a light-transparent element disposed on the rear surface of the LED chip and a plurality of conductive projecting blocks. Each of the conductive projecting blocks is disposed on the corresponding pad of the LED chip.

Abstract: The invention provides electronic articles and methods of making said articles. The electronic articles comprise an electronic component bonded and electrically connected to a substrate using an underfill adhesive comprising the reaction product of a thermosetting resin, curing catalyst, and surface-treated nanoparticles that are substantially spherical, non-agglomerated, amorphous, and solid.

Abstract: An apparatus and method for incorporating discrete passive components into an integrated circuit package. A metal layer is formed over a surface of a substrate. A layer of photosensitive material is then formed over the metal layer. Using standard photolithographic processing, a pattern is formed with the photosensitive material to expose at least one region of the metal layer. The remaining photosensitive material protects the underlying metal during metal etching. The substrate is then subjected to a metal etching process to remove the metal that is not protected by the photosensitive material. The remaining photosensitive material is then removed from each remaining area of the metal layer. The discrete passive components can then be attached to the formed metal lands.

Abstract: An integrated circuit package system includes providing a substrate having a bond finger thereon and forming a pedestal on a portion of the bond finger. A first die is mounted on the substrate and adjacent to the bond finger. A portion of the first die, a portion of the bond finger, and a portion of the pedestal are embedded in an resin layer with an exposed portion of the pedestal protruding from the resin layer. A second die is mounted on the first die and electrically coupled to the exposed portion of the pedestal.

Abstract: An interlayer insulating film is formed on a semiconductor substrate. An intra-layer insulating film is formed on the interlayer film. A recess is formed through the intra-layer film. The recess has a pad-part and a wiring-part continuous with the pad-part. The pad-part is wider than the width of the wiring-part. Convex regions are left in the pad-part. The convex regions are disposed in such a manner that a recess area ratio in a near wiring area superposed upon an extended area of the wiring-part into the pad-part, within a first frame area having as an outer periphery an outer periphery of the pad-part and having a first width, becomes larger than a recess area ratio in a second frame area having as an outer periphery an inner periphery of the first frame area and having a second width. A conductive film is filled in the recess.

Abstract: An integrated circuit (IC) carrier assembly includes a printed circuit board (PCB). A carrier is soldered to the PCB. The carrier includes a grid of electrical contact islands surrounding a receiving zone for receiving an IC. Pairs of adjacent islands are interconnected by respective resilient suspension means. The IC is received in the receiving zone and is electrically coupled to a number of the plurality of islands adjacent to the receiving zone. The IC is fast to a retainer, and the retainer is fast with the number of the plurality of islands and the IC.

Abstract: A method of modifying a semiconductor device to provide electrical parameter monitoring. The device includes a semiconductor die and a package substrate. The substrate includes a conductive plane. The die is connected to the plane via a plurality of connection structures. The method includes disconnecting a first one of the connection structures from the plane, and connecting the first connection structure to an external package connection, thereby providing a capability to monitor an electrical parameter of the die via the external package connection.

Abstract: The semiconductor module includes a heat spreader and at least two semiconductors coupled thereto. Each of the semiconductors comprises a die containing integrated circuitry and electrical connectors coupled to the die. The module also includes a flexible circuit having opposing first and second sides. The first side of the flexible circuit coupled to the heat spreader, while the second side is coupled to the electrical connectors. The module also includes a termination resistor electrically coupled to the integrated circuitry of at least one of the semiconductors.

Abstract: Consistent with an example embodiment, an electronic device comprises an integrated circuit and a carrier substrate with a bottom and top conductive layer, and is provided with voltage supply, ground and signal transmission connections. In order to enable the use of more than one supply voltage, the integrated circuit is subdivided into core functionality and peripheral functionality, and the carrier substrate is subdivided into a corresponding core area and peripheral area. The ground connections of both core and periphery are mutually coupled through an interconnect in the carrier substrate. This interconnect is particularly a ground plane, and allows the provision of a transmission line character to the interconnects for signal transmission of the periphery.

Abstract: A circuit device is provided in which the bonding reliability of a brazing material such as soft solder is improved. A circuit device of the present invention includes conductive patterns, a bonding material which fixes circuit elements to the conductive patterns, and sealing resin which covers the circuit elements. The circuit device has a structure in which Pb-free solder containing Bi is used as the bonding material. Since the melting temperature of Bi is high in comparison with that of a general solder, the melting of the bonding material is suppressed when the circuit device is mounted. Further, Ag or the like may be mixed into the bonding material in order to enhance the wettability of the bonding material.

Abstract: A mark-shaped pad. A bonding pad structure with at least one mark-shaped bonding pad comprises: a bottom metal layer disposed over the surface of a rectangular semiconductor substrate to connect the circuit electrically, an inter-metal dielectric layer disposed over the bottom metal layer, metal plugs formed in the inter-metal dielectric layer to connect with the bottom metal layer, a top metal layer disposed over the inter-metal dielectric layer connecting with the metal plugs, and a passivation layer disposed over the top metal layer with openings to expose the top metal layer portions as bonding pads, wherein at least one bonding pad is mark-shaped, e.g. “”, “”, “” or “”, to indicate the orientation of the bonding pads on the rectangular semiconductor substrate.

Abstract: A singulation method used in leadless packaging process is disclosed. An array of molded products on an upper surface of a lead frame is utilized in the singulation method. The lead frame has a plurality of dambars between the molded products. The lower surface of the lead frame is attached with a tape. Each of the molded products includes a semiconductor chip encapsulated in a package body and electrically coupled to the upper surface of the lead frame. The singulation method is accomplished by etching the upper surface of the lead frame with the package bodies as mask until each dambar is etched away.

Abstract: An apparatus for transverse characterization of materials includes a lower pattern of contacts, separated by spacings, a material, and an upper pattern of a multiplicity of contacts, separated by spacings differing from the spacings of the lower pattern. The transverse characterization method includes receiving lower pattern of a multiplicity of contacts, separated by spacings along a surface, with a material above the surface, successively placing an upper contact near the upper surface of the material in an upper pattern of locations separated by spacings differing from the spacings of the lower pattern, measuring the characteristics between the upper contact and one or more contacts of the lower pattern and evaluating the measured characteristics to previous measurements, wherein the evaluation provides the transverse characterization.