Bonding Areas, E.g., Pads (epo) Patents (Class 257/E23.02)
  • Patent number: 10269743
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method includes forming a contact pad over a semiconductor device. A passivation material is formed over the contact pad. The passivation material has a thickness and is a type of material such that an electrical connection may be made to the contact pad through the passivation material.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Sung Chang, Nien-Tsung Tsai
  • Patent number: 10128185
    Abstract: In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: November 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Bruce, Gregory M. Fritz, Eric A. Joseph, Hiroyuki Miyazoe
  • Patent number: 10064275
    Abstract: A circuit board includes a substrate and multiple pads. The multiple pads are disposed on the substrate and have respective footprints for connecting one or more electronic components to the circuit board, at least a pad from among the pads includes a linear electrical trace laid out in a two-dimensional (2D) pattern that covers at least a part of a footprint of the pad.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: August 28, 2018
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Haim Peretz, Moshe Shoval
  • Patent number: 10038021
    Abstract: The present technology relates to techniques of preventing intrusion of moisture into a chip. Various illustrative embodiments include image sensors that include: a substrate; a plurality of layers stacked on the substrate; the plurality of layers including a photodiode layer having a plurality of photodiodes formed on a surface of the photodiode layer; the plurality of layers including at least one layer having a groove formed such that a portion of the at least one layer is excavated; and a transparent resin layer formed above the photodiode layer and formed in the groove. The present technology can be applied to, for example, an image sensor.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: July 31, 2018
    Assignee: Sony Corporation
    Inventors: Atsushi Yamamoto, Shinji Miyazawa, Yutaka Ooka, Kensaku Maeda, Yusuke Moriya, Naoki Ogawa, Nobutoshi Fujii, Shunsuke Furuse, Masaya Nagata, Yuichi Yamamoto
  • Patent number: 9953954
    Abstract: A Wafer-level chip scale package (WLCSP) includes a semiconductor structure and a first bonding pad formed over a portion of the semiconductor structure. The WLCSP further includes a passivation layer formed over the semiconductor structure and the first bonding pad, exposing portions of the first bonding pad. The WLCSP further includes a conductive redistribution layer formed over the passivation layer and the portions of the first bonding pad exposed by the passivation layer. The WLCSP further includes a planarization layer formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. The WLCSP further includes an under-bump-metallurgy (UBM) layer formed over the planarization layer and a conductive bump formed over the UBM layer.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: April 24, 2018
    Assignee: MEDIATEK INC.
    Inventors: Yan-Liang Ji, Ming-Jen Hsiung
  • Patent number: 9935052
    Abstract: Circuitry having power lines with comparable path resistances may include input-output blocks in an integrated circuit (IC) that are coupled to respective sets of bumps on the IC. The circuitry may have a core region and a periphery region. Groups of input-output blocks may be formed in the periphery region. A first set of power lines in the circuitry extends from the core region to the first group of input-output blocks whereas a second set of power lines in the circuitry extends from the core region to the second group of input-output blocks. The first and second sets of power lines are physically separate from each other.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: April 3, 2018
    Assignee: Altera Corporation
    Inventors: Hui Liu, Karthik Chandrasekar, Kyung Suk Oh, Kaushik Chanda, Arifur Rahman
  • Patent number: 9922947
    Abstract: Various embodiments provide a bonding pad structure that is capable of handling increased bonding loads. In one embodiment, the bonding pad structure includes a continuous metal layer, a first discontinuous metal layer, a second discontinuous metal layer, and dielectric material. The first discontinuous metal layer and the second discontinuous metal layer each include a plurality of holes that are arranged in a pattern. The plurality of holes of the first discontinuous metal layer overlaps at least two of the plurality of holes of the second discontinuous metal layer. The dielectric material is formed between the metal layers and fills the plurality of holes of the first and second discontinuous metal layers.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: March 20, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Dario Vitello, Federico Frego, Salvatore Latino
  • Patent number: 9859177
    Abstract: Aspects of the present disclosure include methods and test structures for an intermediate metal level of an integrated circuit (IC). A method according to the present disclosure can include: fabricating a first plurality of metal levels including an intermediate metal level of an IC structure, the intermediate metal level being one of a plurality of metal levels in the IC structure other than a capping metal level of the IC structure; performing a first functional test on a first circuit positioned within the intermediate metal level; fabricating a second plurality of metal levels after performing the first functional test, the second plurality of metal levels including the capping metal level of the IC structure; and performing a second functional test on a second circuit positioned within the plurality of metal levels, after the fabricating of the capping metal level.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: January 2, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Janakiraman Viraraghavan, Ramesh Raghavan, Balaji Jayaraman, Thejas Kempanna, Rajesh R. Tummuru, Toshiaki Kirihata
  • Patent number: 9859204
    Abstract: Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: January 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myeong Soon Park, Hyunsoo Chung, Won-young Kim, Ae-nee Jang, Chanho Lee
  • Patent number: 9576867
    Abstract: Device comprising a ductile layer, a method for making a component comprising a ductile layer and a method for testing a component are disclosed. An embodiment includes an electronic device including a first conductive layer, a ductile layer and a brittle layer between the first conductive layer and the ductile layer.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Reinhard Pufall
  • Patent number: 9530690
    Abstract: Various embodiments of mechanisms for forming a slotted metal pad over a TSV in substrate are provided. The dielectric structures in the slotted metal pad reduce dishing effect during planarization of the slotted metal pad. As a result, the risk of having metal stringers in upper metal level(s) caused by the dishing effect is greatly reduced.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chuan Tseng, Chia-Wei Liu, Cindy Kuo, Ren-Wei Xiao
  • Patent number: 9496222
    Abstract: A semiconductor device has a structure including a substrate, a first insulating film formed over a part of a principal plane of the substrate, a conductive portion formed over a surface of the first insulating film, and a second insulating film which covers the principal plane of the substrate, the first insulating film, and the conductive portion and whose moisture resistance is higher than moisture resistance of the first insulating film. The first insulating film is placed between the substrate and the conductive portion to prevent the generation of parasitic capacitance. The first insulating film is covered with the second insulating film whose moisture resistance is higher than the moisture resistance of the first insulating film. The second insulating film prevents the first insulating film from absorbing moisture.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: November 15, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Junichi Kon, Yoshihiro Nakata, Kozo Makiyama
  • Patent number: 9425147
    Abstract: A semiconductor device includes an interlayer insulating film; a wiring formed on the interlayer insulating film so as to protrude there from and made of a material having copper as a main component, the wiring having a thickness direction and having a cross sectional shape of an inverted trapezoid that becomes wider in width with distance away from the interlayer insulating film; and a passivation film formed so as to cover the wiring. The passivation film is made of a laminated film in which a first nitride film, an intermediate film, and a second nitride film are laminated in that order from the wiring side. The intermediate film is made of an insulating material differing from those of the first and second nitride films, and has a tapered portion having a cross sectional shape of a trapezoid that becomes narrower in width with distance away from the interlayer insulating film.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: August 23, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Yuichi Nakao, Tadao Ohta
  • Patent number: 9041181
    Abstract: A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee-chul Lee, Myung-kee Chung, Kun-dae Yeom
  • Patent number: 9041182
    Abstract: A semiconductor package according to embodiments includes: a semiconductor chip including a front electrode on a front surface thereof and a back electrode on a back surface thereof; a front-side cap portion including an air gap in a portion between the semiconductor chip and the front-side cap portion and a front-side penetrating electrode, and is positioned to face the front surface of the semiconductor chip; a back-side cap portion bonded with a first cap portion to hermetically seal the semiconductor chip, includes an air gap at least in a portion between the semiconductor chip and the back-side cap portion and a back-side penetrating electrode, and is positioned to face the back surface of the semiconductor chip; a front-side connecting portion which electrically connects the front electrode and the front-side penetrating electrode; and a back-side connecting portion which electrically connects the back electrode and the back-side penetrating electrode.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshihiko Nagano, Kazuhide Abe, Hiroshi Yamada, Kazuhiko Itaya, Taihei Nakada
  • Patent number: 9006896
    Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure located in the dielectric layer and electrically connected to the device region, wherein the conducting pad structure comprises a stacked structure of a plurality of conducting pad layers; a support layer disposed on a top surface of the conducting pad structure; and a protection layer disposed on the second surface of the semiconductor substrate.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: April 14, 2015
    Assignee: Xintec Inc.
    Inventors: Yu-Lung Huang, Tsang-Yu Liu, Shu-Ming Chang
  • Patent number: 8981581
    Abstract: A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heung-Kyu Kwon, Seong-Ho Shin, Yun-Seok Choi, Yong-Hoon Kim
  • Patent number: 8981580
    Abstract: A bonding pad structure is provided that includes two conductive layers and a connective layer interposing the two conductive layers. The connective layer includes a contiguous, conductive structure. In an embodiment, the contiguous conductive structure is a solid layer of conductive material. In other embodiments, the contiguous conductive structure is a conductive network including, for example, a matrix configuration or a plurality of conductive stripes. At least one dielectric spacer may interpose the conductive network. Conductive plugs may interconnect a bond pad and one of the conductive layers.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Yu-Wen Liu, Hao-Yi Tsai, Hsien-Wei Chen
  • Patent number: 8975116
    Abstract: An electronic unit is produced including at least one electronic component at least partially embedded in an insulating material. A film assembly is provided with at least one conductive layer and a carrier layer. The conductive layer includes openings in the form of holes for receiving bumps, which are connected to contact surfaces of the at least one electronic component. The at least one component is placed on the film assembly such that the bumps engage with the openings of the conductive layer. The at least one component is partially embedded from the side opposite of the bumps into a dielectric layer. The carrier layer of the film assembly is removed such that the surface of the bumps is exposed. A metallization layer is then deposited on the side of the remaining conductive layer having the exposed bumps and so as to produce conductor tracks that overlap with the bumps.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: March 10, 2015
    Assignees: Technische Universität Berlin, Fraunhofer-Gesellschaft zur Foerderung der angewandt Forschung e.V.
    Inventors: Andreas Ostmann, Dionysios Manessis, Lars Böttcher, Stefan Karaszkiewicz
  • Patent number: 8970037
    Abstract: A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, filling the opening on the electrode; and a dome-shaped bump containing Sn and Ti, covering the under bump metal layer, wherein at least part of the under bump metal layer has a portion sandwiched between the external electrode and the insulating covering layer.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: March 3, 2015
    Assignee: TDK Corporation
    Inventors: Kenichi Yoshida, Makoto Orikasa, Hideyuki Seike, Yuhei Horikawa, Hisayuki Abe
  • Patent number: 8970017
    Abstract: An apparatus having a bonding pad and a conductor is disclosed. The bonding pad may be formed in a conductive layer of an integrated circuit. The bonding pad generally has (i) a bond region, (ii) an interface edge sized to match a transmission line and (iii) a tapered region between the bond region and the interface edge. The interface edge may be narrower than the bond region. The tapered region generally has a non-rectangular shape that spans from the bond region to the interface edge. The conductor may be bonded to the bond region. The conductor is generally configured to exchange a signal with the bond region. The signal may be in a microwave frequency range.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: March 3, 2015
    Assignee: M/A-COM Technology Solutions Holdings, Inc.
    Inventors: Jabra Tarazi, Leif Göran Martin Snygg
  • Patent number: 8963331
    Abstract: Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire lateral periphery of the component, and may be spaced from the component by an intervening ring of electrically insulative material. The copper component may be a bond pad or an interconnect between two levels of metal layers. Some embodiments include semiconductor constructions in which nickel extends across a copper component, a copper barrier is laterally offset from the copper component, and an insulative material is between the copper barrier and the copper component.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Tianhong Zhang, Akram Ditali
  • Patent number: 8957493
    Abstract: A semiconductor device includes an active layer, at least one source electrode, at least one drain electrode, at least one gate electrode, a first insulating layer, a first source pad, a first drain pad, at least one source plug, and at least one drain plug. The source electrode and the drain electrode are both disposed on the active layer. Projections of the source electrode and the drain electrode on the active layer form a source region and a drain region, respectively. The first source pad and the first drain pad are both disposed on the first insulating layer. A projection of the first source pad on the active layer forms a source pad region. An area of an overlapping region between the source pad region and the drain region is smaller than or equal to 40% of an area of the drain region.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: February 17, 2015
    Assignee: Delta Electronics, Inc.
    Inventors: Li-Fan Lin, Wen-Chia Liao
  • Patent number: 8952531
    Abstract: A packaging method comprises steps of forming a plurality of pads and another circuit pattern on a substrate, forming a second dry film pattern including opening exposing the pad, mounting a solder coating ball in the opening of the second dry film pattern, performing a reflow process on the solder coating ball in order to allow the solder coating ball to have a modified pattern, delaminating the second dry film pattern, and forming a solder pattern including the modified pattern of the solder coating ball in a solder to mount a chip on the substrate using the solder pattern.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: February 10, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jin Won Choi, Yon Ho You
  • Patent number: 8946886
    Abstract: An electronic component package includes a substrate having a first surface, an electronic component mounted to the substrate, traces on the first surface, a terminal on the first surface, and a solder mask on the first surface. The solder mask includes a solder mask opening exposing the terminal. An electrically conductive coating and/or conductive coating feature is formed on the solder mask and extends into the solder mask opening to contact and be electrically connected to the terminal. The conductive coating may be grounded to shield the electronic component from electromagnetic interference (EMI). Further, the conductive coating provides a ground plane for the traces facilitating impedance matching of signals on the traces. In addition, the conductive coating has a high thermal conductivity thus enhancing heat dissipation from the electronic component.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: February 3, 2015
    Inventors: Ruben Fuentes, August Joseph Miller, Jr.
  • Patent number: 8946770
    Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: February 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
  • Patent number: 8941241
    Abstract: A semiconductor device includes at least 4 conductive line groups arranged in parallel over one memory cell block and each configured to include conductive lines. First contact pads may be coupled to the respective ends of the conductive lines of two of the 4 conductive line groups in a first direction, and second contact pads may be coupled to the respective ends of the conductive lines of the remaining 2 of the 4 conductive line groups in a second direction opposite to the first direction.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: January 27, 2015
    Assignee: SK Hynix Inc.
    Inventor: Dae Sung Eom
  • Patent number: 8928146
    Abstract: A semiconductor chip includes at least one integrated circuit device and a bond pad that is electrically connected to the at least one integrated circuit device. The bond pad has an irregular configuration when viewed from above that corresponds to a first area portion that is defined by a first substantially regular geometric shape when viewed from above and a second area portion adjacent to the first area portion. The second area portion is located at a greater distance from a centerline of the semiconductor chip than any part of the first area portion when viewed from above, and two sides of the first area portion are substantially aligned with and substantially flush with two respective sides of the second area portion.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: January 6, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Vivian W. Ryan
  • Patent number: 8922008
    Abstract: A bump structure includes a first bump and a second bump. The first bump is disposed on a connection pad of a substrate. The first bump includes a lower portion having a first width, a middle portion having a second width smaller than the first width, and an upper portion having a third width greater than the second width. The second bump is disposed on the upper portion of the first bump.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Yun Myung, Yong-Hwan Kwon, Jong-Bo Shim, Moon-Gi Cho
  • Patent number: 8916980
    Abstract: An apparatus includes an image sensor with a frontside and a backside. The image sensor includes an active circuit region and bonding pads. The active circuit region has a first shape that is substantially rectangular. The substantially rectangular first shape has first chamfered corners. A perimeter of the frontside of the image sensor has a second shape that is substantially rectangular. The second substantially rectangular shape has second chamfered corners. The bonding pads are disposed on the frontside of the image sensor. The bonding pads are disposed between the first chamfered corners and the second chamfered corners. The first shape is disposed inside the second shape.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: December 23, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Tiejun Dai, Kuei Chen Liang
  • Patent number: 8916448
    Abstract: The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Tien-Jen Cheng, Mukta G. Farooq, John A. Fitzsimmons
  • Patent number: 8912656
    Abstract: An integrated circuit (IC) package includes an IC chip, a package carrier, and a plurality of conductive bumps connecting the IC chip to the package carrier. The IC chip includes a substrate and an IC layered structure configured on an active surface of the substrate. The active surface has a core area and a signal area surrounding the core area. The IC layered structure includes a first physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads, respectively. The first inner pads are arranged in multiple rows in the signal area.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: December 16, 2014
    Assignee: VIA Technologies, Inc.
    Inventors: Wei-Chih Lai, Jiang Fan
  • Patent number: 8907485
    Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: December 9, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo M. Higgins, III, Chu-Chung Lee
  • Patent number: 8907478
    Abstract: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Yu-Wen Liu, Ying-Ju Chen, Hsiu-Ping Wei
  • Patent number: 8901754
    Abstract: A semiconductor device comprises a semiconductor chip having a plurality of electrode pads; an insulation layer having one or more apertures which expose at least a part of the plurality of electrode pads respectively on the semiconductor chip; and a plurality of wires which are electrically connected to the exposed plurality of electrode pads.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: December 2, 2014
    Assignee: J-Devices Corporation
    Inventor: Osamu Yamagata
  • Patent number: 8901959
    Abstract: A hybrid IO cell for use with controlled collapse chip connection, wirebond core limited, wirebond IO limited, and wirebond inline chip designs is provided. A method of designing the hybrid IO cell includes designating a technology, determining a minimum pad width of the technology, and determining a minimum pad spacing of the technology. The method also includes determining a width of the hybrid IO cell based on the minimum pad width and the minimum pad spacing, setting a length of the hybrid IO cell equal to the determined width, and storing a definition of the IO cell in a library stored on a computer useable storage medium.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chris J. Rebeor, Rohit Shetty
  • Patent number: 8901728
    Abstract: A three-dimensional structure in which a wiring and a pad part are provided on a surface is provided. A recessed gutter for wiring and a hole for the pad part having a depth that is greater than a thickness of the recessed gutter for wiring are provided on the surface of the three-dimensional structure. The hole for the pad part is provided in succession with the recessed gutter for wiring. At least a part of a wiring conductor is embedded in the recessed gutter for wiring and in the hole for the pad part.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: December 2, 2014
    Assignee: Panasonic Corporation
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara
  • Patent number: 8878365
    Abstract: A semiconductor device, including: a semiconductor layer; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width; an interlayer dielectric formed above the first conductive layer and the second conductive layer; and an electrode pad formed above the interlayer dielectric. A connection section at which the first conductive layer and the second conductive layer are connected is disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad; and a reinforcing section is provided at the connection section.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: November 4, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki
  • Patent number: 8872356
    Abstract: Methods of forming a Ni material on a bond pad are disclosed. The methods include forming a dielectric material over an at least one bond pad, forming an opening within the dielectric material to expose the at least one bond pad, curing the dielectric material to form a surface of the dielectric material having a steep curvilinear profile, and forming a nickel material over the at least one bond pad. The dielectric material having a steep curvilinear profile may be formed by altering at least one of a curing process of the dielectric material and a thickness of the dielectric material. The dielectric material may be used to form a relatively thick Ni material on bond pads smaller than about 50 ?m. Semiconductor structures formed by such methods are also disclosed.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jaspreet S. Gandhi, Don L. Yates, Yangyang Sun
  • Patent number: 8866311
    Abstract: The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: October 21, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Hsiang-Ming Feng, Yen-Hua Kuo
  • Patent number: 8866308
    Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: October 21, 2014
    Assignee: Intel Corporation
    Inventors: Mihir K Roy, Mathew J Manusharow
  • Patent number: 8836147
    Abstract: A bonding structure of a ball-bonded portion is obtained by bonding a ball portion formed on a front end of a multilayer copper bonding wire. The multilayer copper bonding wire includes a core member that is mainly composed of copper, and an outer layer that is formed on the core member and is mainly composed of at least one noble metal selected from a group of Pd, Au, Ag and Pt. Further, a first concentrated portion of such noble metal(s) is formed in a ball-root region located at a boundary with the copper bonding wire in a surface region of the ball-bonded portion.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: September 16, 2014
    Assignee: Nippon Steel & Sumikin Materials Co., Ltd.
    Inventors: Tomohiro Uno, Takashi Yamada, Atsuo Ikeda
  • Patent number: 8836146
    Abstract: A chip package includes a semiconductor substrate, a first metal pad over the semiconductor substrate, and a second metal pad over the semiconductor substrate. In a case, the first metal pad is tape automated bonded thereto, and the second metal pad is solder bonded thereto. In another case, the first metal pad is tape automated bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is solder bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is solder bonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is wirebonded thereto.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: September 16, 2014
    Assignee: Qualcomm Incorporated
    Inventors: Chien-Kang Chou, Chiu-Ming Chou, Li-Ren Lin, Hsin-Jung Lo
  • Patent number: 8829693
    Abstract: Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond fingers may be connected together via one or more electrically conductive interconnects.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: September 9, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Mostafa Naguib Abdulla, Steven Eskildsen
  • Patent number: 8822325
    Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: September 2, 2014
    Inventors: Ching-Yu Ni, Chia-Ming Cheng, Nan-Chun Lin
  • Patent number: 8809124
    Abstract: A structure includes a hybrid substrate for supporting a semiconductive device that includes a bumpless build-up layer in which the semiconductive device is embedded and a laminated-core structure. The bumpless build-up layer and the laminated-core structure are rendered an integral apparatus by a reinforcement plating that connects to a plated through hole in the laminated-core structure and to a subsequent bond pad of the bumpless build-up layer structure.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: August 19, 2014
    Assignee: Intel Corporation
    Inventors: Mathew J Manusharow, Mark S Hlad, Ravi K Nalla
  • Patent number: 8810043
    Abstract: A semiconductor device includes a semiconductor element having a main surface where an outside connection terminal pad is provided. The semiconductor element is connected to a conductive layer on a supporting board via a plurality of convex-shaped outside connection terminals provided on the outside connection terminal pad and a connection member; and the connection member commonly covers the convex-shaped outside connection terminals.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takao Nishimura, Yoshikazu Kumagaya, Akira Takashima, Kouichi Nakamura, Kazuyuki Aiba
  • Patent number: 8796868
    Abstract: Apparatuses and methods for an improved semiconductor layout are described herein. Embodiments of the present invention provide a microelectronic device including a microelectronic die and one or more redistribution paths formed thereon for electrically interconnecting at least one bond pad with an exposed portion of the redistribution path. The redistribution paths, bond pads, and exposed portions may be configured to result in the device having a width narrowed by at least the width of the bond pads due to their absence on at least one edge.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: August 5, 2014
    Assignee: Marvell International Ltd.
    Inventors: Thomas Ngo, Shiann-Ming Liou
  • Patent number: 8791568
    Abstract: A semiconductor device includes a substrate, a surface electrode of aluminum-containing material formed on the substrate, a metal film of solderable material formed on the surface electrode, and an end-securing film securing an end of the metal film and having a portion on the surface electrode and also having an overlapping portion which is formed integrally with the portion on the surface electrode and which overlaps the end of the metal film.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: July 29, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Seiya Nakano, Yoshifumi Tomomatsu
  • Patent number: 8786084
    Abstract: A semiconductor package includes a semiconductor die attached to a support having electrically conductive paths, the semiconductor die having a bond-pad electrically connected to the electrically a conductive path on the support by a bond-wire of a first metallic composition, the bond-wire and the bond-pad being coated with a protection layer of a second metallic composition.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: July 22, 2014
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Jean-François Sauty