Abstract: A method of forming a protective structure on a top metal line on an interconnect structure is disclosed. The method includes providing a plate opening in the passivation layer on the top metal line and forming a protective plate in the plate opening on the top metal line.

Abstract: A solder bump on a semiconductor substrate is provided. The solder bump has a semiconductor substrate with a top copper pad thereon, a protective layer on the semiconductor substrate and at least one inorganic passivation layer overlying the protective layer with a first opening exposing the top copper pad, wherein the inorganic passivation layer has a thinner portion adjacent a top portion of the first opening. The solder bump further has a soft passivation layer on the inorganic passivation layer with a second opening larger than the first opening, an under bump metal layer conformally formed along the first opening and the second opening and a solder bump formed on the under bump metal layer.

Abstract: The present invention relates to an electronic device incorporating a heat distributor. It applies more particularly to devices of the plastic package type, with one or more levels of components. According to the invention, the electronic device, for example of the package type, is provided for its external connection with pads distributed over a connection surface. It includes a thermally conducting plate lying parallel to said connection surface and having a nonuniform structure making it possible, when the device is exposed to a given external temperature, to supply a controlled amount of heat to each external connection pad according to its position on the connection surface. If the device is a package comprising a support of the printed circuit type, the conducting plate will advantageously form an internal layer of said support.

Abstract: Systems and methods for vertically stacking integrated circuit (IC) modules on a motherboard to conserve motherboard space and reduce power consumption are disclosed. IC modules can comprise processor circuitry, memory elements, communication circuitry, etc. Pins on each IC module can be directly inserted into lower IC module or into a socket layer that couples the IC modules. Heat generated by the IC modules can be dissipated by inserting heat dissipation layers into the vertical stack, between IC modules, or by placing a heat-dissipating sleeve around the stack. The IC modules themselves and/or heat-generating regions therein may be misaligned on their respective socket layers to further facilitate dissipating heat. Module stacks are scalable in that a user may add memory and/or processor modules as desired to increase device capability.

Abstract: A metal pad formation method and metal pad structure using the same are provided. A wider first pad metal is formed together with a first metal. A dielectric layer is then deposited thereon. A first opening and a second opening are formed in the dielectric layer to respectively expose the first metal and the first pad metal. Then, the first opening is filled by W metal to generate a first via. Finally, a second metal and a second pad metal are formed to respectively cover the first via and the first pad metal to generate the metal pad.

Abstract: A semiconductor device includes a carrier, a chip including a first face having a contact area, where the chip is attached to the carrier such that the contact area faces away from the carrier, a copper connector configured for attachment to the contact area, and a solder material configured to couple the copper connector to the contact area.

Abstract: A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.

Abstract: A semiconductor die featuring vertical rows of bonding pad structures is disclosed. The rows of bonding pad structures are located vertically in the Y direction, or traversing the width of the semiconductor die. A vertical row of bonding pad structures is located on each side of the semiconductor die while a third vertical row of bonding pad structures is located in the center of the semiconductor die. A first set of wire bonds connect each bonding pad structure located on the sides of the semiconductor die to a conductive lead structure located on a ceramic package. A second set of wire bonds connect each bonding pad structure located in the center of the semiconductor die to a lead on chip (LOC) structure located on the semiconductor die.

Abstract: Techniques are provided for reducing the power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive traces. The conductive traces are coupled to solder bumps that receive power supply voltages from an external source. Alternate ones of the traces receive a high power supply voltage VDD and a low power supply voltage VSS. The conductive traces reduce the voltage drop in the power supply voltages by providing shorter paths to route the power supply voltages to circuit elements on the integrated circuit.

Abstract: A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second semiconductor device spaced apart from the first device, a dielectric layer interposed between the first device and the second device, a first conductive pad positioned in the first device, and a second conductive pad positioned in the second device that capacitively communicate signals from the second device to the first device. In another embodiment, a method of forming a SiP device includes forming a first pad on a surface of a first semiconductor device, forming a second pad on a surface of a second semiconductor device, and interposing a dielectric layer between the first semiconductor device and the second semiconductor device that separates the first conductive signal pad and the second conductive signal pad.

Abstract: There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross-section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire 29.

Abstract: Embodiments provide for integrated circuit chip and device having such an integrated circuit, in which different types of pads are arranged in separate rows. In one embodiment the pads are arranged to reduce the loop inductance of corresponding signal and power supply bond wires.

Abstract: A conductive bump structure for an integrated circuit (IC) structure comprises a passivation layer, such as a silicon oxide/silicon nitride stack, that is formed on an upper surface of each of the conductive contact pads (e.g. Al pads) of the IC. A plurality of openings extend through the passivation layer to expose areas of the upper surface of the contact pad. The openings are larger in the longitudinal dimension than in the lateral dimension. A conductive bump, preferably comprising gold (Au), is formed on the passivation layer to extend through the openings in the passivation and into electrical contact with the exposed upper surface areas of the contact pad.

Abstract: A silicon carbide device includes at least one power electrode on a surface thereof, a solderable contract formed on the power electrode, and at least one passivation layer that surrounds the solderable contact but is spaced from the solderable contract, thereby forming a gap.

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract: A solder bump on a semiconductor substrate is provided. The solder bump comprises a semiconductor substrate having a top copper pad thereon, a protective layer on the semiconductor substrate and at least one inorganic passivation layer overlying the protective layer with a first opening exposing the top copper pad, wherein the inorganic passivation layer has a thinner portion adjacent a top portion of the first opening. The solder bump further comprises a soft passivation layer on the inorganic passivation layer with a second opening larger than the first opening, an under bump metal layer conformally formed along the first opening and the second opening and a solder bump formed on the under bump metal layer.

Abstract: A semiconductor package structure and the methods for forming the same are provided. The semiconductor package structure includes an interposer; a first plurality of bonding pads on a side of the interposer; a semiconductor chip; and a second plurality of bonding pads on a side of the semiconductor chip. The first and the second plurality of bonding pads are bonded through metal-to-metal bonds.

Abstract: An integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is over the substrate. A second metallurgy layer is over the first metallurgy layer. A protective layer is over the first contact pad.

Abstract: A semiconductor device has: a circuit portion having semiconductor elements formed on a semiconductor substrate; insulating lamination formed above the semiconductor substrate and covering the circuit portion; a multilevel wiring structure formed in the insulating lamination and including wiring patterns and via conductors; and a pad electrode structure formed above the semiconductor substrate and connected to the multilevel wiring structure. The pad electrode structure includes pad wiring patterns and pad via conductors interconnecting the pad wiring patterns, the uppermost pad wiring pattern includes a pad pattern and a sealing pattern surrounding the pad pattern in a loop shape. Another pad wiring pattern has continuous extended pad pattern of a size overlapping the sealing pattern. The pad via conductors include a plurality of columnar via conductors disposed in register with the pad pattern and a loop-shaped wall portion disposed in register with the sealing pattern.

Abstract: The present invention is a semiconductor device characterized by including a substrate, an insulating film consisting of a fluorine added carbon film formed on the substrate, a barrier layer consisting of a silicon nitride film and a film containing silicon, carbon, and nitride formed on the insulating film, and a hard mask layer having a film containing silicon and oxygen formed on the barrier layer, wherein the barrier layer consists of a silicon nitride film and a film containing silicon, carbon, and nitride that are laminated from the bottom in that order, and functions to prevent the fluorine in the fluorine added carbon film from moving to the hard mask layer.

Abstract: A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation layer on the first pad, the inter-connection line, and the second pad; exposing the first and second pads by patterning the etch-stop layer and the first insulation layer; forming third and fourth pads including a second metal on the first and second pads; sequentially forming second and third insulation layers on the third pad, the fourth pad, and the patterned first insulation layer; and etching the first, second, and third insulation layers using the patterned photosensitive layer on the third insulation layer to expose the third and fourth pads.

Abstract: A method is disclosed for attaching a bonding pad to the ohmic contact of a diode while reducing the complexity of the photolithography steps. The method includes the steps of forming a blanket passivation layer over the epitaxial layers and ohmic contacts of a diode, depositing a photoresist layer over the blanket passivation layer, opening a via through the photoresist above the ohmic contacts and on the blanket passivation layer, removing the portion of the blanket passivation layer defined by the via to expose the surface of the ohmic contact, depositing a metal layer on the remaining photoresist, and on the exposed portion of the ohmic contact defined by the via, and removing the remaining photoresist to thereby concurrently remove any metal on the photoresist and to thereby establish a metal bond pad on the ohmic contact in the via.

Abstract: A semiconductor chip embedding structure is disclosed, including a carrier board having a first and an opposed second surfaces and formed with at least a through hole; a semiconductor chip received in the through hole, the chip having an active surface and an inactive surface opposite to one another, wherein the active surface has a plurality of electrode pads, a passivation layer is formed on the active surface with the electrode pads exposed from the passivation layer, and metal pads are formed on surfaces of the electrode pads; a buffer layer formed on the first surface of the carrier board and on surfaces of the passivation layer and the metal pads; a first dielectric layer formed on the buffer layer; and a first circuit layer formed on the first dielectric layer and electrically connected with the metal pads of the chip via first conductive structures formed in the buffer layer and the first dielectric layer, wherein the CTE (Coefficient of Thermal Expansion) of the buffer layer is between the CTE of the

Abstract: A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to expose a portion of the stud and then forming a conductive layer inside the trench and in electrical contact with the stud.

Abstract: There is provided a semiconductor device whose cost is low and whose case is restrained from breaking. In the semiconductor device having a semiconductor sensor chip, a signal processing circuit for processing signals output from the semiconductor sensor chip and a hollow case for mounting the semiconductor sensor chip and the signal processing circuit therein, the case is constructed by bonding a concave bottom member whose one end is opened with a plate-like lid member that covers the opening of the bottom member. Then, the bottom and lid members are both made of a semiconductor material and are bonded by means of anode bonding or metal bonding for example.

Abstract: Consistent with an example embodiment, an electronic device comprises a semiconductor device, particularly an integrated circuit, and a carrier substrate with conductive layers on the first side and the second side, and voltage supply and ground connections mutually arranged according to a chessboard pattern. These connections extend in a direct path through vertical interconnects and bumps to bond pads at the integrated circuit, which bond pads are arranged in a corresponding chessboard pattern. As a result, an array of direct paths is provided, wherein the voltage supply connections form as much as possible the coaxial center conductors of a coaxial structure.

Abstract: An inorganic solder mask (48) for use as a surface treatment in masking a connection conductor (32) of a semi-conductor chip package (10) against solder wetting when mounting the chip package (10) to a printed wiring board (50) or other substrate. The connection conductor (32) is partially covered by a metallization contact (42) formed from a distinct metal. The inorganic solder mask (46) is applied to an exposed portion (44) of the connection conductor (32) not covered by the metallization contact (42). The metallization contact (42) is not coated by the inorganic solder mask (46). The presence of the inorganic solder mask (46) significantly reduces or prevents wetting of the exposed portion (44) when molten solder is present on the connection conductor (32) without affecting the solidified solder layer (48) formed on the metallization contact (42). As a result, an extraneous mass of solder does not solidify on the exposed portion (44) of the connection conductor (32).

Abstract: A semiconductor chip or wafer comprises a passivation layer and a circuit line. The passivation layer comprises an inorganic layer. The circuit line is over and in touch with the inorganic layer of the passivation layer, wherein the circuit line comprises a first contact point connected to only one second contact point exposed by an opening in the passivation layer, and the positions of the first contact point and the only one second contact point from a top view are different, and the first contact point is used to be wirebonded thereto.

Abstract: A semiconductor device includes: a plurality of power MOS cells on a semiconductor substrate; a plurality of lead wires connecting to a source and a drain of each power MOS cell through a contact hole; a plurality of collecting electrodes connecting in parallel with the lead wires through a via hole; an interlayer protection film on the collecting electrode; a thick film electrode connecting to the collecting electrode through the opening; and a terminal protection film having an opening for bonding connection.

Abstract: A semiconductor device includes a plurality of electrode layers provided at designated positions of a semiconductor substrate, an organic insulation film formed on the semiconductor substrate by selectively exposing designated areas of the electrode layers, and projection electrodes for outside connection, the projection electrodes being formed on the designated areas of the electrode layers. Thickness of the organic insulation film situated in the vicinity of the periphery of the projection electrodes is greater than thickness of the organic insulation film situated between the projection electrodes.

Abstract: A semiconductor device is composed of a semiconductor chip, aluminum pads formed on the semiconductor chip, alloy ball bumps, which are formed on the aluminum pads, containing gold and Pd, and gold wires, which are connected to the alloy ball bumps, having a surface made of gold. The alloy ball bumps may be composition containing gold not less than 98 mass % to not more than 99.5 mass % and palladium not less than 0.5 mass % to not more than 2 mass %. The semiconductor device having above configuration is excellent in long-term reliability.

Abstract: A chip holder formed of silicon, glass, other ceramics or other suitable materials includes a plurality of recesses for retaining semiconductor chips. The bond pads of the semiconductor chip are formed on or over an area of the chip holder that surrounds the semiconductor chip thus expanding the bonding area. The bond pads are coupled, using semiconductor wafer processing techniques, to internal bond pads formed directly on the semiconductor chip.

Abstract: An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.

Abstract: A semiconductor device includes: a semiconductor substrate that has an integrated circuit and an electrode electrically connected to the integrated circuit; a first resin layer that is formed in a first region overlapping the integrated circuit over a surface of the semiconductor substrate where the electrode is formed; a wiring that is electrically connected to the electrode and is formed on the first resin layer; and a second resin layer that is formed on the surface of the semiconductor substrate in a second region surrounding the first region, is the second resin layer being spaced a distance from the first resin layer.

Abstract: An electronic device having a bonding pad structure and a method of fabricating the same is provided. The electronic device may include a first bonding pads formed on the substrate. A second bonding pad may be formed on the lower insulating layer. The second bonding pads may be spaced apart from the first bonding pads. The second bonding pads may have a top surface formed at a higher level than the first bonding pads.

Abstract: In the BGA package and its manufacturing method, a bonding pad is etched from the exposed surface to a part of the insulation layer-coated region so as to form a solder contact side having a dish configuration, which is planar at a bottom center and slanted at a periphery. With this bent structure of the dish configuration, the bonding pad provides an increased bonding area for the solder, so that the BGA package substrate is enhanced in reliability.

Abstract: A method for manufacturing passive devices and semiconductor packages using a thin metal piece is provided. According to the method, an adhesive layer is formed on a dummy substrate; a thin metal piece is bonded on the adhesive layer; a masking material is attached to the thin metal piece, a region where vias are to be formed is patterned, the thin metal piece is etched at a predetermined depth; the masking material is removed, the etched portion is filled with polymer to form a flat polymer layer, a masking material is attached on the polymer layer, a region that is to be attached to an IPD or an IC chip is patterned, a metal pad is formed, and the formed devices are attached to a lower substrate using the metal pad; the adhesive layer and the dummy substrate are removed, a masking material is attached on a surface exposed, a region where passive devices are to be formed is patterned, and the thin metal piece is etched at a predetermined depth; and solder bumps for surface mounting are formed.

Abstract: This invention provides a semiconductor device. The semiconductor device includes a bonding pad array comprising: a signal bonding pad, a control pin bonding pad and at least one stacking bonding pad on an active surface. At least one stacking bonding pad is adjacent to the control pin bonding pad. This invention also provides a stacked structure of semiconductor devices and/or a semiconductor device package including the semiconductor device.

Abstract: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

Abstract: A semiconductor device having bonding pads on a semiconductor substrate includes: an upper copper layer that is formed on the lower surface of the bonding pads with a barrier metal interposed and that has a copper area ratio that is greater than layers in which circuit interconnects are formed; and a lower copper layer that is electrically insulated from the upper copper layer and that is formed closer to the semiconductor substrate than the upper copper layer.

Abstract: The invention provides a package type semiconductor device and a manufacturing method thereof where reliability is improved without increasing a manufacturing cost. A resin layer and a supporting member are formed on a top surface of a semiconductor substrate formed with pad electrodes. Then, openings are formed penetrating the resin layer and the supporting member so as to expose the pad electrodes. Metal layers are then formed on the pad electrodes exposed in the openings, and conductive terminals are formed thereon. Finally, the semiconductor substrate is separated into semiconductor dice by dicing. When this semiconductor device is mounted on a circuit board (not shown), the conductive terminals of the semiconductor die and external electrodes of the circuit board are electrically connected with each other.

Abstract: A pad structure includes a first metal-containing layer formed over a substrate. A first passivation layer is formed over the first metal-containing layer. The first passivation layer has a first opening partially exposing the first metal-containing layer. A pad layer is formed over the first passivation layer, covering the first opening. The pad layer includes a probing region configured to be contacted by a probe and a bonding region configured to have a wired bonded to it. The probing region contacts the first metal-containing layer through the first opening, and the bonding region overlies a portion of the first passivation layer.

Abstract: Vias and conductive pads configured and coupled in a manner to reduce delamination are described herein. The via and the conductive pads may be located in a substrate such as a carrier substrate, a die, or a printed circuit board.

Abstract: A semiconductor device has a plurality of bumps in a same row for staggered probing. The bumps in a same row are disposed on a chip and include a plurality of regular bumps and a plurality of irregular bumps. The regular bumps and the irregular bumps are interspersed in a same pitch. Along a defined line, the widths of the irregular bumps are narrower than the ones of the regular bumps for fine pitch applications. Additionally, the irregular bumps have a plurality of integral probed portions far away the line, top surfaces of which are expanded such that probed points can be defined on the probed portions for staggered probing.

Abstract: A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.

Abstract: A housing having a non-detachable bond to a micromechanical component using a flexible bonding material in particular. The combination including the housing and the micromechanical component as well as the manufacturing method of this combination. At least part of the component and/or of the housing has depressions for receiving the bonding material. These depressions may be designed as grooves, for example.

Abstract: An advantage of the present invention is to suppress moisture infiltrating from a pad electrode portion from spreading over the surface of a wiring pattern and improve the reliability of a packaging board. The wiring pattern of the packaging board is formed on an insulating substrate and includes a wiring region, an electrode region (pad electrode) connected with a semiconductor device, and a boundary region provided between the wiring region and the electrode region. A gold plating layer is provided on the surface of the electrode region of the wiring pattern. The top surface of the boundary region of the wiring pattern is so formed as to be dented from the top surface of the wiring region of the wiring pattern, and there is provided a stepped portion in the boundary region.

Abstract: In one embodiment, a semiconductor package is formed by adding a layer of particles to desired portions of a packing substrate. The layer of particles forms a matrix of crevices that provides a micro-lock feature for mechanically locking or engaging encapsulating materials.

Abstract: An aspect of the semiconductor device comprising a package substrate which has a plurality of pads to which a power supply voltage is applied on an upper surface thereof, a first memory chip which is arranged on the package substrate and has a first power supply pad provided on a first side and a second power supply pad provided on a second side perpendicular to the first side, and a second memory chip which is translated in a direction along which the first and second power supply pads of the first memory chip are exposed, arranged on the first memory chip, and has the same structure as the first memory chip, wherein the first and second power supply pads are provided at diagonal corners of the first memory chip, respectively.

Abstract: An integrated circuit package bond pad includes an insulating layer and an electrode located over the insulating layer. The electrode has a first surface configured to be bonded to external circuitry and a second surface opposite the first surface. A plurality of conductive members is located in the insulating layer, wherein ones of the plurality of conductive members contact the second surface of the electrode.