Abstract: An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated.

Abstract: The present invention is directed to a power semiconductor device in which a control circuit controls a power switching element, comprising: a semiconductor substrate having a front surface and a back surface; a capacitor disposed on the front surface side of the semiconductor substrate and being comprised of a stacked structure of a first conductive layer, an insulation film and a second conductive layer; and a bonding pad which is disposed on the front surface side to the capacitor and to which a bonding wire being connected, wherein the bonding pad are arranged overlapping the capacitor.

Abstract: Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.

Abstract: A semiconductor chip includes: a semiconductor substrate; a penetrating electrode which is formed through the semiconductor substrate from a first surface to a second surface of the semiconductor substrate and has a projection which projects from the second surface; an insulating layer formed over an entire surface of the second surface. The insulating layer includes a first insulating section formed in a region around the projection and a second insulating section other than the first insulating section. The second insulating section is formed to be thinner than a thickest area of the first insulating section.

Abstract: A semiconductor device having a semiconductor substrate, at least one of a protruding electrode and wiring formed on one surface of the semiconductor substrate, and a first resin film formed on this surface. The first resin film has elasticity low enough to reduce stress induced by a difference in thermal expansion coefficient between the semiconductor substrate and the first resin film. A second resin film, having higher elasticity or higher strength than the first resin film, may be formed on the other surface of the semiconductor substrate.

Abstract: A pad structure includes a first metal-containing layer formed over a substrate. A first passivation layer is formed over the first metal-containing layer. The first passivation layer has a first opening partially exposing the first metal-containing layer. A pad layer is formed over the first passivation layer, covering the first opening. The pad layer includes a probing region configured to be contacted by a probe and a bonding region configured to have a wired bonded to it. The probing region contacts the first metal-containing layer through the first opening, and the bonding region overlies a portion of the first passivation layer.

Abstract: The electronic device (100) comprises a semiconductor element (1) (e.g. a transistor), an encapsulation (5) and an electrically conductive layer (3) with a first and a second contact pad (11,12), used as signal pads, and a third contact pad (13) used as ground pads. Due to the shape of the contact pads (11,12,13), the spacing (200) is continuous, with a small entrance in between of the first and second contact pads (11,12). Consequently, the parasitic inductance is reduced and the device (100) is suitable for use at frequencies below and above 30 GHz, particularly up to 40 GHz.

Abstract: A multi-layered circuit board a built-in component including multiple terminals, at least one signal pad formed on a top surface of the multi-layered circuit board for signal transmission, each of the at least one signal pad corresponding to one of the multiple terminals, and at least one test pad formed on the top surface of the multi-layered circuit board, each of the at least one test pad corresponding to one of the at least one signal pad for testing an electric path extending from the one signal pad through the one terminal to the each of the at least one test pad.

Abstract: Various systems and methods for implementing multi-mode semiconductor devices are discussed herein. For example, a multi-mode semiconductor device is disclosed that includes a device package with a number of package pins. In addition, the device includes a semiconductor die or substrate with at least two IO buffers. One of the IO buffers is located a distance from a package pin and another of the IO buffers is located another distance from the package pin. One of the IO buffers includes first bond pad electrically coupled to a circuit implementing a first interface type and a floating bond pad, and the other IO buffer includes a second bond pad electrically coupled to a circuit implementing a second interface type. In some cases, the floating bond pad is electrically coupled to the circuit implementing the second interface type via a conductive interconnect, and the floating bond pad is electrically coupled to the package pin.

Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.

Abstract: The present invention provides an indexed support substrate. The support substrate comprises at least one set of indexing features that are distinguishable from one another and from the surrounding substrate. The support substrate also comprises a set of useful domains. The indexing features are positioned on the substrate in such a way as to correspond to the useful domains in an identifying fashion.

Abstract: An apparatus and method for incorporating discrete passive components into an integrated circuit package. A metal layer is formed over a surface of a substrate. A layer of photosensitive material is then formed over the metal layer. Using standard photolithographic processing, a pattern is formed with the photosensitive material to expose at least one region of the metal layer. The remaining photosensitive material protects the underlying metal during metal etching. The substrate is then subjected to a metal etching process to remove the metal that is not protected by the photosensitive material. The remaining photosensitive material is then removed from each remaining area of the metal layer. The discrete passive components can then be attached to the formed metal lands.

Abstract: There is provided a solution to the problem of the poor adhesion in the pad portion while inhibiting the dishing in the pad portion. An SiON film, which covers insulating areas and has an opening above Cu pad areas, is formed, and a barrier metal film is formed in the opening of the SiON film. Such constitution provides the structure, in which the upper portion of the interfaces between the Cu pad areas and the insulating areas are covered by the SiON film.

Abstract: Disclosed is a method of realizing thermosonic wire bonding between metal wires and copper pads by depositing a thin film to surfaces of semiconductor chips with copper pads, where a thin film that provides the effect of self-passivation to prevent oxidization of the copper pads located thereunder is deposited on surfaces of the copper pads to provide sufficient protection to the chips with copper pads thereby preventing copper from oxidizing at elevated temperature during packaging, due to die sawing, die mounting or curing and thermosonic wire bonding, which would result in failure of bonding metal wires to the copper pads, poor bondability between the metal wires and the copper pads, or low bonding strength of the bonds.

Abstract: An electrical package for an integrated circuit die which comprises a die-attach paddle for mounting the integrated circuit die. The die-attach paddle has at least one down-set area located on a periphery of the die-attach paddle. The down-set area has an upper surface and a lower surface, with the upper surface configured to electrically couple a first end of a first electrically conductive lead wire. A second end of the first electrically conductive lead wire is bonded to the integrated circuit die. The upper surface is further configured to electrically couple a first end of a second electrically conductive lead wire and a second end of the second electrically conductive lead wire is bonded to a lead finger of the electrical package.

Abstract: An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated.

Abstract: In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.

Abstract: A semiconductor chip structure includes a top metal layer and an inter-layer dielectric under the top metal layer. The top metal layer includes a bonding pad area and a non-bonding pad area. The inter-layer dielectric includes at least one first via disposed under the bonding pad area, and a plurality of conventional second vias disposed under the non-bonding pad area. The size of the first via is much larger than the size of the second via to improve bonding pad reliability. The cross section of the first via is a rectangular, a square, or a polygonal. The top metal layer has a predefined thickness to improve a yield of a wire bonding.

Abstract: A semiconductor chip or wafer comprises a passivation layer and a circuit line. The passivation layer comprises an inorganic layer. The circuit line is over and in touch with the inorganic layer of the passivation layer, wherein the circuit line comprises a first contact point connected to only one second contact point exposed by an opening in the passivation layer, and the positions of the first contact point and the only one second contact point from a top view are different, and the first contact point is used to be wirebonded thereto.

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line and a metal pillar, a connection joint that electrically connects the routing line and the pad, and an encapsulant. The metal pillar includes tapered sidewalls with first and second sidewall portions and a spike, and the first and second sidewall portions are concave arcs that are adjacent to one another at the spike.

Abstract: The invention provides methods and systems for laser assisted wirebonding. One or more conditioning laser pulses are used to prepare a bonding surface for wirebonding by removing impurities such as residues from manufacturing processes, oxides, or irregularities on the bonding surface. Subsequently, a free air ball is brought into contact with the conditioned bonding surface to form a weld.

Abstract: A ball grid array package includes a substrate, a chip, a plurality of pads, a solder mask, a plurality of partitioning walls, and a plurality of solder balls. The substrate has an upper surface and a lower surface opposite to the upper surface. The chip is disposed on the upper surface of the substrate. The pads are disposed on the lower surface of the substrate and electrically connected to the chip. The solder mask is disposed on the lower surface of the substrate. The partitioning walls are disposed on the solder mask and between the adjacent pads. The solder balls are respectively disposed on the pads.

Abstract: An interlayer insulating film is formed on a semiconductor substrate. An intra-layer insulating film is formed on the interlayer film. A recess is formed through the intra-layer film. The recess has a pad-part and a wiring-part continuous with the pad-part. The pad-part is wider than the width of the wiring-part. Convex regions are left in the pad-part. The convex regions are disposed in such a manner that a recess area ratio in a near wiring area superposed upon an extended area of the wiring-part into the pad-part, within a first frame area having as an outer periphery an outer periphery of the pad-part and having a first width, becomes larger than a recess area ratio in a second frame area having as an outer periphery an inner periphery of the first frame area and having a second width. A conductive film is filled in the recess.

Abstract: A manufacturing method of a package substrate is disclosed. The method for manufacturing a package substrate is by forming a bump on a bump pad in a core board, where a first circuit pattern including the bump pad is formed on one surface, a second circuit pattern electrically connected with the first circuit pattern is formed on the other surface, and a dielectric layer is selectively coated on the one surface such that the bump pad is exposed. The method includes layering a conductive layer on the other surface of the core board, coating a plating resist on the conductive layer, forming the bump by supplying electricity to the conductive layer to electroplate the bump pad, and removing the plating resist and the conductive layer.

Abstract: An electronic component has an electronic circuit and a rubber-elastic elevation. The rubber-elastic elevation is formed of an insulating rubber-elastic material disposed on a surface of the electronic component and has a conductive land on its crest. The rubber-elastic elevation also has on its sloping side or in its volume a conduction path between the land and the electronic circuit.

Abstract: A method is provided for forming a microelectronic assembly. A contact structure (46) is formed over a first side of a first substrate (20) having a microelectronic device formed over a second side thereof. The contact structure is electrically connected to the microelectronic device. A non-solderable layer (52) is formed over at least a portion of the contact structure and at least a portion of the first substrate. The contact structure and a second substrate (62) are interconnected with solder (68).

Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.

Abstract: An integrated circuit (IC) carrier assembly includes a printed circuit board (PCB). A carrier is soldered to the PCB. The carrier includes a grid of electrical contact islands surrounding a receiving zone for receiving an IC. Pairs of adjacent islands are interconnected by respective resilient suspension means. The IC is received in the receiving zone and is electrically coupled to a number of the plurality of islands adjacent to the receiving zone. The IC is fast to a retainer, and the retainer is fast with the number of the plurality of islands and the IC.

Abstract: A semiconductor apparatus includes a semiconductor device to be mounted on a circuit board; a plurality of conductive posts electrically connected to the semiconductor device; and a plurality of conductive bumps each provided on an outer end of each of the conductive posts, so that the plurality of conductive bump is soldered onto the circuit board when the semiconductor device is mounted on the circuit board. A distance between a peripheral edge of the semiconductor device and an outer edge of the conductive post is determined to be narrow so that a solderbility or wetting condition of the conductive bumps can be visibly recognized easily.

Abstract: A pad electrode of a field effect transistor is formed solely of a pad metal layer without providing a gate metal layer. A high concentration impurity region is provided below the pad electrode, and the pad electrode is directly contacted to a substrate. Predetermined isolation is ensured by the high concentration impurity region. Accordingly, in a structure not requiring a nitride film as similar to the related art, it is possible to avoid defects upon wire boding attributing to hardening of the gate metal layer. Therefore, in the case of a buried gate electrode structure for enhancing characteristics of the field effect transistor, it is possible to enhance reliability and yields.

Abstract: The present invention provides a metallization scheme, a method for manufacturing the metallization scheme, and an integrated circuit including the metallization scheme. In one aspect, the metallization scheme (300) includes a protective layer (320) located over a substrate (310), and a conductive layer (330) located over the protective layer (320). The metallization scheme (300) further includes a stress-reducing low-modulus material (340) located between the protective layer (320) and the conductive layer (330).

Abstract: An input and output circuit of an integrated circuit chip for exchanging signals between logic circuits of the integrated circuit chip and a system. The input and output circuit includes a plurality of power rings for providing a plurality of power sources, a plurality of input and output pads for transmitting signals, a sequence of input and output cells for transmitting signals, and a plurality of electrostatic discharge protection cells deposited within the sequence of input and output cells for performing electrostatic discharge protection for the input and output cells, wherein the plurality of electrostatic discharge protection cells are not coupled to any input and output pads.

Abstract: The present invention provides a QFN package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive leads as I/O pads of the chip carrier for the external circuitry. A plurality of pads, corresponding to bonding pads of the chip, is disposed on the top surface of the chip carrier. The aforementioned package structure can employ wiring bonding technology, flip chip technology or surface mount technology to attach the chip to the chip carrier.

Abstract: A wire connection structure for an integrated circuit (IC) die includes a semiconductor wafer with an active device and/or a passive device. One or more dielectric layers are arranged adjacent to the active and/or passive device. One or more metal interconnect layers are arranged adjacent to the active and/or passive device. A contact pad is arranged in an outermost metal interconnect layer. A passivation layer is arranged over the outermost metal interconnect layer and includes at least one passivation opening that exposes the contact pad. A bond pad is arranged over the passivation layer and the active and/or passive device and is connected to the contact pad through the passivation opening. Formation of the bond pad does not damage the active and/or passive device.

Abstract: The present invention provides an apparatus and methods for the functionality of an integrated circuit. An exemplary embodiment according to an aspect of the present invention includes a ball grid array having open spaces therein. Within the open spaces, pairs of opposite polarity vias are clustered to minimize current path inductance by exploiting mutual inductance between vias of opposite current flow. In an illustrative embodiment, capacitors are coupled to the vias to further reduce current path inductance.

Abstract: A semiconductor die includes a plurality of drivers and a plurality of bonding pads. Each driver is formed by a plurality of interconnected modules and has an associated bonding pad to which at least one of the modules of the driver is electrically connected. The modules of some of the drivers are positioned outside of the associated bonding pad toward a periphery of the die. The bonding pads may be arranged, for example, in a double- or triple-staggered pattern around the periphery of the die.

Abstract: The present invention discloses a semiconductor device having a pad structure for preventing a stress of a silicon nitride film. The semiconductor device includes a semiconductor substrate, a lower structure formed on the semiconductor substrate, a first insulation film formed on the lower structure, a first metal layer coupled to the lower structure through a first metal contact in the first insulation film, a second metal layer formed on the first metal layer, and a plurality of dummy gates having a concentric square structure formed at the lower portion of the pad region on the second metal layer.

Abstract: A solderable device includes a substrate and a soldering pad overlying the substrate. A solder mask overlies the substrate and portions of the soldering pad. The solder mask has an opening that exposes a portion of the soldering pad. The opening has at least two edges that symmetrically overlie portions of the soldering pad.

Abstract: A semiconductor device comprises a substrate, an external terminal provided on the substrate, an internal wiring pattern electrically connected to the external terminal, a semiconductor chip mounted on the substrate and electrically connected to the internal wiring pattern, and an antenna pattern. The antenna pattern provided at each of adjacent two corner portions of the substrate and is grounded.

Abstract: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.

Abstract: The present invention discloses a structure of wafer level packaging. The structure comprises a first patterned isolation layer, a conductive layer and a second patterned isolation layer. The first patterned isolation layer is formed with a passivation layer of an IC (Integrated Circuit). The conductive layer is configured to have a curved or winding conductive pattern. The second patterned isolation layer is formed over the conductive layer to have a plurality of openings, and contact metal balls can be formed on the openings to electrically couple to a print circuit board.

Abstract: A wiring board includes a film base, a plurality of conductive wirings aligned on the film base, and protrusion electrodes formed of a plated metal in the vicinity of end portions of the conductive wirings, respectively. An outer surface at both side portions of the protrusion electrodes in cross section in a width direction of the conductive wirings defines a curve, and the protrusion electrodes in cross section in a longitudinal direction of the conductive wirings define a rectangular shape. The conductive wirings include a first conductive wiring having a wiring width of W1 and a second conductive wiring having a wiring width of W2 larger than W1, and the protrusion electrode on the first conductive wiring and the protrusion electrode on the second conductive wiring have a substantially same height.

Abstract: Consistent with an example embodiment, an electronic device comprises an integrated circuit and a carrier substrate with a bottom and top conductive layer, and is provided with voltage supply, ground and signal transmission connections. In order to enable the use of more than one supply voltage, the integrated circuit is subdivided into core functionality and peripheral functionality, and the carrier substrate is subdivided into a corresponding core area and peripheral area. The ground connections of both core and periphery are mutually coupled through an interconnect in the carrier substrate. This interconnect is particularly a ground plane, and allows the provision of a transmission line character to the interconnects for signal transmission of the periphery.

Abstract: A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. The redistribution layer is formed over the first passivation layer and electrically connected to the bonding pad. Furthermore, the redistribution layer also extends from the bonding pad to the recess. The second passivation layer is formed over the first passivation layer and the redistribution layer. The second passivation layer also has an opening that exposes the redistribution layer above the recess. The bump passes through the opening and connects electrically with the redistribution layer above the recess.

Abstract: Disclosed is a method for forming a bonding pad of a semiconductor device. The present invention provides a method for forming a bonding pad of a semiconductor device comprising the steps of: (a) forming a top metal line having a predetermined width on a structure of a semiconductor substrate; (b) forming an insulating layer on the top metal line and the structure of the semiconductor substrate; (c) selectively etching the insulating layer to form a bonding pad which exposes portions of the top metal line; (d) performing a plasma treatment over the semiconductor substrate by using CF4, Ar, and O2 gas.

Abstract: In an integrated circuit (1) having a substrate (3) and having a signal-processing circuit (4) which is produced at a surface (8) of the substrate (3), there is provided on the substrate surface (8) a protective layer (12) that has at least one aperture (13) through which a second contact pad (14) is electrically and mechanically connected to a first contact pad (9), wherein the second contact pad (14) is of a height of at least 15 ?m and projects laterally beyond the aperture (13) on all sides and is seated on the protective layer (12) by an overlap zone (z) that is closed on itself like a ring, wherein the overlap zone (z) has a constant width of overlap (w) of between 2 ?m and 15 ?m, and wherein at least one element of the signal-processing circuit (4), and preferably only one capacitor (5) of the signal-processing circuit (4), is provided opposite the first contact pad (9).

Abstract: A wafer level chip scale package capable of reducing parasitic capacitances between a rerouting and the metal wiring of a wafer, and a method for manufacturing the same are provided. An embodiment of the wafer level chip scale package includes a wafer arranged with a plurality of bonding pads and an insulating member formed on the wafer so that the bonding pads are exposed. A rerouting is further formed on the insulating member in contact with the exposed bonding pads and an external connecting terminal is electrically connected to a portion of the rerouting. Here, the insulating member overlapping the rerouting is provided with a plurality of spaces in which air is trapped.

Abstract: According to one exemplary embodiment, a structure in a semiconductor die comprises a metal pad situated in an interconnect metal layer, where the metal pad comprises copper. The structure further comprises an interlayer dielectric layer situated over the metal pad. The structure further comprises a terminal via defined in the interlayer dielectric layer, where the terminal via is situated on the metal pad. The terminal via extends along only one side of the metal pad. The structure further comprises a terminal metal layer situated on the interlayer dielectric layer and in the terminal via. The structure further comprises a dielectric liner situated on the terminal metal layer, where a bond pad opening is defined in the dielectric liner, and where the bond pad opening exposes a portion of the terminal metal layer. The interlayer dielectric layer is situated between the exposed portion of the terminal metal layer and metal pad.

Abstract: A wiring substrate having variously sized ball pads, a semiconductor package including the wiring substrate, and a stack package using the semiconductor package, to improve board level reliability (BLR) of a semiconductor package or stack package mounted on a mother board are shown. Outer ball pads are formed to have relatively greater surface areas at the corners of the semiconductor package as compared to those at other areas and are formed to have the greatest surface area within a designable range. Additionally, occurrence of cracks may be inhibited at junctions of other solder balls by forming dummy solder pads at the outermost corners among the outer ball pads formed proximate to the corners of the wiring substrate. Stress arising during a board level reliability test is absorbed without product failure at junctions between the dummy solder pads and dummy solder balls.

Abstract: A bond pad structure for an integrated circuit includes first and second active devices formed in a substrate, first and second buses above the first and second active devices, respectively, a bond pad above the first and second buses, first interconnections between the first and second active devices and the bond pad, and second interconnections between the first and second active devices and the first and second buses, respectively. The first active device may be at least one PMOS transistor, and the second active device may be at least one NMOS transistor. A guard band region may be formed in the substrate.