Abstract: A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.

Abstract: A wire bonding structure includes a chip and a bonding wire. The chip includes a base material, at least one first metallic pad, a re-distribution layer and at least one second metallic pad. The first metallic pad is disposed on the base material. The re-distribution layer has a first end and a second end, and the first end is electrically connected to the first metallic pad. The second metallic pad is electrically connected to the second end of the re-distribution layer. The bonding wire is bonded to the second metallic pad.

Abstract: A semiconductor device includes a semiconductor element having a main surface where an outside connection terminal pad is provided. The semiconductor element is connected to a conductive layer on a supporting board via a plurality of convex-shaped outside connection terminals provided on the outside connection terminal pad and a connection member; and the connection member commonly covers the convex-shaped outside connection terminals.

Abstract: The present invention relates to integrating an inertial mechanical device on top of an IC substrate monolithically using IC-foundry compatible processes. The IC substrate is completed first using standard IC processes. A thick silicon layer is added on top of the IC substrate. A subsequent patterning step defines a mechanical structure for inertial sensing. Finally, the mechanical device is encapsulated by a thick insulating layer at the wafer level. Compared with the incumbent bulk or surface micromachined MEMS inertial sensors, vertically monolithically integrated inertial sensors provided by embodiments of the present invention have one or more of the following advantages: smaller chip size, lower parasitics, higher sensitivity, lower power, and lower cost.

Abstract: A semiconductor device includes a die pad, a semiconductor element which is loaded on the die pad, and a sealing resin. A plurality of electrically conductive portions each having a layered structure including a metal foil comprising copper or a copper alloy, and electrically conductive portion plating layers provided at both upper and lower ends of the metal foil are arranged around the die pad. The die pad has a lower die pad plating layer, and the semiconductor element is loaded on the die pad comprising such a die pad plating layer. Electrodes provided on the semiconductor element are electrically connected with top ends of the electrically conductive portions via wires, respectively. The lower electrically conductive portion plating layers of the electrically conductive portions and the die pad plating layer of the die pad are exposed outside from the sealing resin on their back faces.

Abstract: A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.

Abstract: An under-bump metallization (UBM) structure for a substrate, such as an organic substrate, a ceramic substrate, a silicon or glass interposer, a high density interconnect, a printed circuit board, or the like, is provided. A buffer layer is formed over a contact pad on the substrate such that at least a portion of the contact pad is exposed. A conductor pad is formed within the opening and extends over at least a portion of the buffer layer. The conductor pad may have a uniform thickness and/or a non-planar surface. The substrate may be attached to another substrate and/or a die.

Abstract: A package structure in which a coreless substrate has direct electrical connections to a semiconductor chip and a manufacturing method thereof are disclosed. The method includes the following steps: providing a metal carrier board having a cavity; placing a chip having a plurality of electrode pads on an active surface in the cavity of a board; filling the cavity with an adhesive for fixing the chip; forming a solder mask on the active surface of the chip and the surface of the metal carrier board at the same side, wherein the solder mask has a plurality of openings to expose the electrode pads of the chip; forming a built-up structure on the solder mask and the exposed active surface of the chip in the openings; and removing the metal carrier board. In this method the metal carrier board can support the built-up structure to thereby avoid warpage.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device comprises a semiconductor die including a bond pad, a redistribution layer, and a solder ball. The redistribution layer is formed by sequentially plating copper and nickel, sequentially plating nickel and copper, or sequentially plating copper, nickel, and copper. The redistribution layer includes a nickel layer in order to prevent a crack from occurring in a copper layer. Further, a projection is formed in an area of the redistribution layer or a dielectric layer to which the solder ball is welded and corresponds, so that an area of the redistribution layer to which the solder ball is welded increases, thereby increasing bonding power between the solder ball and the redistribution layer.

Abstract: A package structure and a package substrate thereof are provided. The package structure includes a package substrate, a chip and a molding compound. The package substrate has an upper surface and a lower surface. The lower surface has a molding area and a pad area. The molding area has at least one window opening penetrating the upper surface and the lower surface. The pad area is used for disposing at least one solder ball or at least one connecting pin. The package substrate includes a solder mask. The solder mask covers the lower surface of the package substrate. The solder mask has at least one groove. The groove is disposed between the molding area and the pad area. The chip disposed on the package substrate has an active surface. The active surface contacts with the upper surface of the package substrate. The molding area is covered by the molding compound.

Abstract: Semiconductor dice comprise at least one bond pad on an active surface of the semiconductor die. At least one blind hole extends from a back surface of the semiconductor die opposing the active surface, through a thickness of the semiconductor die, to an underside of the at least one bond pad. At least one quantity of passivation material covers at least a sidewall surface of the at least one blind hole. At least one conductive material is disposed in the at least one blind hole adjacent and in electrical communication with the at least one bond pad and adjacent the at least one quantity of passivation material.

Abstract: A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second semiconductor device spaced apart from the first device, a dielectric layer interposed between the first device and the second device, a first conductive pad positioned in the first device, and a second conductive pad positioned in the second device that capacitively communicate signals from the second device to the first device. In another embodiment, a method of forming a SiP device includes forming a first pad on a surface of a first semiconductor device, forming a second pad on a surface of a second semiconductor device, and interposing a dielectric layer between the first semiconductor device and the second semiconductor device that separates the first conductive signal pad and the second conductive signal pad.

Abstract: A chip holder formed of silicon, glass, other ceramics or other suitable materials includes a plurality of recesses for retaining semiconductor chips. The bond pads of the semiconductor chip are formed on or over an area of the chip holder that surrounds the semiconductor chip thus expanding the bonding area. The bond pads are coupled, using semiconductor wafer processing techniques, to internal bond pads formed directly on the semiconductor chip.

Abstract: A structure of embedded active components and the manufacturing method thereof are provided. The manufacturing steps involve providing a molding plate, and setting several active components on the molding plate as first. A dielectric layer covers the molding plate to cap the active components. An electric circuit is formed on the dielectric layer, in contact with the active components. Finally, the structure with embedded active components is released from the molding plate.

Abstract: A semiconductor memory apparatus includes a first pad group located along a first edge of a plurality of banks, a second pad group located along a second edge of the plurality of banks opposite the first pad group, and a pad control section configured to provide first and second bonding signals and to implement control operation in response to a test mode signal and a bonding option signal to selectively employ signals from the first and second pad groups.

Abstract: An optimized semiconductor chip pad configuration. The pad includes a pad circuit area Ap, a first dimension x and a second dimension y, in a chip having N number of pins on each side. The pins include a longitudinal axis, and the chip includes a chip core of length Lc. The method includes determining the first dimension x by dividing the length Lc by the N, determining the second dimension y by dividing the pad circuit area Ap by a result of a division of the length Lc by the N, and creating a semiconductor area pad that includes pins with the longitudinal axis positioned parallel to the chip core. A stack of circuits is designed in the chip to fit in the pad based on the first dimension x and the second dimension y.

Abstract: In a pad forming region electrically connecting an element forming region to the outside, in which a low dielectric constant insulating film is formed in association with in the element forming region, a Cu film serving as a via formed in the low dielectric constant insulating film in the pad forming region is disposed in higher density than that of a Cu film serving as a via in the element forming region. Hereby, when an internal stress occurs, the stress is prevented from disproportionately concentrating on the via, and deterioration of a function of a wiring caused thereby can be avoided.

Abstract: A semiconductor structure is provided. In one embodiment, a bond pad is formed above one or more underlying layers of a substrate. A plurality of dummy plugs are spaced around the bond pad, the plurality of dummy plugs substantially vertically traversing the one or more underlying layers, wherein the plurality of dummy plugs anchor at least two of the underlying layers together to achieve improved mechanical strength.

Abstract: A chip assembly includes a semiconductor chip and a wirebonded wire. The semiconductor chip includes a passivation layer over a silicon substrate and over a thin metal structure, a first thick metal layer over the passivation layer and on a contact point of the thin metal structure exposed by an opening in the passivation layer, a polymer layer over the passivation layer and on the first thick metal layer, and a second thick metal layer on the polymer layer and on the first thick metal layer exposed by an opening in the polymer layer. The first thick metal layer includes a copper layer with a thickness between 3 and 25 micrometers. The wirebonded wire is bonded to the second thick metal layer.

Abstract: A bump structure with an annular support suitable for being disposed on a substrate is provided. The substrate has at least one pad and a passivation layer that has at least one opening exposing a portion of the pad. The bump structure with the annular support includes an under ball metal (UBM) layer, a bump, and an annular support. The UBM layer is disposed on the passivation layer and covers the pad exposed by the passivation layer. The bump is disposed on the UBM layer over the pad, and a diameter of a lower surface of the bump is less than the diameter of an upper surface thereof. The annular support surrounds and contacts the bump, and a material of the annular support is photoresist. An under cut effect is not apt to happen on the bump structure.

Abstract: A method for fabricating an encapsulant cavity integrated circuit package system includes: forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.

Abstract: A semiconductor device includes a first pad, a second pad and a third pad. The first pad and the third pad are electrically connected to each other. The first pad and the second pad are used for bonding. The second pad and the third pad are used for probing. According to this structure, Small size semiconductor device having high reliability even after a probing test can be provided.

Abstract: This invention provides a semiconductor device. The semiconductor device includes a bonding pad array comprising: a signal bonding pad, a control pin bonding pad and at least one stacking bonding pad on an active surface. At least one stacking bonding pad is adjacent to the control pin bonding pad. This invention also provides a stacked structure of semiconductor devices and/or a semiconductor device package including the semiconductor device.

Abstract: A semiconductor device having pads is provided. The semiconductor device includes first pads formed along a first row, and second pads formed along a second row. The first via contact portions extending from the first pads toward the second row, and second via contact portions extending from the second pads toward the first row. The first and second via contact portions are arranged along a third row between the first and second rows.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: According to an aspect of the present invention, there is provided a semiconductor device, including a semiconductor chip including a first electrode and a second electrode of a semiconductor element, the first electrode and the second electrode being configured on a first surface and a second surface of the semiconductor chip, an encapsulating material encapsulating the semiconductor chip, the surface portion being other than regions, each of the regions connecting with the first second electrodes, each of inner electrodes being connected with the first or the second electrodes, a thickness of the inner electrode from the first surface or the second surface being the same thickness as the encapsulating material from the first surface or the second surface, respectively, outer electrodes, each of the outer electrodes being formed on the encapsulating material and connected with the inner electrode, a width of the outer electrode being at least wider than a width of the semiconductor chip, and outer plating ma

Abstract: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Abstract: The present invention provides a technique capable of suppressing variations in the height of each solder ball where an NSMD is used as a structure for each land. Vias that extend through a wiring board are provided. Lands are formed at the back surface of the wiring board so as to be coupled directly to the vias respectively. The lands are respectively formed so as to be internally included in openings defined in a solder resist. Half balls are mounted over the lands respectively. Namely, the present invention has a feature in that the configuration of coupling between each of the lands and its corresponding via both formed at the back surface of the wiring board is taken as a land on via structure and a configuration form of each land is taken as an NSMD.

Abstract: Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.

Abstract: A semiconductor package includes a semiconductor chip including a body unit having one or more circuit units. A first bonding pad is disposed in a first face of the body unit and is connected to a circuit unit. A second bonding pad is disposed in the first face of the body unit in the bonding pad region so as to be positioned in an adjacent surrounding area of the first bonding pad and borders at least one side face of the first bonding pad while being insulated from the first bonding pad. A first connection terminal is attached onto the first bonding pad, and a second connection terminal is attached onto the second bonding pad and is positioned in an adjacent surrounding area of the first connection terminal and borders at least one side face of the first connection terminal while being insulated from the first connection terminal.

Abstract: A substrate includes a substrate; a number of pad redistribution chips stacked on the substrate and on one another after being rotated 90° in a predetermined direction relative to one another, the pad redistribution chips having a number of center pads positioned at the center thereof, a number of (+) edge pads positioned on an end thereof while corresponding to those of the center pads lying in (+) direction from a middle center pad located in the middle of the center pads, a number of (?) edge pads positioned on the other end thereof while corresponding to those of the center pads lying in (?) direction with symmetry to those of the center pads lying in the (+) direction, and a number of traces for electrically connecting the center pads to the corresponding (±) edge pads, respectively; a flexible PCB for electrically connecting the substrate to the pad redistribution chips; and an anisotropic dielectric film for electrically connecting the pad redistribution chips to the flexible PCB and the substrate to t

Abstract: A method of manufacture of a leadless integrated circuit packaging system includes: providing a substrate; patterning a die attach pad on the substrate; forming a tiered plated pad array around the die attach pad; mounting an integrated circuit die on the die attach pad; coupling an electrical interconnect between the integrated circuit die and the tiered plated pad array; forming a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array; and exposing a contact pad layer by removing the substrate.

Abstract: An integrated circuit structure includes a semiconductor chip having a first region and a second region; a dielectric layer formed on the first region and the second region of the semiconductor chip; a first elongated under-bump metallization (UBM) connector formed in the dielectric layer and on the first region of the semiconductor chip and having a first longer axis extending in a first direction; and a second elongated UBM connector formed in the dielectric layer on the second region of the semiconductor chip and having a second longer axis extending in a second direction. The first direction is different from the second direction.

Abstract: A semiconductor package includes a semiconductor substrate a semiconductor substrate having source and drain regions formed therein, an intermediate routing structure to provide electrical interconnects to the source and drain regions, a dielectric layer formed over the intermediate routing structure, and an under-bump-metallization (UBM) stack. The intermediate routing structure includes an outermost conductive layer, and the dielectric layer has an opening positioned over a portion of the intermediate layer routing structure. The UBM stack includes a conductive base layer formed over the dielectric layer and electrically connected to the outermost conductive layer through the opening, and a thick conductive layer formed on the base layer. A conductive bump is positioned on the UBM stack and laterally spaced from the opening.

Abstract: An integrated circuit packaging system includes: attaching a carrier, having a carrier top side and a carrier bottom side, and an interconnect without an active device attached to the carrier bottom side; and forming a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation and with the carrier top side partially exposed with the cavity.

Abstract: A bonding pad includes multiple metal layers, insulation layers disposed between the multiple metal layers, and a fixing pin coupled between the uppermost metal layer and an underlying metal layer of the multiple metal layers, where a bonding is performed on the uppermost metal layers.

Abstract: A system and method is disclosed that prevents the formation of a vertical bird's beak structure in the manufacture of a semiconductor device. A polysilicon filled trench is formed in a substrate of the semiconductor device. One or more composite layers are then applied over the trench and the substrate. A mask and etch process is then applied to etch the composite layers adjacent to the polysilicon filled trench. A field oxide process is applied to form field oxide portions in the substrate adjacent to the trench. Because no field oxide is placed over the trench there is no formation of a vertical bird's beak structure. A gate oxide layer is applied and a protection cap is formed over the polysilicon filled trench to protect the trench from unwanted effects of subsequent processing steps.

Abstract: A semiconductor package and a method for making the same, whereby the semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, and second and third metal layers. The substrate has a surface having at least first and second pads. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer.

Abstract: A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation layer on the first pad, the inter-connection line, and the second pad; exposing the first and second pads by patterning the etch-stop layer and the first insulation layer; forming third and fourth pads including a second metal on the first and second pads; sequentially forming second and third insulation layers on the third pad, the fourth pad, and the patterned first insulation layer; and etching the first, second, and third insulation layers using the patterned photosensitive layer on the third insulation layer to expose the third and fourth pads.

Abstract: An article including a substrate having a blind hole formed therein, wherein the blind hole is defined by a floor and a sidewall and a solder connection is provided. The solder connection may couple a first contact pad to a second contact pad. The first contact pad may cover a first field of the floor of the blind hole, and may also promote wetting of a solder material of the solder connection. Wetting may be impeded on a second field of the floor of the blind hole. The second contact pad may be arranged above a surface of a further substrate, wherein the surface of the further substrate may be oriented perpendicularly to the floor of the blind hole in the substrate.

Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

Abstract: An integrated circuit device includes a receiving circuit, a transmission circuit, and common pads common to the receiving circuit and the transmission circuit, which are disposed in such a way that the distance between the receiving circuit and the common pad, and the distance between the transmission circuit and the common pad become shorter, respectively.

Abstract: A process comprises manufacturing an electromigration-resistant under-bump metallization (UBM) flip chip structure comprising a Cu layer by applying to the Cu layer a metallic reaction barrier layer comprising NiFe. The solder employed in the flip chip structure comprise substantially lead-free tin. A structure comprises a product produced by this process. In another embodiment a process comprises manufacturing an electromigration-resistant UBM Sn-rich Pb-free solder bump flip chip structure wherein the electromigration-resistant UBM structure comprises a four-layer structure, or a three-layer structure, wherein the four layer structure is formed by providing 1) an adhesion layer, 2) a Cu seed layer for plating, 3) a reaction barrier layer, and 4) a wettable layer for joining to the solder, and the three-layer structure is formed by providing 1) an adhesion layer, 2) a reaction barrier layer, and 3) a wettable layer.

Abstract: A manufacturing method of a bump structure having a reinforcement member is disclosed. First, a substrate including pads and a passivation layer is provided. The passivation layer has first openings, and each first opening exposes a portion of the corresponding pad respectively. Next, an under ball metal (UBM) material layer is formed on the substrate to cover the passivation layer and the pads exposed by the passivation layer. Bumps are formed on the UBM material layer and the lower surface of each bump is smaller than that of the opening. Each reinforcement member formed on the UBM material layer around each bump contacts with each bump, and the material of the reinforcement member is a polymer. The UBM material layer is patterned to form UBM layers and the lower surface of each UBM layer is larger than that of each corresponding opening. Hence, the bump has a planar upper surface.

Abstract: The present invention discloses a metallization layer structure for flip chip package, which comprises an UBM layer formed on a metal pad, whereby a fine-quality tin-based solder ball can be formed on the metal pad. The UBM layer is a NiZnP layer formed via the reduction and oxidization of a solution containing nickel sulfate (Ni2SO4), zinc sulfate (ZnSO4), sodium dihydrogen phosphite (NaH2PO2), sodium citrate dihydrate (Na3C6H5O7-2H2O), and ammonium chloride (NH4Cl). The present invention replaces the conventional Au/Ni—P dual-layer structure. Therefore, the present invention can decrease the complexity of the process and reduce the cost. Further, the metallization layer structure of the present invention is tough, hard to peel off and highly corrosion-resistant.

Abstract: In a semiconductor package, at least two of connection pads are formed into different-shape pads which are different in planar shape from other connection pads, and one different-shape pad and another different-shape pad are disposed in a manner that, when the position of the one different-shape pad is rotated about the center point of the semiconductor package, the position does not coincide with the disposition position of the other different-shape pad.

Abstract: A semiconductor device includes an insulating film formed on a substrate; an interconnect layer including a plurality of interconnects formed in the insulating film; and a pad formed on the insulating film. In a region containing at least a part of a section below the pad, a narrow spacing region is formed, where a spacing between the adjacent interconnects is shorter than that in a section outside the region containing at least a part of the section below the pad.

Abstract: A method of securing a bond pad in to a semiconductor chip having an upper top metal surface which includes one or more holes, the method comprising the steps of forming a passivation layer over the upper metal surface, which passivation layer has holes therein substantially corresponding to the or each hole in the upper metal layer and being substantially the same size or smaller than the holes in the upper metal layer; forming the bond pad over the passivation layer; characterised in that the step of forming the bond pad comprises introducing some of the material from the bond pad into the holes in the passivation layer and upper metal layer when forming the bond pad, securing the bond pad to the passivation layer by allowing said material to flow under the surface thereof and attach thereto without attaching to the upper metal layer to thereby form a securing means.

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.