Additional Leads Being Tape Carrier Or Flat Leads (epo) Patents (Class 257/E23.034)
  • Patent number: 10586771
    Abstract: A conductive polymer shielding layer covering insulating layer formed on an integrated-circuit die is provided and a method thereof. The method comprises die attaching, wire bonding, back etching, insulation molding, partial cutting, conductive material/polymer coating, and singulation.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: March 10, 2020
    Assignee: UTAC HEADQUARTERS PTE, LTD
    Inventors: Saravuth Sirinorakul, Somchai Nondhasitthichail
  • Patent number: 9583421
    Abstract: Leadframes for semiconductor packages. Implementations may include a plurality of leads extending inwardly into an opening surrounded by the plurality of leads where the plurality of leads except for at least one are configured to mechanically couple at a surface of a semiconductor chip. The at least one of the plurality of leads that is not configured to mechanically coupled at the surface of the semiconductor chip be configured to electrically couple with the semiconductor chip.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: February 28, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Francois Ricodeau
  • Patent number: 9029991
    Abstract: An example semiconductor package with reduced solder voiding is described, which has a leadframe having an I/O pad and a thermal pad, a fabricated semiconductor die having a bond pad, where the fabricated semiconductor die is attached to a top surface of the thermal pad, and a wire bond connecting the bond pad to the I/O pad, where a bottom surface of the thermal pad has channels.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: May 12, 2015
    Assignee: Conexant Systems, Inc.
    Inventors: Robert W. Warren, Hyun Jung Lee, Nic Rossi
  • Patent number: 8975738
    Abstract: A structure may include a spacer element overlying a first portion of a first surface of a substrate; first terminals at a second surface of the substrate opposite the first surface; and second terminals overlying a third surface of the spacer element facing away from the first surface. Traces extend from the second terminals along an edge surface of the spacer element that extends from the third surface towards the first surface, and may be electrically coupled between the second terminals and the first terminals or electrically conductive elements at the first surface. The spacer element may at least partially define a second portion of the first surface, which is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some of the conductive elements are at the second portion and may permit connection with such microelectronic element.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: March 10, 2015
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 8952510
    Abstract: A semiconductor chip for a TAB package includes a surface including a set of input pads connected to internal circuitry of the chip and for receiving external signals The surface includes output pads. A plurality of input pads are adjacent a first edge and are in a first row substantially parallel to the first edge and extending in a first direction; a plurality of first output pads are adjacent a second edge, and are in a second row substantially parallel to the second edge and extending in the first direction; and a plurality of second output pads are located between the first row and the second row. The plurality of second output pads include first and second outermost pads located a certain distance from a respective third edge and fourth edge, and first and second inner pads located a greater distance from the respective third edge and fourth edge.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sang Cho, Chang-Sig Kang, Dae-Woo Son, Yun-Seok Choi, Kyong-Soon Cho, Sang-Heui Lee
  • Patent number: 8853694
    Abstract: Provided are a chip on film (COF) package and semiconductor having the same. The COF package can include a flexible film having first and second surfaces opposite to and facing each other and including a conductive via penetrating from the first surface to the second surface, first and second conductive patterns respectively is on the first surface and the second surface and electrically connected to each other through the conductive via, an integrated circuit (IC) chip is on the first surface and electrically connected to the first conductive pattern, a test pad overlaps the conductive via and is electrically connected to at least one of the first conductive pattern and the second conductive pattern, and an external connection pattern is on the second surface spaced apart from the conductive via and electrically connected to the second conductive pattern.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Uk Han, Jeong-Kyu Ha, Young-Shin Kwon, Seung-Hwan Kim, Kwan-Jai Lee
  • Patent number: 8810017
    Abstract: A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: August 19, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Dioscoro A. Merilo, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Patent number: 8791556
    Abstract: An integrated circuit packaging system, and a method of manufacture therefor, including: electrical terminals; circuitry protective material around the electrical terminals and formed to have recessed pad volumes; routable circuitry on the top surface of the circuitry protective material; and an integrated circuit die electrically connected to the electrical terminals.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: July 29, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8785299
    Abstract: An embodiment is a device comprising a semiconductor die, an adhesive layer on a first side of the semiconductor die, and a molding compound surrounding the semiconductor die and the adhesive layer, wherein the molding compound is at a same level as the adhesive layer. The device further comprises a first post-passivation interconnect (PPI) electrically coupled to a second side of the semiconductor die, and a first connector electrically coupled to the first PPI, wherein the first connector is over and aligned to the molding compound.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Mao, Chin-Chuan Chang, Jui-Pin Hung, Jing-Cheng Lin
  • Publication number: 20140131842
    Abstract: An axially-mountable device includes a semiconductor chip comprising lower and upper electrical contacts. A lower die pad is electrically and mechanically connected to the lower electrical contact of the chip. An upper die pad is electrically and mechanically connected to the upper electrical contact of the chip. A first axially extending electrical lead is electrically and mechanically connected to the upper die pad and extends in a first axial direction. A second axially extending electrical lead is electrically and mechanically connected to the lower die pad and extends in a second axial direction that is opposite to the first axial direction. Packaging material encapsulates the semiconductor chip, the upper and lower die pads and a portion of the first and second axially extending leads. The first and second leads extend from the packaging material and are adapted to allow the device to be axially-mounted with another electrical component.
    Type: Application
    Filed: November 10, 2012
    Publication date: May 15, 2014
    Applicant: Vishay General Semiconductor LLC
    Inventors: Wan-Lan Chiang, Chih-Ping Peng, Hui-Ying Ding
  • Patent number: 8629537
    Abstract: An integrated circuit package system is provided forming a die support system from a padless lead frame having die supports with each substantially equally spaced from another, and attaching an integrated circuit die having a peripheral area on the die supports.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: January 14, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Patent number: 8618642
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 31, 2013
    Assignees: Renesas Electronics Corporation, Hitachi Hokkai Semiconductor Ltd.
    Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
  • Patent number: 8581378
    Abstract: Terminals (2b, 2c) are divided into two along a common boundary, coatings (10, 11) most suitable for two conductive bonding materials (5, 6) to be used are exposed on the terminals (2b, 2c), the most suitable one of the coatings (10, 11) is selected, and the corresponding conductive bonding material (5, 6) is bonded onto the coating. Thus it is possible to improve the reliability of bonding and easily reduce a bonding resistance while suppressing a decrease in the reliability of a semiconductor element 3.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: November 12, 2013
    Assignee: Panasonic Corporation
    Inventors: Toshiyuki Yokoe, Chie Fujioka, Daichi Kumano
  • Patent number: 8575735
    Abstract: A semiconductor chip for a tape automated bonding (TAB) package is disclosed. The semiconductor chip comprises a connection surface including a set of input pads connected to internal circuitry of the chip and for conveying external signals to the internal circuitry, the set of input pads comprising all of the input pads on the chip. The connection surface includes a set of output pads connected to internal circuitry of the chip and for conveying internal chip signals to outside the chip, the set of output pads comprising all of the output pads on the chip.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: November 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sang Cho, Chang-Sig Kang, Dae-Woo Son, Yun-Seok Choi, Kyong-Soon Cho, Sang-Heul Lee
  • Patent number: 8525313
    Abstract: A chip assembly includes a chip, a paddle, an interface layer, a frequency extending device, and lands. The chip has contacts. The interface layer is disposed between the chip and the paddle. The frequency extending device has at least a conductive layer and a dielectric layer. The conductive layer has conductive traces. The frequency extending device is disposed adjacent to the side of the chip and overlying the paddle. The lands are disposed adjacent to the side of the paddle. The contacts are connected to the conductive traces. The conductive traces are connected to the lands. The frequency extending device is configured to reduce impedance discontinuity such that the impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by bond wires each having a length greater than or substantially equal to the distance between the contacts and the lands.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: September 3, 2013
    Assignee: Semtech Corporation
    Inventors: Binneg Y. Lao, William W. Chen
  • Patent number: 8525305
    Abstract: A lead carrier provides support for an integrated circuit chip and associated leads during manufacture as packages containing such chips. The lead carrier includes a temporary support member with multiple package sites. Each package site includes a die attach pad surrounded by a plurality of terminal pads. The pads are formed of a sintered electrically conductive material. A chip is mounted upon the die attach pad and wire bonds extend from the chip to the terminal pads. The pads, chip and wire bonds are all encapsulated within a mold compound. The temporary support member can be peeled away and then the individual package sites can be isolated from each other to provide completed packages including multiple surface mount joints for mounting within an electronics system board. Edges of the pads are contoured to cause the pads to engage with the mold compound to securely hold the pads within the package.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: September 3, 2013
    Assignee: EoPlex Limited
    Inventor: Philip E. Rogren
  • Patent number: 8426980
    Abstract: A chip-to-chip multi-signaling communication system with common conductive layer, which comprises a first chip, a second chip, and a common conductive layer, is disclosed. The first chip has at least a first metal pad and a second metal pad. The second chip has at least a first metal pad and a second metal pad. The common conductive layer is to a conductive material and glued directly to the first chip and the second chip. Wherein, the first metal pad of the second chip is aligned with the first metal pad of the first chip for receiving the signal from the first metal pad of the first chip through the common conductive layer. The interference generated by other pads of the first and the second chips is suppressed by the design of the pads and the common conductive layer.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: April 23, 2013
    Assignee: National Chiao Tung University
    Inventors: Chau-Chin Su, Ying-Chieh Ho, Po-Hsiang Huang
  • Publication number: 20120168920
    Abstract: A leadless semiconductor package includes a package body on a leadframe that includes a die paddle and a plurality of bond pads, none of which extend as far as a lateral face of the body. During manufacture of the package, molding compound is deposited over a face of the leadframe on which the die paddle and bond pads are positioned. After the molding compound is cured, a back side of the leadframe is etched to isolate the die paddle and bond pads, back surfaces of which remain exposed at a back face of the body. During manufacture of the leadframe, a parent substrate is etched to define the die paddle and a plurality of bond pads on one side of the substrate and a plurality of cavities on the opposite face.
    Type: Application
    Filed: December 30, 2010
    Publication date: July 5, 2012
    Applicant: STMICROELECTRONICS, INC.
    Inventors: Jerry Tan, William Cabreros
  • Publication number: 20120168921
    Abstract: A leadless semiconductor package includes a package body on a leadframe that includes a die paddle and a plurality of high-aspect-ratio leads, each coupled at a first end to a contact pad of the package, and at a second end to a semiconductor die mounted to the die paddle. During manufacture of the package, molding compound is deposited over a face of the leadframe on which the die paddle and leads are positioned. After the molding compound is cured, a back side of the leadframe is etched to isolate the die paddle and leads, and to thin a portion of each of the leads. Back surfaces of the leads remain exposed at a back face of the body. The thinned portions of the leads are covered with a dielectric. During manufacture of the leadframe, a parent substrate is etched to define the die paddle and a plurality of leads on one side of the substrate and a plurality of cavities on the opposite face.
    Type: Application
    Filed: December 30, 2010
    Publication date: July 5, 2012
    Applicant: STMICROELECTRONICS, INC.
    Inventors: Jerry Tan, William Cabreros
  • Patent number: 8212342
    Abstract: A method of manufacture of an integrated circuit package system includes providing a first frame having a first removable backing element connecting a first die attach pad and a first plurality of terminal leads. A first die is attached to the first die attach pad. A substrate is provided. A second die is attached to the substrate. The first die is attached to the second die with a plurality of die interconnects. The first removable backing element is removed after connecting the first die to the second die.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: July 3, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Dioscoro A. Merilo, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Patent number: 8193622
    Abstract: A semiconductor die package is disclosed. The semiconductor die package includes a semiconductor die comprising an input at a first top semiconductor die surface and an output at a second bottom semiconductor die surface. A leadframe having a first leadframe surface and a second leadframe surface opposite the first leadframe surface is in the semiconductor die package and is coupled to the first top semiconductor die surface. A clip having a first clip surface and a second clip surface is coupled to the second bottom semiconductor die surface. A molding material having exterior molding material surfaces covers at least a portion of the leadframe, the clip, and the semiconductor die. The first leadframe surface and the first clip surface are exposed by the molding material, and the first leadframe surface, the first clip surface, and the exterior molding material surfaces of the molding material form exterior surfaces of the semiconductor die package.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: June 5, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Ruben P. Madrid
  • Patent number: 8188596
    Abstract: A multi-chip module is disclosed. In one embodiment, the multichip module includes a first chip, a second chip and a common chip carrier is disclosed. The first chip and the second chip are mounted on the common chip carrier. The second chip is mounted on the chip carrier in a flip-chip orientation. The second chip is electrically connected to the first chip via the chip carrier.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: May 29, 2012
    Assignee: Infineon Technologies AG
    Inventor: Ralf Otremba
  • Patent number: 8063470
    Abstract: A leadframe for use in fabricating a no lead semiconductor package contains connecting bars between individual electrical contact pads. For embodiments having a die pad, the leadframe further includes connecting bars between the contact pads and the die pad. The lower surfaces of the connecting bars are coplanar with the lower surfaces of the contact pads and/or the die pad, and the upper surfaces of the connecting bars are recessed with respect to the upper surfaces of the contact pads and/or the die pad. The semiconductor package is fabricated by encapsulating the die and the leadframe in a molding compound and then removing the connecting bars. The leadframe is typically formed by half etching a metal sheet to form the connecting bars. The connecting bars are removed from the encapsulated package by a selected cutting, sawing, or etching means, based on a predetermined pattern.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: November 22, 2011
    Assignee: Utac Thai Limited
    Inventors: Saravuth Sirinorakul, Somchai Nondhasitthichai
  • Patent number: 8030766
    Abstract: A semiconductor device that can cope with larger numbers of pins and finer pitches while suppressing lowering of the manufacturing yield and reliability includes: a semiconductor chip having a plurality of electrodes provided on an upper surface thereof; a plurality of lead terminals including inner lead portions disposed toward the semiconductor chip; a sheet-form wiring member having a plurality of conductors insulated from one another on one main surface thereof; and a sealing-resin layer for sealing at least the semiconductor chip, the inner lead portions and the wiring member. The electrodes of the semiconductor device and the inner lead portions of the lead terminals are electrically connected respectively to each other via the conductors of the wiring member.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: October 4, 2011
    Assignee: Rohm Co., Ltd.
    Inventor: Akihiko Tadaoka
  • Patent number: 8022517
    Abstract: A semiconductor chip package includes a lead frame, an insulation member, a chip, bonding wires and a sealing member. The lead frame includes a plurality of first leads and a plurality of second leads. The second leads have a chip adhesion region. The insulation member fills a space between the second leads in the chip adhesion region. The chip is provided on at least one surface of the insulation member. The chip has single-side bonding pads. The bonding wires electrically connect the leads and the bonding pads. The sealing member covers the lead frame, the insulation member, the chip and the bonding wires. Since the space between the second leads is filled with the insulation member, voids may be prevented from occurring.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: September 20, 2011
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Sung-Hwan Yoon, Sang-Wook Park, Min-Young Son
  • Publication number: 20110169148
    Abstract: A tape wiring substrate may have dispersion wiring patterns. The dispersion wiring patterns may be provided between input/output wiring pattern groups to compensate for the intervals therebetween. Connecting wiring patterns may be configured to connect the dispersion wiring patterns to a first end of the adjacent input/output wiring pattern.
    Type: Application
    Filed: March 23, 2011
    Publication date: July 14, 2011
    Inventor: Dong-Han Kim
  • Patent number: 7928543
    Abstract: A tape wiring substrate may have dispersion wiring patterns. The dispersion wiring patterns may be provided between input/output wiring pattern groups to compensate for the intervals therebetween. Connecting wiring patterns may be configured to connect the dispersion wiring patterns to a first end of the adjacent input/output wiring pattern.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: April 19, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Han Kim
  • Patent number: 7902647
    Abstract: A device is provided in which a glass panel having beveled edge is flexibly connected to a TAB package. The outer lead portions of the TAB package include an end portion of first width connected to a connection pattern on the glass panel, a terminal portion having a second width greater than the first width, and a transition portion having a width that varies between the first and second widths. When the TAB package is connected the transition portion of the respective outer lead portions are disposed over the beveled edge of the glass panel.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: March 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ye-chung Chung, Sa-yoon Kang
  • Patent number: 7880280
    Abstract: An electronic component has at least two semiconductor devices, a contact clip and a leadframe with a device carrier portion and a plurality of leads. The contact clip extends between the first side of at least two semiconductor devices and at least one lead of the leadframe to electrically connect a load electrode of the at least two semiconductor devices to at least one lead.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: February 1, 2011
    Assignee: Infineon Technologies AG
    Inventor: Ralf Otremba
  • Patent number: 7872345
    Abstract: An integrated circuit package system includes: providing a protective layer having an opening; forming a conductive layer over the protective layer and filling the opening; patterning a rigid locking lead, having both a lead locking portion and a lead exposed portion, from the conductive layer; connecting an integrated circuit and the rigid locking lead; and forming an encapsulation over the integrated circuit with the lead locking portion in the encapsulation and the lead exposed portion exposed from the encapsulation.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: January 18, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Linda Pei Ee Chua, Heap Hoe Kuan
  • Patent number: 7851896
    Abstract: A Quad Flat Non-leaded (QFN) chip package including a patterned conductive layer, a first solder resist layer, a chip, a plurality of bonding wires and a molding compound is provided. The patterned conductive layer has a first surface and a second surface opposite to each other. The first solder resist layer is disposed on the first surface, wherein a part of the first surface is exposed by the first solder resist layer. The chip is disposed on the first solder resist layer, wherein the first solder resist layer is between the patterned conductive layer and the chip. The bonding wires are electrically connected to the chip and the patterned conductive layer exposed by the first solder resist layer. The molding compound encapsulates the pattern conductive layer, the first solder resist layer, the chip and the bonding wires.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: December 14, 2010
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Geng-Shin Shen, Chun-Ying Lin, Shih-Wen Chou
  • Patent number: 7847380
    Abstract: Provided are a tape substrate for a smart card, a method of fabricating the same, and a semiconductor module and a smart card using the tape substrate. The tape substrate includes at least one tape unit. The at least one tape unit includes a chip mounting unit defining a region on which a semiconductor chip is to be mounted, a plurality of pin electrode units arranged around the chip mounting unit and separated from one another, a border unit encircling the chip mounting unit and the pin electrode units, and a cutting unit disposed between the chip mounting unit and the border unit and between the pin electrode units and the border unit. The cutting unit includes a plurality of connection lines connecting the chip mounting unit and the pin electrode units to the border unit.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: December 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yucai Huang
  • Patent number: 7821115
    Abstract: A semiconductor device on a tape carrier package with improved heat dissipation, as provided. The number of outputs of the semiconductor device has been increased for implementing a multi-channel configuration, and narrower pitches are employed. Included are a tape carrier 20 having lead patterns 21 to 24 formed on a tape base 28 thereof, and a semiconductor device 10 mounted on the tape carrier 20 and having electrode patterns 11 to 14 disposed thereon. The semiconductor device 10 includes heat dissipating electrode patterns 15 to 17 at positions where the heat dissipating electrode patterns 15 to 17 do not interfere with the electrode patterns 11 to 14. The lead patterns 21 to 24 are electrically connected to the corresponding electrode patterns 11 to 14, respectively. On the tape carrier 20, heat dissipation patterns 25 to 27 are formed. The heat dissipation patterns have a surface area broader than that of the lead patterns and have the heat dissipating electrode patterns disposed thereon.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Chihiro Sasaki, Yasuaki Iwata
  • Patent number: 7821124
    Abstract: Semiconductor die packages and methods of making them are disclosed. An exemplary package comprises a leadframe having a source lead and a gate lead, and a semiconductor die coupled to the source and gate leads at a first surface of the leadframe. The source lead has a protruding region at a second surface of the leadframe. A molding material is disposed around the semiconductor die, the gate lead, and the source lead such that a surface of the die and a surface of the protruding region are left exposed by the molding material. An exemplary method comprises obtaining the semiconductor die and leadframe, and forming a molding material around at least a portion of the leadframe and die such that a surface of the protruding region is exposed through the molding material.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: October 26, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Rajeev Joshi, Chung-Lin Wu
  • Patent number: 7804160
    Abstract: An ultrasonic bonding equipment for manufacturing a semiconductor device comprises a tip portion. The tip portion has a top surface which is faced to a member to be bonded, and propagates an ultrasonic vibration to the top surface. A plurality of protruding portions are provided on the top surface. Each of the protruding portions has: a first pair of opposite side surfaces inclined with respect to the top surface; and a second pair of opposite side surfaces substantially vertical to the top surface. A semiconductor device comprises: a semiconductor chip; a lead; and a bonding strap electrically connecting the semiconductor chip and the lead. A recess is formed on an upper surface of the bonding strap in at least one of a first region where the bonding strap and the semiconductor chip are connected and a second region where the bonding strap and the lead is connected.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: September 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masataka Nanba, Shigeru Tanabe
  • Patent number: 7795071
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: September 14, 2010
    Assignee: Advanpack Solutions Pte Ltd.
    Inventors: Chew Hwee-Seng Jimmy, Ong Chee Kian, Abd. Razak Bin Chichik
  • Patent number: 7786575
    Abstract: A stacked die semiconductor package includes a first integrated circuit chip, a first circuit tape coupled to the first integrated circuit chip, a second integrated circuit chip coupled to the first circuit tape, and at least one component coupled to the first circuit tape. The at least one component may include one or more passive components, one or more active components, or a combination of passive and active components. The stacked die semiconductor package can also include a second circuit tape coupled to the second integrated circuit chip and a third integrated circuit chip coupled to the second circuit tape. The stacked die semiconductor package can also include an encapsulant.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: August 31, 2010
    Assignee: STATS ChipPAC Ltd.
    Inventors: Philip Lyndon R. Cablao, Dario S. Filoteo, Jr., Emmanuel A. Espiritu, Leo A. Merilo
  • Patent number: 7745929
    Abstract: A semiconductor device (1) has a semiconductor component (2), a first electrode (6) and a control electrode (7) being arranged on the top side (4). The semiconductor device (1) furthermore has a circuit carrier (3) having a chip island (9) and a plurality of flat conductors (10). The rear side (5) of the semiconductor component (2) is mounted on the chip island (9). The first electrode (6) is electrically connected to a first flat conductor (13) via a first contact clip (16) and the control electrode (7) is electrically connected to a control flat conductor (14) via the second contact clip (19). The upper surface (33) of the first contact clip (16) is at least partly arranged in a plane which is further away from the top side (4) of the semiconductor component (2) than the entire upper surface (34) of the second contact clip (19).
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: June 29, 2010
    Assignee: Infineon Technologies AG
    Inventor: Ralf Otremba
  • Patent number: 7719027
    Abstract: The present invention provides an integrated circuit and the method of implementing the same. The integrated circuit includes a die, a base, a covering material and a plurality of pins. The die has at least a first function and a second function and includes a plurality of signal pads and at least a switching pad. The die receives and outputs signals through the signal pads, and the switching pad is utilized to switch the functions of the die. The base is utilized to support the die, and the covering material is utilized to cover the die and the base. One terminal of each pin is inside the covering material and coupled to the corresponding signal pad, and the other terminal of each pin is outside the covering material. The signal pads are connected to the circuits outside the integrate circuit through the pins.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: May 18, 2010
    Assignee: MStar Semiconductor, Inc.
    Inventor: ShouFang Chen
  • Patent number: 7709947
    Abstract: The first external electrode has a main body portion a part of which is buried in a side wall of a case and joining portions protruding from an end of the main body portion toward the inside of the case. Each joining portion of the first external electrode is formed to have a thickness smaller than that of the main body portion, and an end portion of each joining portion is directly joined onto a wiring pattern of the insulating substrate through ultrasonic joining. Therefore, a load and ultrasonic vibration necessary for joining the joining portion onto the wiring pattern can be suppressed, which makes it possible to directly join the first external electrode onto the wiring pattern of the insulating substrate without damaging an insulating member of the insulating substrate.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: May 4, 2010
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventor: Jun Ishikawa
  • Patent number: 7696014
    Abstract: A method for breaking an adhesive film mounted on the back of a wafer having a plurality of streets formed in a lattice pattern on the face of the wafer, and having devices formed in a plurality of regions demarcated by the plurality of streets, the devices being divided individually, is adapted to break the adhesive film along the outer peripheral edges of the individual devices, with the adhesive film being stuck to the surface of a dicing tape mounted on an annular frame. The method comprises: a laser processing step of projecting a laser beam with a pulse width of 100 picoseconds or less onto the adhesive film through gaps between the individually divided devices to form deteriorated layers in the adhesive film along the outer peripheral edges of the individual devices; and an adhesive film breaking step of exerting external force on the adhesive film having the deteriorated layers formed therein, to break the adhesive film along the deteriorated layers.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: April 13, 2010
    Assignee: Disco Corporation
    Inventors: Nobuyasu Kitahara, Yuki Ogawa
  • Patent number: 7679173
    Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: March 16, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tomoaki Uno, Nobuyoshi Matsuura, Yukihiro Sato, Keiichi Okawa, Tetsuya Kawashima, Kisho Ashida
  • Publication number: 20100059875
    Abstract: The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7D2, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.
    Type: Application
    Filed: June 8, 2009
    Publication date: March 11, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Yukihiro Sato, Tomoaki Uno
  • Patent number: 7663211
    Abstract: An integrated power device module having a leadframe structure with first and second spaced pads and one or more common source-drain leads located between said first and second pads, first and second transistors flip chip attached respectively to said first and second pads, wherein the source of said second transistor is electrically connected to said one or more common source-drain leads, and a first clip attached to the drain of said first transistor and electrically connected to said one or more common source-drain leads. In another embodiment a partially encapsulated power quad flat no-lead package having an exposed top thermal drain clip which is substantially perpendicular to said with a folded stud exposed top thermal drain clip, and an exposed thermal source pad.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: February 16, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jonathan A. Noquil, Ruben Madrid
  • Patent number: 7659608
    Abstract: A stacked die semiconductor package includes a first integrated circuit chip, a first circuit tape coupled to the first integrated circuit chip, a second integrated circuit chip coupled to the first circuit tape, and at least one component coupled to the first circuit tape. The at least one component may include one or more passive components, one or more active components, or a combination of passive and active components. The stacked die semiconductor package can also include a second circuit tape coupled to the second integrated circuit chip and a third integrated circuit chip coupled to the second circuit tape. The stacked die semiconductor package can also include an encapsulant.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: February 9, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Philip Lyndon R. Cablao, Dario S. Filoteo, Jr., Emmanuel A. Espiritu, Leo A. Merilo
  • Patent number: 7649246
    Abstract: A device is provided in which a glass panel having beveled edge is flexibly connected to a TAB package. The outer lead portions of the TAB package include an end portion of first width connected to a connection pattern on the glass panel, a terminal portion having a second width greater than the first width, and a transition portion having a width that varies between the first and second widths. When the TAB package is connected the transition portion of the respective outer lead portions are disposed over the beveled edge of the glass panel.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: January 19, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ye-chung Chung, Sa-yoon Kang
  • Patent number: 7638863
    Abstract: In one embodiment, a semiconductor package is formed to include a tamper barrier that is positioned between at least a portion of the connection terminals of the semiconductor package and an edge of the semiconductor package.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: December 29, 2009
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Phillip Celaya, James P. Letterman, Jr.
  • Patent number: 7626255
    Abstract: Provided is a device, an assembly comprising said device, a sub-assembly and an element suitable for use in the assembly. The device comprises a body of an electrically insulating material having a first side and an opposite second side, the body being provided with conductors according to a desired pattern, said conductors being anchored in the body. The body is provided with a through-hole extending from the first side to the second side of the body and having a surfacial area which is smaller on the first side than on the second side. Such a device can very suitably be used in an assembly comprising an element which is a sensor, preferably a chemical sensor, and particularly a biosensor.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: December 1, 2009
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Johannus Wilhelmus Weekamp, Menno Willem Jose Prins
  • Patent number: 7612457
    Abstract: An integrated circuit includes a first surface configured for mounting to a carrier, an active area of the integrated circuit spaced from the first surface, a bond pad disposed over and in electrical communication with the active area, and a ceramic inorganic stress-buffering layer disposed between the active area and the bond pad.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: November 3, 2009
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Alfred Haimerl, Angela Wieneke Kessler, Michael Bauer
  • Patent number: 7598123
    Abstract: A semiconductor component comprising two stacked semiconductor dice and a method of manufacture. A leadframe having an active area that includes leadframe leads and a cavity is mounted to a support material such as an adhesive tape. A packaged semiconductor die that includes a first semiconductor die mounted to a support structure and encapsulated within a mold compound is mounted on the adhesive tape. A second semiconductor die is mounted to the packaged semiconductor die. Bond pads on the second semiconductor die are electrically connected to the leadframe, the support structure on which the first semiconductor die is mounted, or both. A mold compound is formed around the second semiconductor die, portions of the leadframe, and the packaged semiconductor die. The adhesive tape is removed and the leadframe is singulated to form multi-chip packages.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: October 6, 2009
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Jay A. Yoder, Joseph K. Fauty, James P. Letterman