Characterized By Die Pad (epo) Patents (Class 257/E23.037)
  • Patent number: 10553525
    Abstract: A semiconductor device has a semiconductor chip, a signal lead that is arranged in a periphery of the semiconductor chip and has a main surface and a rear surface opposed to the main surface, a wire that electrically connects the semiconductor chip and the main surface of the signal lead, and a sealing body made of sealing resin that seals the semiconductor chip, the signal lead and the wire. The signal lead has, in an extending direction of the signal lead, one end located inside the sealing body, the other end located outside the sealing body, and a wire connection region which is the main surface of the signal lead and to which the wire is connected, and an inner groove is provided in the main surface of the signal lead between the one end and the wire connection region.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: February 4, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tomoya Kashiwazaki
  • Patent number: 10403566
    Abstract: A power module (10) having a leadframe (20), a power semiconductor (30) arranged on the leadframe (20), a base plate (40) for dispersing heat generated by the power semiconductor (30) and a potting compound (50) surrounding the leadframe (20) and the power semiconductor (30), that physically connects the power semiconductor (30) and/or the leadframe (20) to the base plate (40).
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: September 3, 2019
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Ronald Eisele, Frank Osterwald
  • Patent number: 10361156
    Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Bey Wu, Dian-Hau Chen, Jye-Yen Cheng, Sheung-Hsuan Wei, Li-Yu Lee, Tai-Yang Wu
  • Patent number: 10347551
    Abstract: A semiconductor package comprises a resin material, a semiconductor chip in the resin material, and a metal member in the resin material. The metal member has a first surface that faces the semiconductor chip and a second surface that is opposed to the first surface. The first surface of the metal member has a plurality of first recess portions formed thereon. The first recess portions extend into the metal member and have an opening width that is less than a bottom width.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: July 9, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Kishi, Akito Shimizu
  • Patent number: 10204890
    Abstract: Methods, systems, and devices for enabling the use of a special, generic, or standard substrate for similar system SIP assemblies are disclosed. The required customization, which is defined by a system's interconnecting scheme, is done during package assembly by creating appropriate connections using wire bonds on pads that are placed on the substrate and intentionally left open for purpose of customization. The wire bond links can be changed as required for a given system design.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: February 12, 2019
    Assignee: Octavo Systems LLC
    Inventors: Masood Murtuza, Gene Alan Frantz
  • Patent number: 10177770
    Abstract: A circuit device includes a digital interface, a processor, an oscillation signal generation circuit, a clock signal generation circuit that generates a clock signal having frequency obtained through multiplication of a frequency of the oscillation signal, and terminal groups of the digital interface and the clock signal generation circuit. The terminal group of the digital interface is disposed in a first region along a first side of the circuit device, and the terminal group of the clock signal generation circuit is disposed in any one of second, third and fourth regions of the circuit device.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: January 8, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Takemi Yonezawa
  • Patent number: 9972560
    Abstract: A lead frame includes a first lead frame including a first lead; a second lead frame including a second lead, the second lead frame being stacked on the first lead frame so that a space is formed between the first lead frame and the second lead frame, and the second lead being bonded to the first lead; and a resin portion provided in the space formed between the first lead frame and the second lead frame, wherein each of the first lead and the second lead includes an embedded portion embedded in the resin portion, and a protruding portion protruded from the resin portion, and wherein the embedded portion of the first lead and the embedded portion of the second lead are bonded in the resin portion.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: May 15, 2018
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Tetsuichiro Kasahara, Hideki Matsuzawa, Masayuki Okushi, Naoya Sakai
  • Patent number: 9911684
    Abstract: A system, in some embodiments, comprises: a first surface of a lead frame; a second surface of the lead frame, opposite the first surface, said second surface having been etched; and one or more holes passing through said lead frame and coincident with the first and second surfaces, wherein said one or more holes are adapted to control fluid flow on said first surface.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: March 6, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Stephen St. Germain, Dennis Lee Conner, Jay A. Yoder
  • Patent number: 9905498
    Abstract: The disclosed embodiments of electronic packages include electrical contact pad features present on all sides of the package that facilitate simple and low cost electrical connections to the package made through a mechanical contacting scheme. In an embodiment, an electronic package comprises: a metal leadframe having a first leadframe portion having a first thickness and a second leadframe portion having a second thickness that is less than the first thickness, the second leadframe portion defining electrical contact pads; a silicon die attached to the second leadframe portion and overlying a space formed in the leadframe by the first and second leadframe portions; and wirebonds coupling the silicon die to the electrical contact pads. A method of fabricating the electronic package is also disclosed.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: February 27, 2018
    Assignee: Atmel Corporation
    Inventor: Ken M. Lam
  • Patent number: 9831158
    Abstract: A semiconductor device includes a lead frame; a semiconductor chip mounted on the lead frame; and an encapsulation resin, wherein a convexo-concave portion including a plurality of concave portions is provided at a covered portion of the lead frame that is covered by the encapsulation resin, wherein the planer shape of each of the concave portions is a circle, the diameter of which is greater than or equal to 0.020 mm and less than or equal to 0.060 mm, or a polygon, the diameter of whose circumcircle is greater than or equal to 0.020 mm and less than or equal to 0.060 mm, and wherein a ratio S/S0 is greater than or equal to 1.7 where ā€œSā€ is a surface area of the convexo-concave portion that is formed at a flat surface whose surface area is ā€œS0ā€.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: November 28, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Shintaro Hayashi
  • Patent number: 9640463
    Abstract: Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry. The semiconductor device includes a built-up substrate lead frame having, a sub-structure of I/O terminals and a die attach area, the I/O terminals and die attach area enveloped in a molding compound, the die attach area having exposed areas to facilitate device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads; connection traces electrically couple the I/O terminals with one another, said connection traces having facilitated electroplating of exposed vertical surfaces of the I/O terminals during assembly, said connection traces being severed after assembly. An envelope of molding compound encapsulates the device die onto the built-up substrate lead frame.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: May 2, 2017
    Assignee: Nexperia B.V.
    Inventors: Kan Wae Lam, Pompeo V. Umali, Chi Ho Leung, Shun Tik Yeung, Chi Ling Shum
  • Patent number: 9613829
    Abstract: Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: April 4, 2017
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Seung Woo Lee, Byong Jin Kim, Won Bae Bang, Sang Goo Kang
  • Patent number: 9508678
    Abstract: A method of manufacturing a semiconductor device which improves the reliability of a semiconductor device. The method of manufacturing the semiconductor device includes the step of connecting a ball portion formed at the tip of a wire with a pad (electrode pad) of a semiconductor chip. The pad is comprised of an aluminum-based material and has a trench in its portion to be connected with the ball portion. The ball portion is comprised of a harder material than gold. The step of connecting the ball portion includes the step of applying ultrasonic waves to the ball portion.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: November 29, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Naoki Kawanabe
  • Patent number: 9355943
    Abstract: Provided is a method of manufacturing a semiconductor device which includes a semiconductor chip, an insulating board mounted with the semiconductor chip and having a wiring pattern, and a leadframe connected to the wiring pattern, the semiconductor chip, the wiring pattern and the leadframe being partially sealed with a sealing resin, wherein: an epoxy resin composition formed by adding 0.3 to 0.7 mass % of epoxysilane as a silane coupling agent to an epoxy resin is used as the sealing resin; and a copper member made of copper or a copper alloy and having an oxide film formed in the surface with a film thickness in a color indicated by an L* value in the range of 48 to 51, an a* value in the range of 40 to 49 and a b* value in the range of 24 to 40 is used as the leadframe and the wiring pattern.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: May 31, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuko Nakamata, Yuji Ichimura, Kei Yamaguchi
  • Patent number: 9323972
    Abstract: A finger biometric sensor may include first and second integrated circuit (IC) dies arranged in a stacked relation. The first IC die may include a first semiconductor substrate and an array of finger biometric sensing pixels thereon, and the second IC die may include a second semiconductor substrate and processing circuitry thereon coupled to the array of finger biometric sensing pixels. The first and second IC dies may each have respective first and second non-rectangular shapes, such as circular shapes that are coextensive.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: April 26, 2016
    Assignee: APPLE INC.
    Inventors: Jean-Marie Bussat, Gordon S. Franza, Giovanni Gozzini
  • Patent number: 9024419
    Abstract: A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: May 5, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Tadatoshi Danno, Hiroyoshi Taya, Yoshiharu Shimizu
  • Patent number: 9012268
    Abstract: Embodiments of the present disclosure are directed to leadframe strips and methods of forming packages that include first separating adjacent leads of a leadframe strip and subsequently singulating components into individual packages. In one embodiment, the adjacent leads are separated by etching through the leads, thereby providing electrical isolation of the adjacent packages. In that regard, if desired, the individual adjacent packages may be electrically tested in leadframe strip form. Subsequently, the individual packages are formed by sawing through the encapsulation material.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Jonathan Jaurigue, Rogelio Real, Francis Ann Llana, Ricky Calustre, Rodolfo Gacusan
  • Patent number: 8987879
    Abstract: A semiconductor device includes a leadframe with a die pad and a first lead, a semiconductor chip with a first electrode, and a contact clip with a first contact area and a second contact area. The semiconductor chip is placed over the die pad. The first contact area is placed over the first lead and the second contact area is placed over the first electrode of the semiconductor chip. A plurality of protrusions extends from each of the first and second contact areas and each of the protrusions has a height of at least 5 ?m.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: March 24, 2015
    Assignee: Infineon Technologies AG
    Inventor: Ralf Otremba
  • Patent number: 8981540
    Abstract: A package structure is disclosed, which includes: a carrier having a recessed portion formed on a lower side thereof and filled with a dielectric material; a semiconductor element disposed on an upper side of the carrier and electrically connected to the carrier; and an encapsulant formed on the upper side of the carrier for encapsulating the semiconductor element. Therein, the dielectric material is exposed from the encapsulant. As such, when the carrier is disposed on a circuit board, the dielectric material is sandwiched between the lower side of the carrier and the circuit board to form a decoupling capacitor, thereby improving the power integrity.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: March 17, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Yu Chiang, Wen-Jung Chiang, Hsing-Hung Lee
  • Patent number: 8956920
    Abstract: Embodiments of a method for preparing a leadframe for integrated circuit (IC) die packaging in a molded package with an exposed die pad are disclosed. In one embodiment, a method involves producing a leadframe with a die pad, wherein the die pad has a top surface, a bottom surface, and a perimeter edge. The die pad is then planarized to flatten burrs that may exist at the perimeter edge of the die pad, wherein planarizing the die pad comprises embedding tool markings in the die pad at the perimeter edge of the die pad, the tool markings including a series of peaks and valleys that run parallel to the perimeter edge at all locations around the perimeter edge. Embodiments of a leadframe for IC die packaging in a molded package are also disclosed.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: February 17, 2015
    Assignee: NXP B.V.
    Inventors: Tsung Yi Wu, Chyi Keh Chern, Tsung Wen Chang
  • Patent number: 8936971
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle group having a first package paddle electrically isolated from a second package paddle; attaching an integrated circuit device on the first package paddle and the second package paddle; forming a standoff terminal adjacent the package paddle group and electrically connected to the integrated circuit device; connecting a paddle connector to the integrated circuit device and the first package paddle and another paddle connector to the integrated circuit device and the second package paddle; and forming an encapsulation over the integrated circuit device, the first package paddle, the second package paddle, and the standoff terminal, the encapsulation exposing a portion of the first package paddle, the second package paddle, and the standoff terminal.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: January 20, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Patent number: 8921985
    Abstract: A semiconductor device includes: a semiconductor chip including a main surface electrode; a first mounting lead; a second mounting lead; a connection lead which overlaps with the main surface electrode, the first mounting lead and the second mounting lead when viewed in a thickness direction of the semiconductor chip and makes electrical conduction between the main surface electrode, the first mounting lead and the second mounting lead; and a resin portion which covers the semiconductor chip, the first mounting lead and the second mounting lead, wherein the resin portion has a resin bottom lying on the same plane as a bottom of the first mounting lead and a bottom of the second mounting lead.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: December 30, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Koshun Saito
  • Patent number: 8916965
    Abstract: Thermal transfer from a silicon-on-insulator (SOI) die is improved by mounting the die in a bump-on-leadframe manner in a semiconductor package, with solder or other metal bumps connecting the active layer of the SOI die to metal leads used to mount the package on a printed circuit board or other support structure.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: December 23, 2014
    Assignee: Advanced Analogic Technologies Incorporated
    Inventor: Richard K. Williams
  • Patent number: 8836104
    Abstract: Various stress relief structures are provided for effectively reducing thermal stress on a semiconductor chip in a chip package. Trenches on a metal substrate are created in groups in two-dimension, where each trench is opened from top or bottom surface of the metal substrate and in various shapes. The metal substrate is partitioned into many smaller substrates depending on the number of trench groups and partitions, and is attached to a semiconductor chip for stress relief. In an alternative embodiment, a plurality of cylindrical metal structures are used together with a metal substrate in a chip package for the purpose of heat removal and thermal stress relief on a semiconductor chip. In another alternative embodiment, a metal foam is used together with a semiconductor chip to create a chip package. In another alternative embodiment, a semiconductor chip is sandwiched between a heat sink and a circuit board by solder bumps directly with underfill on the circuit board.
    Type: Grant
    Filed: March 3, 2012
    Date of Patent: September 16, 2014
    Inventor: Ho-Yuan Yu
  • Patent number: 8835219
    Abstract: An electric device and a method of making an electric device are disclosed. In one embodiment the electric device comprises a component comprising a component contact area and a carrier comprising a carrier contact area. The electric device further comprises a first conductive connection layer connecting the component contact area with the carrier contact area, wherein the first conductive connection layer overlies a first region of the component contact area and a second connection layer connecting the component contact area with the carrier contact area, wherein the second connection layer overlies a second region of the component contact area, and wherein the second connection layer comprises a polymer layer.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: September 16, 2014
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Khalil Hosseini
  • Patent number: 8835225
    Abstract: A Quad Flat No-Lead (QFN) semiconductor package includes a die pad; I/O connections disposed at the periphery of the die pad; a chip mounted on the die pad; bonding wires; an encapsulant for encapsulating the die pad, the I/O connections, the chip and the bonding wires while exposing the bottom surfaces of the die pad and the I/O connections; a surface layer formed on the bottoms surfaces of the die pad and the I/O connections; a dielectric layer formed on the bottom surfaces of the encapsulant and the surface layer and having openings for exposing the surface layer. The surface layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the die pad and prevent solder extrusion on the interface of the I/O connections and the dielectric layer, thereby increasing product yield.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: September 16, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Fu-Di Tang, Ching-Chiuan Wei, Yung-Chih Lin
  • Patent number: 8829660
    Abstract: A resin-sealed semiconductor device includes a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured via a solder layer; a sealing resin layer sealing the semiconductor chip; and lead terminals connected electrically with the semiconductor chip. One end portion of the lead terminals is covered by the sealing resin layer. The die pad and the lead terminals are formed of copper and a copper alloy, and the die pad is formed with a thickness larger than a thickness of the lead terminals, which is a thickness of 0.25 mm or more.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: September 9, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Yasumasa Kasuya, Motoharu Haga, Shoji Yasunaga
  • Patent number: 8816480
    Abstract: The electronic device package includes a package substrate including a frame portion and a cantilever portion surrounded by the frame portion, at least one semiconductor chip mounted on the cantilever portion, and a molding member disposed on the package substrate to cover the at least one semiconductor chip. The cantilever portion has a first edge connected to the frame portion and declines from the first edge toward a second edge located opposite to the first edge. Related methods are also provided.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: August 26, 2014
    Assignee: SK Hynix Inc.
    Inventor: Tae Jim Kang
  • Patent number: 8796838
    Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: August 5, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yukihiro Satou, Toshiyuki Hata
  • Patent number: 8796826
    Abstract: A device and method for minimizing the forces that may compromise a lead frame mount to a support structure in an integrated circuit die package during various packaging method steps. When a window clamp is used to provide pressure during a lead frame bonding step or during a wire bonding step during packaging, the vertical force applied by the window clamp may be transferred in lateral direction by the physical contour of the top plate of the support structure. By changing the physical contour of the top plate of the support structure, such as by disposing a specific kind of contoured protrusion, one may minimize or eliminate the lateral forces that act against achieving a solid bond of the lead frame to the support structure. Further, during wire bonding, the same minimization or elimination of lateral forces lead to improved wire bonding.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 5, 2014
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Xueren Zhang, Kim-Yong Goh, Wingshenq Wong
  • Patent number: 8791555
    Abstract: A semiconductor device including a semiconductor element, a die pad of a plane size smaller than that of the semiconductor element, a plurality of hanging leads extending from the die pad, and sealing resin for covering the semiconductor element, the die pad, and the hanging leads. The width of a first main surface of each hanging lead, integrated with the mounting surface of the die pad, is smaller than the width of a second main surface thereof, integrated with the opposite surface of the die pad.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: July 29, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takahiro Yurino
  • Patent number: 8772088
    Abstract: In a high frequency module, electronic components are mounted on a mounting surface of a collective substrate including a plurality of unit substrates that include a via conductor electrically conducted to a ground potential in a peripheral portion thereof, and the mounting surface and the electronic components are encapsulated with an encapsulation layer. The collective substrate is cut on the encapsulation layer side, thereby forming a half-cut groove penetrating through the encapsulation layer and extending halfway along the collective substrate in a thickness direction such that the via conductor is exposed only at a bottom surface of the half-cut groove. A conductive shield layer is formed to cover the encapsulation layer and is electrically conducted to the exposed via conductor. The collective substrate is then cut into individual unit substrates each including the conductive shield layer electrically conducted to the ground potential through the via conductor.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: July 8, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takayuki Horibe
  • Patent number: 8759956
    Abstract: Embodiments provide provides a chip package. The chip package may include a leadframe having a die pad and a plurality of lead fingers; a first chip attached to the die pad, the first chip being bonded to one or more of the lead fingers via a first set of wire bonds; a second chip bonded to one or more of the lead fingers via flip chip; and a heat slug attached to the second chip.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: June 24, 2014
    Assignee: Infineon Technologies AG
    Inventor: Tyrone Jon Donato Soller
  • Patent number: 8749037
    Abstract: A multiple memory access system is disclosed. The system includes a first die disposed on a package substrate. A second die is stacked above the first die. The first die, the second die and the package substrate form a first package. An IC is placed within a close proximity of the first package where the first die communicates with the second die at a first data rate while the first die communicates with the IC at a second data rate. The first data rate is higher than the second data rate.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: June 10, 2014
    Assignee: Altera Corporation
    Inventor: Hui Liu
  • Patent number: 8735223
    Abstract: A method of forming a semiconductor device includes affixing a die to a heat sink to form a die and heat sink assembly and then placing the die and heat sink assembly on a support element. A semiconductor device includes a die and heat sink assembly disposed on a support element. The die and heat sink assembly is pre-assembled prior to being disposed on the support element.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: May 27, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Wei Gao, Zhiwei Gong, Dehong Ye, Huchang Zhang
  • Patent number: 8729553
    Abstract: A thin film transistor (TFT), a method of fabricating the same, and display device having the TFT of which the TFT includes a metal catalyst layer disposed on a substrate, a semiconductor layer disposed on the metal catalyst layer, a gate insulating layer disposed on the entire surface of the substrate, a gate electrode disposed on the gate insulating layer at a position corresponding to the semiconductor layer, an interlayer insulating layer disposed on the entire surface of the substrate, and source and drain electrodes disposed on the interlayer insulating layer and connected to the semiconductor layer, wherein the metal catalyst layer includes one of carbon, nitrogen, and halogen. The thin film transistor includes a poly-Si layer that may be formed to a smaller thickness than in conventional deposition methods thereby producing a TFT in which the remaining amount of metal catalyst in a semiconductor layer is reduced.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: May 20, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin-Seong Park, Yeon-Gon Mo, Hye-Dong Kim
  • Patent number: 8722530
    Abstract: A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: May 13, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gregory S. Spencer, Phillip E. Crabtree, Dean J. Denning, Kurt H. Junker, Gerald A. Martin
  • Publication number: 20140117521
    Abstract: A lead frame for assembling a semiconductor device has a die pad surrounded by lead fingers. Each of the lead fingers has a proximal end close to but spaced from an edge of the die pad and a distal end farther from the die pad. A semiconductor die is attached to a surface of the die pad. The die has die bonding pads on its upper surface that are electrically connected to the proximal ends of the lead fingers with bond wires. An encapsulation material covers the bond wires, semiconductor die and the proximal ends of the lead fingers. Prior to assembly, hot spots of the die are determined and the lead fingers closest to the hot spots are selected to project closer to the die than the other lead fingers. These longer lead fingers assist in dissipating the heat at the die hot spot.
    Type: Application
    Filed: October 29, 2012
    Publication date: May 1, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chetan Verma, Piyush Kumar Mishra, Cheong Chiang Ng
  • Patent number: 8709875
    Abstract: A method of packaging a power semiconductor die includes providing a first lead frame of a dual gauge lead frame. The first lead frame includes a thick die pad. A tape is attached to a first side of the thick die pad and the power die is attached to a second side of the thick die pad. A second lead frame of the dual gauge lead frame is provided. The second lead frame has thin lead fingers. One end of the lead fingers is attached to an active surface of the power die such that the lead fingers are electrically connected to bonding pads of the power die. A molding compound is then dispensed onto a top surface of the dual gauge lead frame such that the molding compound covers the power die and the lead fingers.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: April 29, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinzhong Yao, Zhigang Bai, Xuesong Xu
  • Patent number: 8698294
    Abstract: An integrated circuit package system provides a known good die module by providing a leadframe, providing a first die, attaching the first die to the leadframe, and encapsulating at least the first die. A second die is attached to the known good die module such that the known good die module is a substrate for the second die. The second die is electrically attached to the known good die module. At least the second die is additionally encapsulated.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: April 15, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Jose Alvin Caparas, Arnel Trasporto, Jeffrey D. Punzalan
  • Patent number: 8680661
    Abstract: Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: March 25, 2014
    Assignee: International Rectifier Corporation
    Inventor: Eung San Cho
  • Patent number: 8674487
    Abstract: A semiconductor package with a die pad, a die disposed on the die pad, and a first lead disposed about the die pad. The first lead includes a contact element, an extension element extending substantially in the direction of the die pad, and a concave surface disposed between the contact element and the extension element. A second lead having a concave surface is also disposed about the die pad. The first lead concave surface is opposite in direction to the second lead concave surface.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: March 18, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Lin-Wang Yu, Ping-Cheng Hu, Che-Chin Chang, Yu-Fang Tsai
  • Patent number: 8669654
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having a single integral structure with a paddle central portion surrounded by a paddle peripheral portion; forming a terminal adjacent the package paddle; mounting an integrated circuit over the paddle central portion; and forming an encapsulation over the integrated circuit and the terminal, the encapsulation free of delamination with the encapsulation directly on the paddle peripheral portion.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: March 11, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8669646
    Abstract: Methods and apparatus for improved electromagnetic interference (EMI) shielding and thermal performance in integrated circuit (IC) packages are described. A die-up or die-down package includes a protective lid, a plurality of ground posts, an IC die, and a substrate. The substrate includes a plurality of ground planes. The IC die is mounted to the substrate. Plurality of ground posts is coupled to plurality of ground planes that surround IC die. Protective lid is coupled to plurality of ground posts. The plurality of ground posts and the protective lid from an enclosure structure that substantially encloses the IC die, and shields EMI from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: March 11, 2014
    Assignee: Broadcom Corporation
    Inventors: Mohammad Tabatabai, Abbas Amirichimeh, Lorenzo Longo
  • Publication number: 20140061883
    Abstract: A leadframe (e.g., incorporated in a device package) includes a feature (e.g., a die pad or lead) with a vent hole formed between first and second opposed surfaces. The cross-sectional area of the vent hole varies substantially between the surfaces (e.g., the vent hole has a constricted portion). The vent hole may be formed from a first opening extending from the first surface toward the second surface to a first depth that is less than a thickness of the leadframe feature, and a second opening extending from the second surface toward the first surface to a second depth that is less than the thickness of the leadframe feature, but that is large enough for the second opening to intersect the first opening. Vertical central axes of the openings are horizontally offset from each other, and the constricted portion of the vent hole corresponds to the intersection of the openings.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 6, 2014
    Inventors: PHILIP H. BOWLES, Stephen R. Hooper
  • Patent number: 8664752
    Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: March 4, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
  • Patent number: 8647974
    Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a first conductor pad and a passivation structure. A second conductor pad is fabricated around but not in physical contact with the first conductor pad to leave a gap. The second conductor pad is adapted to protect a portion of the passivation structure.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: February 11, 2014
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Roden R. Topacio, Michael Z. Su, Neil McLellan
  • Patent number: 8648474
    Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: February 11, 2014
    Assignee: UTAC Thai Limited
    Inventors: Somchai Nondhasittichai, Saravuth Sirinorakul
  • Patent number: 8643158
    Abstract: A semiconductor package is assembled using first and second lead frames. The first lead frame includes a die flag and the second lead frame includes lead fingers. When the first and second lead frames are mated, the lead fingers surround the die flag. Side surfaces of the die flag are partially etched to form an extended die attach surface on the die flag, and portions of the top surface of each of the lead fingers also are partially etched to form lead finger surfaces that are complementary with the etched side surfaces of the die flag. A semiconductor die is attached to the extended die attach surface and bond pads of the semiconductor die are electrically connected to the lead fingers. An encapsulating material covers the die, electrical connections, and top surfaces of the die flag and lead fingers.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Peng Liu, Qingchun He, Ping Wu
  • Publication number: 20140008777
    Abstract: Embodiments of the present invention are directed to a thermal leadless array package with die attach pad locking feature and methods of producing the same. A copper layer is half-etched on both surfaces to define an array of package contacts and a die attach pad. Each die attach pad is fully embedded in encapsulate material to provide a positive mechanical locking feature for better reliability. In some embodiments, the contacts include four active corner contacts.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 9, 2014
    Applicant: UTAC DONGGUAN LTD
    Inventors: Albert LOH, Edward THEN, Serafin PEDRON, JR., Saravuth Sirinorakul