Plurality Of Lead Frames Mounted In One Device (epo) Patents (Class 257/E23.042)
  • Patent number: 11387117
    Abstract: A component carrier having a base structure consisting of an electrically conductive material, an electronic component arranged on the base structure and a surrounding structure on the base structure, where the surrounding structure at least partially surrounds the electronic component laterally.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: July 12, 2022
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Minwoo Lee
  • Patent number: 11189556
    Abstract: A semi-manufactured power semiconductor module includes a substrate for bonding at least one power semiconductor chip; a first leadframe bonded to the substrate and providing power terminals; and a second leadframe bonded to the substrate and providing auxiliary terminals; wherein the first leadframe and/or the second leadframe include an interlocking element adapted for aligning the first leadframe and the second leadframe with respect to each other and/or with respect to a mold for molding an encapsulation around the substrate, the first leadframe and the second leadframe.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: November 30, 2021
    Assignees: ABB Power Grids Switzerland AG, AUDI AG
    Inventors: Fabian Mohn, Chunlei Liu, Jürgen Schuderer
  • Patent number: 10580666
    Abstract: A carrier substrate includes a base layer having a first surface, and having a second surface that is parallel to and opposite of the first surface. The carrier substrate further includes a glass layer bonded to the first surface of the base layer. The carrier substrate has a Young's modulus greater than or equal to 150 GPa. A carrier substrate includes a polycrystalline ceramic and has a Young's modulus greater than or equal to 150 GPa. The carrier substrate has a coefficient of thermal expansion of greater than or equal to 20×10?7/° C. to less than or equal to 120×10?7/° C. over a range from 25° C. to 500° C.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: March 3, 2020
    Assignee: Corning Incorporated
    Inventors: Sumalee Likitvanichkul Fagan, Weiguo Miao, Eric James Nichols
  • Patent number: 10312183
    Abstract: A die package component with a jumper structure includes a first lead frame, a second lead frame, a die, a jumper structure and a package body. The first lead frame has a die connection surface. The second lead frame is separated to the first lead frame. The second lead frame has a lead frame connection groove which defines a thermal deformation tolerance allowable route. The jumper structure is thermally deformed in a thermal-variable environment. The jumper structure includes a die welding portion and a lead welding portion. The die welding portion is welded to the die. Upon meeting a thermal deformation, the lead welding portion would be movable welded along the thermal deformation tolerance allowable route to the lead frame connection groove.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR CO., LTD.
    Inventors: Reyn Qin, Lucy Fan, Meifang Song, Xiaoli Wang
  • Patent number: 10269696
    Abstract: Flexible circuits mountable in a standoff region between a chip carrier, e.g., a ball grid array (BGA) component, and a printed circuit board (PCB) of a surface-mount package are described. In an example, a flexible circuit includes holes to receive pins, e.g., solder balls, of the BGA component, and one or more conductive leads electrically connected to respective solder balls within the holes. The conductive leads may interconnect several solder balls within the standoff region, and may be electrically accessible through a test pad located laterally outward from the standoff region. Electrical signals may be monitored or driven through the test pad, and thus, the flexible circuit may be used as a debug tool for detecting and or correcting a design fault of the surface-mount package.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Gerrit John Vreman, Animesh Mishra
  • Patent number: 10104762
    Abstract: The invention relates to an electric assembly to be mounted on a top-hat rail, comprising: an electric current supply component (200): a multi-layered support (206) including a metal plate (300), a conductive layer (302) for electrically contacting the electric current supply component (200) and an electric insulation layer (304) which is arranged between the metal plate (300) and the conductive layer (302); the electric current supply component (200) is connected in an heat-conductive manner to the metal plate (300) in order to withdraw thermal energy from the electric current supply component (200).
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: October 16, 2018
    Assignees: PHOENIX CONTACT GMBH & CO. KG, PHOENIX CONTACT POWER SUPPLIES GMBH
    Inventors: Hartmut Henkel, Michael Heinemann, Guido Remmert
  • Patent number: 9978695
    Abstract: A semiconductor device includes a die pad, a plurality of first lands each having a first land first top recessed portion disposed on a first land first end distal to the die pad, and a plurality of second lands each having a second land first bottom recessed portion disposed on a second land first end distal to the die pad. A semiconductor die is electrically connected to the first and second lands. A package body, which defines a bottom surface and a side surface, at least partially encapsulating the first and second lands and the semiconductor die such that at least portions of the first and second lands are exposed in and substantially flush with the bottom surface of the package body.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: May 22, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Jae Min Bae, Byong Jin Kim, Won Bae Bang
  • Patent number: 9870985
    Abstract: An electronic component includes a leadframe and a first semiconductor die. The leadframe includes a leadframe top side, a leadframe bottom side opposite the leadframe top side, and a top notch at the leadframe top side. The top notch includes a top notch base located between the leadframe top side and the leadframe bottom side, and defining a notch length of the top notch, and can also include a top notch first sidewall extended, along the notch length, from the leadframe top side to the top notch base. The first semiconductor die can include a die top side a die bottom side opposite the die top side and mounted onto the leadframe top side, and a die perimeter. The top notch can be located outside the die perimeter. Other examples and related methods are also disclosed.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: January 16, 2018
    Assignee: Amkor Technology, Inc.
    Inventor: Marc Alan Mangrum
  • Patent number: 9632487
    Abstract: Discussed is an organic light emitting display device including a substrate having a display area in which a plurality of plurality pixels are disposed, a non-display area outside of the display area, and at least one open hole area defined between the plurality of pixels, and a stacked layer structure disposed on the substrate and defining the plurality of pixels in the display area, the stacked layer structure including at least one organic layer, wherein the at least one open hole area includes at least one open hole penetrating through the substrate and at least one partition disposed along a circumference of the at least one open hole between the at least one open hole and the plurality of pixels adjacent thereto to separate the at least one organic layer from a corresponding layer that extends to the at least one open hole.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: April 25, 2017
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Miso Kim, Taejoon Ahn, Sangmoo Song, Heekwang Kang, Hoyoung Lee
  • Patent number: 9631481
    Abstract: A semiconductor device includes a die pad, a plurality of first lands each having a first land first top recessed portion disposed on a first land first end distal to the die pad, and a plurality of second lands each having a second land first bottom recessed portion disposed on a second land first end distal to the die pad. A semiconductor die is electrically connected to the first and second lands. A package body, which defines a bottom surface and a side surface, at least partially encapsulating the first and second lands and the semiconductor die such that at least portions of the first and second lands are exposed in and substantially flush with the bottom surface of the package body.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: April 25, 2017
    Assignee: Amkor Technology, Inc.
    Inventors: Jae Min Bae, Byong Jin Kim, Won Bae Bang
  • Patent number: 9559043
    Abstract: A leadframe, a package assembly and methods for manufacturing the same are disclosed. A plurality of electronic devices are stacked in a plurality of levels in the package assembly. The leadframe includes a plurality of leads having interconnect areas. The plurality of leads are grouped so that the interconnect areas of each group of leads have a height corresponding to one level of electronic devices. In the package assembly, the interconnect areas of each group of leads are soldered to one level of electronic devices. The leadframe and the package assembly result in increased packaging density, less usage of bonding wires in the package assembly, and improve reliability. The method for manufacturing the package assembly reduces adverse effects of a reflow process on properties of the electronic devices, and thus further improves reliability of the package assembly.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: January 31, 2017
    Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd.
    Inventor: Jiaming Ye
  • Patent number: 9508631
    Abstract: In one embodiment, a semiconductor device includes a die pad defining multiple peripheral edge segments. In addition, the semiconductor device includes a plurality of leads and lands which are provided in a prescribed arrangement. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads and lands. At least portions of the die pad, the leads, the lands, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and the lands being exposed in a common exterior surface of the package body.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: November 29, 2016
    Assignee: Amkor Technology, Inc.
    Inventors: Jae Min Bae, Byong Jin Kim, Won Bae Bang
  • Patent number: 9275939
    Abstract: In one embodiment, a semiconductor device includes a die pad defining multiple peripheral edge segments. In addition, the semiconductor device includes a plurality of leads and lands which are provided in a prescribed arrangement. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads and lands. At least portions of the die pad, the leads, the lands, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and the lands being exposed in a common exterior surface of the package body.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: March 1, 2016
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Jae Min Bae, Byong Jin Kim, Won Bae Bang
  • Patent number: 9029903
    Abstract: A light emitting diode package including a package body with a cavity, a plurality of light emitting diode (LED) chips in the cavity, a plurality of wires connected to the plurality of LED chips, and a plurality of lead frames in the package body, wherein the lead frames comprise a first lead frame electrically connected to a first electrode of a first LED chip, a second lead frame electrically connected to a second electrode of the first LED chip and a second electrode of a second LED chip, a third lead frame electrically connected to a first electrode of the second LED chip, and fourth lead frame electrically connected to a second electrode of a third LED chip. Further, ends of the lead frames are exposed outside of the package body and penetrate the package body, and the first electrodes are P electrodes and the second electrodes are N electrodes.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: May 12, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Won-Jin Son
  • Patent number: 9024420
    Abstract: Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: May 5, 2015
    Assignee: International Rectifier Corporation
    Inventors: Dean Fernando, Roel Barbosa
  • Patent number: 8975738
    Abstract: A structure may include a spacer element overlying a first portion of a first surface of a substrate; first terminals at a second surface of the substrate opposite the first surface; and second terminals overlying a third surface of the spacer element facing away from the first surface. Traces extend from the second terminals along an edge surface of the spacer element that extends from the third surface towards the first surface, and may be electrically coupled between the second terminals and the first terminals or electrically conductive elements at the first surface. The spacer element may at least partially define a second portion of the first surface, which is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some of the conductive elements are at the second portion and may permit connection with such microelectronic element.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: March 10, 2015
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 8937372
    Abstract: An integrated circuit package system includes an in-line strip, attaching an integrated circuit die over the in-line strip, and applying a molding material with a molded segment having a molded strip protrusion formed therefrom over the in-line strip.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: January 20, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jae Hak Yee, Junwoo Myung
  • Patent number: 8786065
    Abstract: A substrate includes a first lead frame, a second lead frame, and a resin layer. The first lead frame includes a heat sink and a plurality of electrodes for external connection. The second lead frame is laminated on the first lead frame and includes a plurality of wirings for mounting light emitting elements. The resin layer is filled between the first lead frame and the second lead frame. The plurality of wirings are arranged above the heat sink. The plurality of electrodes and part of the plurality of wirings are joined with each other.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: July 22, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yasuyuki Kimura, Tadashi Arai, Tsuyoshi Kobayashi, Toshiyuki Okabe
  • Patent number: 8772914
    Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: July 8, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yasutaka Nakashiba, Kenta Ogawa
  • Patent number: 8716069
    Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: May 6, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Yueh-Se Ho, Yongping Ding
  • Patent number: 8643158
    Abstract: A semiconductor package is assembled using first and second lead frames. The first lead frame includes a die flag and the second lead frame includes lead fingers. When the first and second lead frames are mated, the lead fingers surround the die flag. Side surfaces of the die flag are partially etched to form an extended die attach surface on the die flag, and portions of the top surface of each of the lead fingers also are partially etched to form lead finger surfaces that are complementary with the etched side surfaces of the die flag. A semiconductor die is attached to the extended die attach surface and bond pads of the semiconductor die are electrically connected to the lead fingers. An encapsulating material covers the die, electrical connections, and top surfaces of the die flag and lead fingers.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Peng Liu, Qingchun He, Ping Wu
  • Patent number: 8629538
    Abstract: Disclosed herein is a power module package including: a first substrate having one surface and the other surface; a second substrate contacting one side of one surface of the first substrate; and a first lead frame contacting the other side of one surface of the first substrate. The power module package further includes: a first metal layer formed on one side of one surface of the first substrate; a first bonding layer formed on the first metal layer and contacting a lower surface of the second substrate; a second metal layer formed on the other side of one surface of the first substrate; and a second bonding layer formed on the second metal layer and contacting a lower surface of the first lead frame.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: January 14, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd
    Inventors: Young Ki Lee, Young Ho Sohn, Kwang Soo Kim, Chang Hyun Lim
  • Publication number: 20140008702
    Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads.
    Type: Application
    Filed: July 9, 2012
    Publication date: January 9, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Juergen Schredl, Xaver Schloegel, Klaus Schiess
  • Patent number: 8587101
    Abstract: Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: November 19, 2013
    Assignee: International Rectifier Corporation
    Inventors: Dean Fernando, Roel Barbosa
  • Patent number: 8492786
    Abstract: A light emitting device package is disclosed. The light emitting device package includes a light emitting device disposed on a first lead frame, the light emitting device having an electrode pad on an upper surface thereof, a first wire to electrically interconnect a second lead frame spaced apart from the first lead frame and the electrode pad, and a first bonding ball disposed on the second lead frame, the first bonding ball spaced apart from a first contact point, which is in contact with the first wire and the second lead frame, wherein the first bonding ball is disposed between the first wire and the second lead frame to electrically interconnect the first wire and the second lead frame.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: July 23, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventors: Sunghee Won, Youngsu Chun
  • Patent number: 8487322
    Abstract: A luminous body comprises a transparent plastic moulding with indentations, and LED DIEs disposed within the indentations. One side of each LED DIE lies approximately flush with an upper side of the moulding, and each LED DIE is connected to an electricity supply via electrical conductors disposed on the moulding. A method for producing such a luminous body is also disclosed.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: July 16, 2013
    Assignee: Bayer Intellectual Property GmbH
    Inventors: Andrea Maier-Richter, Eckard Foltin, Michael Roppel, Peter Schibli
  • Patent number: 8487418
    Abstract: According to one embodiment, an LED package includes (2×n) (n is an integer of 2 or more) lead frames, n LED chips and a resin body. The (2×n) lead frames are arranged to be apart from each other. The n LED chips are provided above the lead frames. Each of the n LED chips has one terminal connected to each of n lead frames of the (2×n) lead frames and another terminal connected to each of lead frames of the (2×n) lead frames other than the n lead frames. The resin body covers the (2×n) lead frames and the n LED chips.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: July 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidenori Egoshi, Kazuhiro Tamura, Hiroaki Oshio, Satoshi Shimizu, Teruo Takeuchi, Kazuhiro Inoue, Iwao Matsumoto
  • Patent number: 8471271
    Abstract: Provided is a light emitting diode package and a method of manufacturing the same. The light emitting diode package includes a package main body with a cavity, a plurality of light emitting diode chips, a wire, and a plurality of lead frames. The plurality of light emitting diode chips are mounted in the cavity. The wire is connected to an electrode of at least one light emitting diode chip. The plurality of lead frames are formed in the cavity, and at least one lead frame is electrically connected to the light emitting diode chip or a plurality of wires.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: June 25, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventor: Won-Jin Son
  • Publication number: 20130127029
    Abstract: A leadframe, device package, and mode of construction configured to attain a thin profile and improved thermal performance. Leadframes of this invention include a raised die attachment pad arrange above distal ends of leadframe leads. A package will further include a die electrically coupled with an underside surface of the raised die attachment pad, in one example, using ball bonds, the whole sealed in an encapsulant that exposed a bottom portion of the die and a portion of a lead. Two leadframe stacks of such packages are also disclosed as are methods of manufacture.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 23, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lee Han Meng @ Eugene LEE, Wei Fen Sueann LIM, Chen Seong CHUA, Kooi Choon OOI
  • Publication number: 20130105956
    Abstract: Disclosed herein is a power module package, including: a first lead frame; and a second lead frame. The first lead frame and the second lead frame may be spaced apart from each other, and the first lead frame and the second lead frame may have different thicknesses. In addition, the power module package further includes: a first semiconductor chip bonded to a first surface of one side of the first lead frame; and a second semiconductor chip bonded to a first surface of one side of the second lead frame.
    Type: Application
    Filed: October 24, 2012
    Publication date: May 2, 2013
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Samsung Electro-Mechanics Co., Ltd.
  • Patent number: 8426953
    Abstract: A two tier power module has, in one form thereof, a PC board having upper and lower traces with an opening in the insulating material that contains a power device which has upward extending solder bump connections. An upper leadframe is mounted on the solder bumps and the upper tracks of the PC board. Vias in the PC board connect selected upper and lower traces. A control device is mounted atop the leadframe and wire bonded to the leadframe, and the assembly is encapsulated leaving exposed the bottom surfaces of the lower traces of the PC board as external connections. In another form the PC board is replaced by a planar leadframe and the upper leadframe has stepped sections which make connections with the planar leadframe, the bottom surfaces of the planar leadframe forming external connections of the module.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: April 23, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Yong Liu, Margie T. Rios, Hua Yang, Yumin Liu, Tiburcio A. Maldo
  • Publication number: 20130093069
    Abstract: The invention discloses a package structure made of the combination of a metallic substrate and a lead frame. In one embodiment, a recess is formed in the metallic substrate and a first conductive element having at least one first I/O terminal is bonded in the recess. A lead frame is formed on the metallic substrate and comprises a plurality of electrical connections to connect with said at least one first I/O terminal of the first conductive element. In another embodiment, another conductive element is disposed in the vacancy of the lead frame. The invention also discloses a method for manufacturing a package structure made of the combination of a metallic substrate and a lead frame.
    Type: Application
    Filed: October 14, 2011
    Publication date: April 18, 2013
    Applicant: CYNTEC CO., LTD.
    Inventors: BAU-RU LU, JENG-JEN LI, CHIANG KAIPENG
  • Publication number: 20130069210
    Abstract: Disclosed herein is a power module package including: a first substrate having one surface and the other surface; a second substrate contacting one side of one surface of the first substrate; and a first lead frame contacting the other side of one surface of the first substrate. The power module package further includes: a first metal layer formed on one side of one surface of the first substrate; a first bonding layer formed on the first metal layer and contacting a lower surface of the second substrate; a second metal layer formed on the other side of one surface of the first substrate; and a second bonding layer formed on the second metal layer and contacting a lower surface of the first lead frame.
    Type: Application
    Filed: December 9, 2011
    Publication date: March 21, 2013
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Ki Lee, Young Ho Sohn, Kwang Soo Kim, Chang Hyun Lim
  • Patent number: 8384206
    Abstract: In one embodiment, a semiconductor package is formed to include a leadframe that includes a plurality of die attach areas for attaching a semiconductor die to the leadframe. The leadframe is positioned to overlie another leadframe that forms some of the external terminals or leads of the package.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: February 26, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Stephen St. Germain, Roger M. Arbuthnot, Frank Tim Jones
  • Patent number: 8378470
    Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: February 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yasutaka Nakashiba, Kenta Ogawa
  • Patent number: 8373257
    Abstract: A clip for a semiconductor device package may include a metal sheet including an array of windows and one or more conductive fingers. Each of the conductive fingers has a first end and a second end. The first end is electrically connected to the metal sheet at one of the windows. Each of the conductive fingers is adapted to provide electrical connection to a top semiconductor region of a semiconductor device or a lead frame at the second end.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: February 12, 2013
    Assignee: Alpha & Omega Semiconductor Incorporated
    Inventors: Lei Shi, Zhao Liang, Kai Liu
  • Patent number: 8269334
    Abstract: Embodiments of the present invention provide electrical bussing for multichip leadframes. In various embodiments, a leadframe may comprise a first die paddle for receiving a first microelectronic device, a second die paddle for receiving a second microelectronic device, and at least one electrical bus disposed between the first die paddle and the second die paddle.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: September 18, 2012
    Assignee: Marvell International Ltd.
    Inventor: Michael D. Cusack
  • Publication number: 20120153445
    Abstract: Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer. The insulation layer may include a top, a bottom opposite to the top, and a conductive pattern having different pitches. The organic layer may be connected to the bottom of the insulation layer, and may include a circuit pattern connected to the conductive pattern. The conductive pattern may include a first metal pattern, and a second conductive pattern. The first metal pattern may have a first pitch, and may be disposed in the top of the insulation layer. The second conductive pattern may have a second pitch greater than the first pitch, and may be extended from the first metal pattern to be connected to the circuit pattern through the insulation layer.
    Type: Application
    Filed: August 3, 2011
    Publication date: June 21, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Daewoo Son, Chulwoo Kim
  • Patent number: 8154108
    Abstract: A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacitor configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: April 10, 2012
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Kai Liu, Lei Shi, Jun Lu, Anup Bhalla
  • Patent number: 8138587
    Abstract: A device including two mounting surfaces. One embodiment provides a power semiconductor chip and having a first electrode on a first surface and a second electrode on a second surface opposite to the first surface. A first external contact element and a second external contact element, are both electrically coupled to the first electrode of the semiconductor chip. A third external contact element and a fourth external contact element, both electrically coupled to the second electrode of the semiconductor chip. A first mounting surface is provided on which the first and third external contact elements are disposed. A second mounting surface is provided on which the second and fourth external contact elements are disposed.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: March 20, 2012
    Assignee: Infineon Technologies AG
    Inventor: Ralf Otremba
  • Patent number: 8120153
    Abstract: A cost-effective, ultra-compact, hybrid power module packaging system and method for making allows device operation in conventional and high temperature ranges over 300° C. Double metal leadframes are directly bonded to the front- and backside of semiconductor chips, and injection-molded high temperature polymer materials encapsulate the module. The invention eliminates the use of unreliable metal wirebonds and solders joints, and expensive aluminum nitride ceramic substrates commonly used in conventional and high temperature hybrid power modules. Advantages of the new power modules include high current carrying capability, low package parasitic impedance, low thermo-mechanical stress under high temperature cycling, low package thermal resistance (double-side cooling), modularity for easy system-level integration, and low-cost manufacturing of devices compatible with current electronic packaging industry. A first embodiment uses molybdenum leadframes for operation in temperatures over 300° C.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: February 21, 2012
    Assignee: University of Central Florida Research Foundation, Inc.
    Inventor: Zheng John Shen
  • Patent number: 8115214
    Abstract: Provided is a light emitting diode package and a method of manufacturing the same. The light emitting diode package includes a package main body with a cavity, a plurality of light emitting diode chips, a wire, and a plurality of lead frames. The plurality of light emitting diode chips are mounted in the cavity. The wire is connected to an electrode of at least one light emitting diode chip. The plurality of lead frames are formed in the cavity, and at least one lead frame is electrically connected to the light emitting diode chip or a plurality of wires.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: February 14, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventor: Won-Jin Son
  • Publication number: 20120025358
    Abstract: A semiconductor element to be mounted on a circuit carrier includes a semiconductor die and at least one lead frame. In order to reduce the size required for mounting a semiconductor die on a circuit carrier, a semiconductor element includes a semiconductor die and at least one lead frame. The at least one lead frame is directly attached to the semiconductor die at a connection region of the semiconductor die, and the connection region provides an electrical connection to and mechanical support for the semiconductor die.
    Type: Application
    Filed: March 23, 2011
    Publication date: February 2, 2012
    Inventors: Agatino Carmelo Minotti, Alessandro Lo Piparo
  • Publication number: 20120001311
    Abstract: In a package for a semiconductor device according to the present invention, steps 10 are provided at least on the sides of lead frames 1 and 2 at exposed portions in the opening of a resin part 3, thereby increasing adhesion between the lead frames 1 and 2 and resin and suppressing leakage of molding resin and intrusion of outside air or moisture from a gap between the lead frames 1 and 2 and the resin.
    Type: Application
    Filed: June 21, 2011
    Publication date: January 5, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Masanori Nishino, Hiroshi Horiki
  • Publication number: 20120001310
    Abstract: A package for a semiconductor device according to the present invention includes at least one through hole 6 provided on at least one of lead frames 1 and 2. Thus when resin is injected to form a mounting region 4 of a semiconductor element while holding the lead frames 1 and 2, the resin can be injected from the back sides of the lead frames 1 and 2 through the through hole 6 serving as a resin flow path, thereby shortening the resin flow path and suppressing the occurrence of portions unfilled with the resin and poor appearances.
    Type: Application
    Filed: June 21, 2011
    Publication date: January 5, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Masanori Nishino, Hiroshi Horiki
  • Patent number: 8063479
    Abstract: A housing for a semiconductor component, in which the housing has a plurality of pins which are provided at the edge of the housing at distances, the pins each having a width, a thickness and a length. In order to create a housing for a semiconductor component whose characteristic frequencies are outside a range in which the characteristic frequencies of the housing negatively influence the semiconductor component, either at least one of the distances lies outside the range of 1.24 mm to 1.30 mm, at least one of the widths lies outside the range of 0.33 mm to 0.51 mm, at least one of the thicknesses lies outside the range of 0.23 to 0.32 mm, or at least one of the lengths lies outside the range of 2.05 to 4.12 mm.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: November 22, 2011
    Assignee: Robert Bosch GmbH
    Inventors: Thorsten Wallisch, Christian Solf, Florian Grabmaier
  • Patent number: 8030743
    Abstract: A two tier power module has, in one form thereof, a PC board having upper and lower traces with an opening in the insulating material that contains a power device which has upward extending solder bump connections. An upper leadframe is mounted on the solder bumps and the upper tracks of the PC board. Vias in the PC board connect selected upper and lower traces. A control device is mounted atop the leadframe and wire bonded to the leadframe, and the assembly is encapsulated leaving exposed the bottom surfaces of the lower traces of the PC board as external connections. In another form the PC board is replaced by a planar leadframe and the upper leadframe has stepped sections which make connections with the planar leadframe, the bottom surfaces of the planar leadframe forming external connections of the module.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: October 4, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Yong Liu, Margie T. Rios, Hua Yang, Yumin Liu, Tiburcio A. Maldo
  • Publication number: 20110169152
    Abstract: In one embodiment, a semiconductor package is formed to include a leadframe that includes a plurality of die attach areas for attaching a semiconductor die to the leadframe. The leadframe is positioned to overlie another leadframe that forms some of the external terminals or leads of the package.
    Type: Application
    Filed: March 22, 2011
    Publication date: July 14, 2011
    Inventors: Stephen St. Germain, Roger M. Arbuthnot, Frank Tim Jones
  • Patent number: 7977774
    Abstract: A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of at least one row thereof being exposed in a common exterior surface of the package body.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: July 12, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: YeonHo Choi, GiJeong Kim, WanJong Kim
  • Publication number: 20110156085
    Abstract: A semiconductor package includes at least four lead frames each having an extending portion and a connecting portion, a heat dissipation plate having a top surface and a bottom surface, at least one semiconductor chip positioned on the top surface of the heat dissipation plate. At least one conductive wire electrically connects the chip to the lead frames. An encapsulation covers the lead frames, the heat dissipation plate, the semiconductor chip, and the conductive wires, while the bottom surface of the heat dissipation plate and the extending portions of the lead frames are exposed.
    Type: Application
    Filed: October 12, 2010
    Publication date: June 30, 2011
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: HUNG-CHIN LIN, KUO-FU PENG, CHIEN-MIN CHEN, KO-WEI CHIEN