Insulating Layers On Lead Frame, E.g., Bridging Members (epo) Patents (Class 257/E23.049)
  • Patent number: 10249556
    Abstract: A lead frame strip includes an array of lead frames. The lead frames each include a die pad and lead fingers that are spaced from the die pads and disposed along one or more sides of the die pads. The lead fingers have proximal ends near to the die pad and distal ends farther from the die pad. Connection bars extend between the lead frames. The lead fingers of adjacent lead frames extend from opposing sides of the connection bars. The connection bars have first portions where the lead fingers are connected thereto, and second portions between adjacent lead finger connections to the connection bar. The second portions are etched to form a bar that extends diagonally from a first one of the adjacent lead fingers connected thereto to a second one of the adjacent lead fingers connected thereto.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: April 2, 2019
    Assignee: NXP B.V.
    Inventors: Verapath Vareesantichai, Amornthep Saiyajitara, Pimpa Boonyatee, Adrianus Buijsman
  • Patent number: 9537034
    Abstract: The invention is to facilitate the attachment of an installation system in the production of a solar module. This is achieved via a process which comprises the following steps: a) mutual superposition of the layers that the structure of the solar module requires, where at least one heat-activatable double-sided adhesive tape is placed on the external side of the reverse-side layer and at least one retention plate is placed on said adhesive tape; b) mutual lamination of the layers mutually superposed in step a), at least with exposure to heat.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: January 3, 2017
    Assignee: TESA SE
    Inventors: Michael Schwertfeger, Andreas Stein
  • Patent number: 8791556
    Abstract: An integrated circuit packaging system, and a method of manufacture therefor, including: electrical terminals; circuitry protective material around the electrical terminals and formed to have recessed pad volumes; routable circuitry on the top surface of the circuitry protective material; and an integrated circuit die electrically connected to the electrical terminals.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: July 29, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8703537
    Abstract: The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: April 22, 2014
    Assignee: NeuroNexus Technologies, Inc.
    Inventors: David S. Pellinen, Jamille Farraye Hetke, Daryl R. Kipke, Kc Kong, Rio J. Vetter, Mayurachat Ning Gulari
  • Patent number: 8658465
    Abstract: The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: February 25, 2014
    Assignee: NeuroNexus Technologies, Inc.
    Inventors: David S. Pellinen, Jamille Farraye Hetke, Daryl R. Kipke, Kc Kong, Rio J. Vetter, Mayurachat Gulari
  • Patent number: 8648458
    Abstract: An integrated circuit leadframe device supports various chip arrangements. As consistent with various embodiments, a leadframe includes a plurality of banks of conductive integrated circuit chip connectors. Each bank has a plurality of conductive strips respectively having an end portion, the end portions of each of the strips in the bank being substantially parallel to one another and arranged at an oblique angle to end portions of strips in at least one of the other banks. Each of the end portions has a tip extending to an interior portion of the leadframe device and separated from the other tips by a gap.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: February 11, 2014
    Assignee: NXP B.V.
    Inventor: Barry Lin
  • Patent number: 8648449
    Abstract: According to example configurations herein, a leadframe includes a connection interface. The connection interface can be configured for attaching an electrical circuit to the leadframe. The leadframe also can include a conductive path. The conductive path in the leadframe provides an electrical connection between a first electrical node of the electrical circuit and a second electrical node of the electrical circuit. Prior to making the connection between the electrical circuit and the leadframe, the first electrical node and the second electrical node can be electrically isolated from each other. Subsequent to making connection of the electrical circuit with the leadframe, the conductive path of the leadframe electrically connects the first electrical node and the second electrical node together. Accordingly, the leadframe provides connectivity between nodes of an electrical circuit in lieu of having to provide such connectivity at, for example, a metal interconnect layer of an integrated circuit device.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: February 11, 2014
    Assignee: International Rectifier Corporation
    Inventors: Gary D. Polhemus, Robert T. Carroll, Donald J. Desbiens
  • Patent number: 8258609
    Abstract: An integrated circuit package system is provided including forming a paddle having an integrated circuit die thereover, an outer lead, and an inner lead between the paddle and the outer lead. The integrated circuit package system is also provided including placing a lead support over the inner lead without traversing to an inner body bottom side of the inner lead, connecting the integrated circuit die and the inner lead, and encapsulating the inner lead having the lead support thereover and the inner lead exposed.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: September 4, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Jose Alvin Caparas, Arnel Trasporto
  • Patent number: 8241950
    Abstract: The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: August 14, 2012
    Assignee: Neuronexus Technologies, Inc.
    Inventors: David S. Pellinen, Jamille Farraye Hetke, Daryl R. Kipke, Kc Kong, Rio J. Vetter, Mayurachat Gulari
  • Patent number: 8173454
    Abstract: Disclosed is a light emitting diode package, including a metal body including a cavity for receiving a light emitting diode therein, a lens mount for mounting thereon a lens through which light is transmitted, a heat sink for dissipating heat, a lead insertion recess formed on a bottom surface of the metal body so that a lead is inserted therein, and a bonding hole formed to communicate with the lead insertion recess and passing through the cavity of the metal body; and a lead seated into the lead insertion recess of the metal body and insulation bonded to the bottom surface of the metal body by means of an insulating binder, so that an insulation type bonding relationship between the metal body and the lead is maintained stable. A method of manufacturing the light emitting diode package is also provided.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: May 8, 2012
    Assignee: Intops LED Co., Ltd.
    Inventors: Hyung Tae Kim, Yong Hun Choi, Nag Jong Choi
  • Publication number: 20120061809
    Abstract: Provided is a manufacturing method of a substrate for a semiconductor element, the manufacturing method including the steps of: providing a first photosensitive resin layer at a first surface of a metal plate; providing a second photosensitive resin layer at a second surface of the metal plate different from the first surface; forming a first etching mask for forming a connection post on the first surface of the metal plate; forming a second etching mask for forming a wiring post on the second surface of the metal plate; forming the connection post by performing an etching on the first surface of the metal plate from a first surface side to a midway of the metal plate; applying a premold resin in liquid form to the first surface of the metal plate which underwent the etching on the first surface; forming a premold resin layer by solidifying the premold resin in liquid form being applied; and forming a wiring pattern by performing an etching on the second surface of the metal plate from a second surface side.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 15, 2012
    Applicant: TOPPAN PRINTING CO., LTD
    Inventors: Junko TODA, Susumu Maniwa, Yasuhiro Sakai, Takehito Tsukamoto
  • Patent number: 8097933
    Abstract: A flexible semiconductor package includes a flexible substrate. A data chip is disposed over the flexible substrate. The data chip includes a data storage unit for storing data and first bonding pads that are electrically connected to the data storage unit. A control chip is disposed over the flexible substrate. The control chip includes a data processing unit for processing the data in the data chip and second bonding pads that are electrically connected to the data processing unit. Wirings are formed in order to electrically connect the first bonding pads to the second bonding pads.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: January 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Min Suk Suh
  • Patent number: 8017446
    Abstract: Method for manufacturing a rigid power module with a layer that is electrically insulating and conducts well thermally and has been deposited as a coating, the structure having sprayed-on particles that are fused to each other, of at least one material that is electrically insulating and conducts well thermally, having the following steps: manufacturing a one-piece lead frame; populating the lead frame with semiconductor devices, possible passive components, and bonding corresponding connections, inserting the thus populated lead frame into a compression mould so that accessibility of part areas of the lead frame is ensured, pressing a thermosetting compression moulding compound into the mould while enclosing the populated lead frame, coating the underside of the thus populated lead frame by thermal spraying in at least the electrically conducting areas and overlapping also the predominant areas of the spaces, filled with mold compound.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: September 13, 2011
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Ronald Eisele, Mathias Kock, Teoman Senyildiz
  • Patent number: 7871863
    Abstract: An integrated circuit package system is provided forming a lead from a padless lead frame, and encapsulating the lead for supporting an integrated circuit die with a first molding compound for encapsulation with a second molding compound.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: January 18, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Jose Alvin Caparas, Arnel Senosa Trasporto, Jeffrey D. Punzalan
  • Patent number: 7816771
    Abstract: The present invention provides a stacked chip package structure with leadframe having inner leads with transfer pad, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and vertically distant from the plurality of inner leads; an offset chip-stacked structure formed with a plurality of chips stacked together, the offset chip-stacked structure being set on the die pad and electrically connected to the plurality of inner leads arranged in rows facing each other; and an encapsulant covering the offset chip-stacked structure and the leadframe, the plurality of outer leads extending out of said encapsulant; the improvement of which being that the inner leads of the leadframe are coated with an insulating layer and a plurality of metal pads are selectively formed on the insulating layer.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: October 19, 2010
    Assignees: Chipmos Technologies Inc., Chipmos Technologies (Bermuda) Ltd.
    Inventors: Geng-Shin Shen, Wu-Chang Tu
  • Patent number: 7808096
    Abstract: A semiconductor package production method includes the step of die-cutting part of a lead side portion of a seal formed by molding and dam bars using a pedestal and punch. The pedestal has an outer surface at a position retreating from a side surface of an upper seal portion as far as possible and an inner surface generally near a side surface of a lower seal portion. Width Wa of the upper surface of the upper surface of the pedestal is smaller than the overhang size of the upper seal portion. Tip end region Ra of the lead side portion which is present right under the overhang portion of the upper seal portion has a slanted surface Fa1which is sloped inwardly from top to bottom.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: October 5, 2010
    Assignee: Panasonic Corporation
    Inventors: Hisaho Inao, Tatsuya Hirano, Katsutoshi Shimizu
  • Patent number: 7791178
    Abstract: A lead frame unit, a semiconductor package having a lead frame unit, a stacked semiconductor package having a semiconductor package, and methods of manufacturing the same are provided. The lead frame unit in a stacked semiconductor package may include a die pad supporting a semiconductor chip, an inner lead electrically connected to the semiconductor chip, an outer lead extending from the inner lead, and a heat-resistant insulation member surrounding the connection portion. The outer lead may include a connection portion connected to the inner lead and a junction portion connected to the connection portion and a circuit board. An external signal may be applied to the junction portion. If the lead frame unit is used in the stacked semiconductor package, the outer lead and a dummy outer lead in the stacked semiconductor package may have substantially the same shape.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: September 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-Jae Bang, Heui-Seog Kim, Seong-Chan Han, Jung-Hyeon Kim, Sung-Hwan Kim
  • Patent number: 7759778
    Abstract: A leaded semiconductor power module includes a first heatsink, an electrically insulated substrate thermally coupled to the first heatsink, one or more semiconductor chips, a leadframe substrate, and a second heatsink thermally coupled to the leadframe substrate, the assembly being overmolded with an encapsulant to expose the first heatsink, the second heatsink and peripheral terminals of the leadframe substrate. The semiconductor chips are electrically and structurally coupled to both the insulated substrate and the leadframe substrate, and conductive spacers electrically and structurally couple the insulated substrate to the leadframe substrate.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: July 20, 2010
    Assignee: Delphi Technologies, Inc.
    Inventors: Michael J. Lowry, Eric A. Brauer, Thomas A. Degenkolb, Victor C. M. Wong
  • Patent number: 7683477
    Abstract: A semiconductor device is disclosed. One embodiment provides a device including a carrier, an electrically insulating layer arranged over the carrier and a first semiconductor chip arranged over the electrically insulating layer, wherein the first semiconductor chip has a first contact element on a first surface and a second contact element on a second surface.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: March 23, 2010
    Assignee: Infineon Technologies AG
    Inventor: Ralf Otremba
  • Patent number: 7671382
    Abstract: A semiconductor device which includes a radiating plate, a wiring patterned layer on the radiating plate via an insulating layer, at least one semiconductor chip mounted on the wiring patterned layer. The semiconductor chip has a surface electrode. The semiconductor device further includes a conductive lead plate electrically connected with the surface electrode of the semiconductor chip, and a resin package of thermoplastic resin having anisotropic linear expansion coefficient varying based upon directions. The resin package covers the wiring patterned layer, the semiconductor chip, the conductive lead plate, and at least a portion of the radiating plate. The conductive lead plate extends in a direction which provides the resin package with the maximum linear expansion coefficient. In the semiconductor device so structured, the warpage of the resin package is reduced both in longitudinal and transverse directions.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: March 2, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shingo Sudo, Tatsuo Ota, Nobutake Taniguchi, Hiroshi Yoshida, Hironori Kashimoto
  • Patent number: 7671453
    Abstract: A semiconductor device in which chips are resin-molded, including: frames having front and back surfaces and die pads; power chips mounted on the surfaces of the die pads; an insulation resin sheet having a first and a second surfaces which are opposed against each other, the resin sheet being disposed such that the back surfaces of the die pads contact the first surface of the resin sheet; and a mold resin applied on the first surface of the resin sheet so as to seal up the power chips. The thermal conductivity of the resin sheet is larger than that of the mold resin.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: March 2, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kenichi Hayashi, Hisashi Kawafuji, Tatsuyuki Takeshita, Nobuhito Funakoshi, Hiroyuki Ozaki, Kazuhiro Tada
  • Publication number: 20100025864
    Abstract: A wirebond interconnect structure, having ground pads and signal pads, to which wirebonds are electrically coupled, disposed on a component, is provided and includes a first coating to insulate at least the wirebonds and the signal pads with at least the ground pads exposed, and a second coating, surrounding the first coating, in electrical communication with the ground pads. The first coating is sufficiently thick to achieve a consistent characteristic impedance when the second coating is applied.
    Type: Application
    Filed: July 31, 2008
    Publication date: February 4, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark J. Bailey, Gerald K. Bartley, Darryl J. Becker, Paul E. Dahlen, Philip R. Germann, Andrew B. Maki, Mark O. Maxson
  • Publication number: 20090294948
    Abstract: The present description provides increased contrast between interposer and leads in a stack embodiment that employs an interposer that extends beyond a boundary or perimeter established by the leads of the constituent IC devices.
    Type: Application
    Filed: August 10, 2009
    Publication date: December 3, 2009
    Inventors: Julian Partridge, Roel Perez, Leland Szewerenko
  • Patent number: 7575957
    Abstract: A leadless semiconductor package mainly includes a plurality of inner leads, a chip pad, a semiconductor chip and a molding compound. A non-conductive ink is filled between every two of the inner leads, and couples the inner leads to the chip pad so as to be in replacement of the conventional tie bars. The semiconductor chip is disposed on the chip pad and electrically connected to the inner leads. Moreover, the molding compound is formed on the inner leads and the non-conductive ink for encapsulating the semiconductor chip. The non-conductive ink prevents the exposed bottom surfaces of the inner leads from contamination by the molding compound without attaching an external tape during molding. Also the inner leads can be in a multi-row arrangement and the chip pad can be disposed in an optional location.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: August 18, 2009
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yao-Ting Huang, Chih-Te Lin
  • Patent number: 7573129
    Abstract: The present description provides increased contrast between interposer and leads in a stack embodiment that employs an interposer that extends beyond a boundary or perimeter established by the leads of the constituent IC devices.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: August 11, 2009
    Assignee: Entorian Technologies, LP
    Inventors: Julian Partridge, Roel Perez, Leland Szewerenko
  • Publication number: 20090102068
    Abstract: The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason.
    Type: Application
    Filed: May 30, 2008
    Publication date: April 23, 2009
    Inventors: David S. Pellinen, Jamille Farraye Hetke, Daryl R. Kipke, K. C. Kong, Rio J. Vetter, Mayurachat Gulari
  • Publication number: 20090014894
    Abstract: A stacked semiconductor device includes a first semiconductor element mounted on a wiring board and a second semiconductor element stacked on the first semiconductor element. Electrode pads of the first and second semiconductor elements are electrically connected to connection pads of the wiring board via first and second metal wires. The second metal wire is wired so that a part thereof is in contact with an insulating protective film covering a surface of the first semiconductor element.
    Type: Application
    Filed: July 9, 2008
    Publication date: January 15, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuhiro Ishida, Ryoji Matsushima
  • Patent number: 7476913
    Abstract: A light emitting device has a cup portion with a bottom surface opening, and one electrode of a light emitting element is connected to the cup portion. The other electrode of the light emitting element is connected to a lead set up from an inner space to outside the cup portion using the opening of the cup portion. Each electrode and lead of the light emitting device can be electrically connected without bonding wires. This prevents shadows or light unevenness from reflecting the shape of the bonding wire, thereby enhancing light-emission efficiency. As an alternative to setting up the lead from inside to the outside of the cup portion, the lead existing outside the cup portion and the other electrode are electrically connected via the bonding wire through the cup portion's opening. Thus, light outputted outside of the light emitting device is not intercepted by the bonding wire.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: January 13, 2009
    Assignees: Renesas Technology Corp., Hitachi Cable Precision Co., Ltd., Hitachi Cable, Ltd.
    Inventors: Hiroyuki Isobe, Gen Murakami, Toshikatsu Hiroe
  • Patent number: 7473999
    Abstract: A semiconductor chip comprises a first MOS device, a second MOS device, a first metallization structure connected to said first MOS device, a second metallization structure connected to said second MOS device, a passivation layer over said first and second MOS devices and over said first and second metallization structures, and a third metallization structure connecting said first and second metallization structures.
    Type: Grant
    Filed: September 24, 2006
    Date of Patent: January 6, 2009
    Assignee: MEGICA Corporation
    Inventors: Mou-Shiung Lin, Chien-Kang Chou, Hsin-Jung Lo
  • Publication number: 20080067648
    Abstract: The invention discloses integrated circuits (ICs), molded IC packages, and to leadframe arrays, package arrays and methods for their manufacture. Leadframe arrays and package arrays used for the manufacture of IC packages by transfer molding processes include a locking feature adapted for encapsulation. The locking feature is situated in a strap of the leadframe array overlying a gate between mold cavities. The strap lock formed by curing encapsulant in the locking feature of the strap strengthens the resulting package array and provides improved mold extraction and handling characteristics.
    Type: Application
    Filed: September 18, 2007
    Publication date: March 20, 2008
    Inventor: James R. Huckabee
  • Patent number: 7345356
    Abstract: Packages for an optical integrated circuit die and a method for making such packages are disclosed. The package includes a die, a die pad, a plurality of lead fingers, and an encapsulating dielectric material. The downward second pad surface of the die pad bearing an integrated circuit is encapsulated by a bottom encapsulating dielectric material. The top encapsulating dielectric material provides the function for protecting the leadframe from severe environment. The top encapsulating dielectric material can be neglected if there is no threat on the integrated circuit die and the leadframe. Multiple of lead fingers are mounted on the printed circuit board. A portion of the printed circuit board is removed in order to provide an optical path for the light beam transmitted from a light source through the transparent bottom encapsulating dielectric material into the integrated circuit die. The method of making a package includes forming a leadframe including a die pad and a plurality of lead fingers.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: March 18, 2008
    Assignee: Capella Microsystems Corp.
    Inventor: Chih-Cheng Chien
  • Patent number: 7304371
    Abstract: A lead frame may include a plurality of leads, each having a bonding portion electrically connected to a semiconductor chip and an attaching portion. A tape may be provided on the attaching portions of the leads. The attaching portion of each lead may have a width that is smaller than the width of another portion of the lead. A plating layer may be provided on the attaching portion. The lead frame may be implemented in a semiconductor package.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: December 4, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hun Kim, Jong-Bo Shim, Tae-Je Cho
  • Patent number: 7298026
    Abstract: A method for fabricating a large die package with a leadframe having leads and a paddle is provided. An interposer is attached onto the leadframe with the interposer extending over at least a portion of the paddle and at least a portion of the leads of the lead-frame. The interposer is insulated from the leads. A die is attached to the interposer.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: November 20, 2007
    Assignee: Stats Chippac Ltd.
    Inventors: Il Kwon Shim, Jeffrey D. Punzalan, Keng Kiat Lau
  • Patent number: 7129568
    Abstract: A chip package has lead frame, chip, generic wires, at least one characterized wire, ground wires and insulation material. The lead frame includes die pad, generic leads and at least a characterized lead structure. Generic leads and the characterized lead structure are aligned at peripheral region of the die pad. The characterized lead structure has a cross-sectional area perpendicular to the direction where signals transmit, which is larger than each generic lead. The chip is on the die pad. The generic wires connect the chip to the generic leads. The characterized wire connects the chip to the characterized lead structure. The characterized wire is for transmitting an identical signal between the chip and the characterized lead structure. Ground wires connect the chip to the die pad, and are located at both sides of the characterized wires. The insulation material encapsulates lead frame, chip, generic wires, characterized wire and ground wires.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: October 31, 2006
    Assignee: VIA Technologies, Inc.
    Inventors: Sheng-Yuan Lee, Chi-Hsing Hsu
  • Patent number: 7105916
    Abstract: Provided are an inlet for an electronic tag comprising an insulating film, antennas each made of a conductor layer and formed over one surface of the insulating film, a slit formed in a portion of each of the antennas and having one end extending toward the outer edge of the antenna, a semiconductor chip electrically connected with each of the antennas via a plurality of bump electrodes, and a resin for sealing the semiconductor chip therewith; and a manufacturing process of the inlet. By the present invention, formation of a thin and highly-reliable inlet for a non-contact type electronic tag can be actualized.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: September 12, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Michio Okamoto, Yuichi Morinaga, Yuji Ikeda, Takeshi Saito