Abstract: A semiconductor package structure including a chip and a leadframe unit is provided. The chip has an active surface and a plurality of recesses disposed thereon. The leadframe unit has at least one packaging area in which the chip is disposed. The packaging area has a plurality of leads on the peripheral portion thereof, wherein each of the leads has a first end fastened on the peripheral portion of the packaging area and a second end extending inward to the active surface of the chip. The leads have a plurality of protrusions, which are capable of being contained by the recesses, located on the second ends to electrically connect the chip and the leadframe unit.

Abstract: A semiconductor integrated circuit device includes a die pad and a semiconductor chip mounted over the die pad, having a main surface with surface electrodes and a back surface. Suspension leads support the die pad, and leads are arranged around the semiconductor chip, each of the leads having inner and outer lead portions. A first plating layer is formed at a part of the inner lead portions and a second plating layer is formed over the outer lead portion. Wires electrically connect the surface electrodes with the inner lead portions through the first plating layer. A resin body seals the die pad, the chip, the wires and the inner lead portions. The second plating layer is comprised of different materials than the first plating layer, and is a Pb-free metal layer.

Abstract: A method of producing a leadframe is provided, the method including the steps of providing a substrate, plating the substrate with a layer of tin, plating a layer of nickel over the layer of tin, and thereafter plating one or more protective layers over the layer of nickel. The leadframe may thereafter be heated to produce one or more intermetallic layers comprising tin, which impedes the out-diffusion of copper from a base material of the leadframe to the surface thereof.

Abstract: A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed from the copper itself of the copper of the leadframe. This may be achieved by punching dimples into one surface of the copper plate of the leadframe before plating to form protrusions on the opposing surface. This method of forming the rounded protrusions simplifies the process of forming stand-offs. The protrusions provide a structure that increases wetting area and allows the use of a larger quantity of solder for increased solder joint thickness and better die paddle solder joint area coverage. As a result of the increased solder joint thickness, second level fatigue life is significantly improved.

Abstract: A lead frame includes a plurality of leads electrically connected to a semiconductor chip and a lead lock including a base layer disposed over the plurality of the leads and formed of a material having a coefficient of thermal expansion similar to that of inner leads. An adhesive layer is disposed between the base layer and the plurality of leads to fix the plurality of leads and adhere the base layer to the leads. At least one line electrically connects the semiconductor chip to the base layer of the lead lock. Since regions for bus bars are replaced by the lead lock and are removed, the lead frame can be miniaturized and has superior thermal stability and dimension stability.

Abstract: A method of fabricating a vertical structure opto-electronic device includes fabricating a plurality of vertical structure opto-electronic devices on a crystal substrate, and then removing the substrate using a laser lift-off process. The method then fabricates a metal support structure in place of the substrate. In one aspect, the step of fabricating a metal support structure in place of the substrate includes the step of plating the metal support structure using at least one of electroplating and electro-less plating. In one aspect, the vertical structure is a GaN-based vertical structure, the crystal substrate includes sapphire and the metal support structure includes copper. Advantages of the invention include fabricating vertical structure LEDs suitable for mass production with high reliability and high yield.

Abstract: A method (300) for fabricating a lead frame (100), comprising forming a plurality of external leads (122) in a lead frame material (108), plating a metal (222) on all surfaces of the lead frame material (108), and subsequently forming a plurality of internal leads (124) in the lead frame material (108). The lead frame material (108) may comprise of a portion of a contiguous metal sheeting (204) rolled upon a first coil (202), wherein the contiguous metal sheeting (204) is fed into an external lead stamping apparatus (206), thus forming the external leads (122), and rolled onto a second coil (215). The portion is fed into a plating apparatus and plated with the metal (222), and rolled onto a third coil (218) prior to forming the plurality of internal leads (124). The third coil (218) can be unrolled into an internal lead stamping apparatus (226), thus forming the internal leads (124) of a lead frame (100).

Abstract: A process includes annealing one or more plated conductive leads at a predetermined temperature. The one or more plated conductive leads are plated with one or more layers, where each layer comprises a material. The predetermined temperature is greater than or equal to approximately a melting point of one of the materials. The annealing can reduce growth formations, such as whiskers, on the one or more conductive leads. Lead frames and other devices having plated conductive leads may be subjected to the process, and the resultant plated conductive leads will have fewer growth formations than plated conductive leads not subjected to the process. The plated conductive leads may be trimmed and formed prior to or after the anneal.

Abstract: Fabrication of a semiconductor package includes placing a conductive material on a protrusion from a leadframe to form a first assembly, forming a non-conductive mask about the protrusion, and placing a die on the first assembly, the die having an active area. Fabrication can further include reflowing the conductive material to form a second assembly such that a connection extends from the die active area, through the conductive material, to the protrusion. A semiconductor package includes a leadframe having a protrusion, a conductive material reflowed to the protrusion, and a die having an active area coupled to the protrusion by the reflowed solder.

Abstract: A semiconductor device comprises a semiconductor die, first and second electrically-conductive leads and first and second thermal elements. The die comprises first and second surfaces. The first lead is held in contact with the first surface of the die by a compressive force. The first thermal element is held in contact with a portion of the first lead by a compressive force such that the first thermal element is capable of removing heat from the first lead and from the die. The second lead is held in contact with the second surface of the die by a compressive force. The second thermal element is held in contact with a portion of the second lead by a compressive force such that the second thermal element is capable of removing heat from the second lead and from the die.

Abstract: A semiconductor device includes a semiconductor element; a group of back-inner terminals coupled with the semiconductor element through bonding wires and arranged in an area array shape so as to be exposed inside of the bottom; a group of back-outer terminals arranged outside the group of back-inner terminals; a group of front-outer terminals located immediately above the back-outer terminals to be exposed from the front surface, which are electrically coupled with the back-outer terminals located immediately therebelow through coupling conductors, respectively; and a sealing resin which seals the semiconductor element and bonding wires and non-exposed portions of said back-inner terminals, back-outer terminals and front-outer terminals. On at least the respective terminal faces of said back-inner terminals, back-outer terminals and front-outer terminals, noble-metal plated layers are formed.

Abstract: A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrically connected to the tabs. An encapsulant is applied to the upper and side surfaces of the leadframe. Finally, the leadframe is cut in situ so that the die pad and tabs are severed from the frame, the sides of the package are formed, and the package is severed from the leadframe.

Abstract: A leadframe for a semiconductor device of the present invention is a leadframe for a semiconductor device having a stage section where a semiconductor chip is to be mounted, an inner lead section connected to the stage section, and an outer lead section connected to the inner lead section. The leadframe has (1) a nickel (Ni) layer 1, (2) a palladium (Pd) or palladium alloy layer 2, (3) a tin (Sn) or tin alloy layer or a zinc (Zn) or zinc alloy layer 3, 3a, or 3b, and (4) a gold (Au) layer 4, 4a, or 4b, all of which are formed on a base material B forming the leadframe in sequence from the surface of the leadframe.

Abstract: A leadframe with a base metal structure (for example, copper) and first and second surfaces. A first metal layer, which is adhesive to polymeric materials such as molding compounds, is adherent to the first leadframe surface. The second leadframe surface is covered by a second metal layer for affinity to reflow metals such as tin alloy; this second metal layer has a different composition from the first metal layer. One example of the first surface is a nickel layer (201) in contact with the base metal (105), a palladium layer (202) in contact with the nickel layer, and an outermost tin layer (203) in contact with the palladium. Another example is an oxidized surface of the base metal. The second metal layer, on the second leadframe surface, comprises a nickel layer (201) in contact with the base metal (105), a palladium layer (202) in contact with the nickel layer, and an outermost gold layer (204) in contact with the palladium layer.

Abstract: A lead frame for a semiconductor package having not only high molding resin adhesiveness and a low delamination problem under a severe moisture absorbing atmosphere but also high interface adhesiveness and solder wettability of an Au wire, and a method of manufacturing the lead frame are provided. The lead frame includes a base metal layer formed of a metal and a plurality of plating layers having different components formed on at least a surface of the base metal layer, wherein the plating layers include, a Ni plating layer deposited on at least a surface of the base metal layer and formed of Ni or an Ni alloy, a Pd plating layer stacked on at least a surface of the Ni plating layer and formed of Pd or a Pd alloy, and a protection plating layer stacked on at least a surface of the Pd plating layer and formed of Au or an Au alloy, wherein the Ni plating layer is formed to have a predetermined a thickness and a surface coarseness.

Abstract: A surface mount resistor includes an elongated piece of resistive material having strips of conductive material attached to its opposite ends. The strips of conductive material are separated to create an exposed central portion of the resistive material therebetween. According to the method the resistive strip is attached to a single co extensive strip of conductive material and a central portion of the conductive material is removed to create the exposed central portion of the resistive strip.

Abstract: A semiconductor device having a leadframe comprised of a base metal (110, e.g., copper), a chip mount pad (103) and a plurality of lead segments (104). Each of the segments has a first end (104a) near the mount pad and a second end (104b) remote from the mount pad. The device further has a semiconductor chip (103) attached to the mount pad and electrical interconnections (107) between the chip and the first segment ends. Encapsulation material (120) covers the chip, the bonding wires and the first segment ends, yet leaves the second segment ends exposed. At least portions of the second segment ends have the base metal covered by a layer of solderable metal (130, e.g., nickel) and by an outermost layer of noble metal (140, e.g., stack of palladium and gold).

Abstract: The present invention provides a light emitting diode (LED) package and the fabrication method thereof. The LED package includes a lower metal layer, and a first silicon layer, a first insulation layer, a second silicon layer, a second insulation layer, and a package electrode pattern formed in their order on the lower metal layer. The LED package also includes a spacer having a cavity, formed on the electrode pattern. The LED package further includes an LED mounted in the cavity by flip-chip bonding to the electrode patterns, and an optical element attached to the upper surface of the spacer.

Abstract: A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (302) and a plurality of lead segments (303). Covering the base metal are, consecutively, a continuous nickel layer (201) on the base metal, a layer of palladium on the nickel, wherein the palladium layer (203) on the chip side of the structure is thicker than the palladium layer (202) opposite the chip, and a gold layer (204) on the palladium layer (202) opposite the chip. A semiconductor chip (310) is attached to the chip mount pad and conductive connections (312) span from the chip to the lead segments. Polymeric encapsulation compound (320) covers the chip, the connections, and portions of the lead segments, but leaves other segment portions available for solder reflow attachment to external parts.

Abstract: A method (300) for fabricating a lead frame (100), comprising forming a plurality of external leads (122) in a lead frame material (108), plating a metal (222) on all surfaces of the lead frame material (108), and subsequently forming a plurality of internal leads (124) in the lead frame material (108). The lead frame material (108) may comprise of a portion of a contiguous metal sheeting (204) rolled upon a first coil (202), wherein the contiguous metal sheeting (204) is fed into an external lead stamping apparatus (206), thus forming the external leads (122), and rolled onto a second coil (215). The portion is fed into a plating apparatus and plated with the metal (222), and rolled onto a third coil (218) prior to forming the plurality of internal leads (124). The third coil (218) can be unrolled into an internal lead stamping apparatus (226), thus forming the internal leads (124) of a lead frame (100).

Abstract: In an example embodiment, the semiconductor device comprises a carrier and a semiconductor element, such as an integrated circuit. The carrier is provided with apertures, thereby defining connecting conductors having side faces. Notches are present in the side faces. The semiconductor element is enclosed in an encapsulation that extends into the notches in the carrier. As a result, the encapsulation is mechanically anchored in the carrier. The semiconductor device can be made in a process wherein, after the encapsulating step, no lithographic steps are necessary.

Abstract: A semiconductor package comprising a semiconductor die which has opposed first and second surfaces and at least first and second bond pads disposed on the second surface thereof. In addition to the semiconductor die, the semiconductor package includes at least one lead having opposed first and second surfaces, the first surface of the lead being electrically connected to the first bond pad. Also included in the semiconductor package is at least one conductive post having opposed first and second surfaces, the first surface of the conductive post being electrically connected to the second bond pad. A package body at least partially encapsulates the semiconductor die, the lead, and the conductive post such that the second surface of the lead and the second surface of the conductive post are exposed in a common exterior surface of the package body.

Abstract: A chip packaging structure adapted to reduce EMI includes a chip having contacts provided on one side thereof, and a leadframe having a plurality of leads arranged in a predetermined manner and provided at a bottom side with a conducting protrusion each for electrically connecting to external elements. The leadframe is fixedly attached to one side of the chip having the contacts provided thereon, and the leads are electrically connected at inner ends to the contacts via lead wires. An adhesive layer is applied to one side of the leadframe having the protrusions to thereby adhere a conducting layer to the leadframe with the protrusions downward extended through multiple through holes on the conducting layer; and at least one of the contacts on the chip is electrically connected to the conducting layer for the latter to serve as a ground or a power plane.

Abstract: A carrier has a metal area that is essentially composed of copper. A chip has a rear side metallization layer. A buffer layer, essentially composed of nickel and having a thickness of between 5 ?m and 10 ?m, is arranged on the metal area. The chip does not have a chip housing and is arranged on the metal area, which has been provided with the buffer layer, such that only one connecting medium is arranged between the rear side metallization layer of the chip and the buffer layer.