For Flat Cards, E.g., Credit Cards (epo) Patents (Class 257/E23.064)
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Patent number: 7348662Abstract: A composite multi-layer substrate comprising a flat plate-like core member formed of a material having an excellent electric conductivity, an excellent heat conductivity, and a high rigidity, a front resin layer and a rear resin layer covering at least the front and rear surfaces of the core member, and a bottomless hole formed in the core member through the front and rear sides of the core member, wherein an electronic component is installed in the bottomless hole, whereby since the strength of the composite multi-layer substrate can be assured by the rigidity of the core member, conventional prior art glass cloth can be eliminated, deterioration in the electric characteristics caused by ion migration can be avoided and will result in reduced production cost.Type: GrantFiled: May 27, 2003Date of Patent: March 25, 2008Assignee: Taiyo Yuden Co., Ltd.Inventors: Masashi Miyazaki, Mitsuhiro Takayama, Tatsuro Sawatari
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Patent number: 7332798Abstract: Provided is a non-contact ID card which is superior in the productivity and the electrical properties, and a method capable of manufacturing such non-contact ID card. The non-contact ID card of the present invention is characterized in that the non-contact ID card comprises an antenna circuit board in which an antenna is formed on a substrate and an interposer board in which an enlarged electrode, which is connected to an electrode of an IC chip, is formed on a substrate on which the IC chip is mounted. The non-contact ID card is formed by laminating both boards in such a manner that the electrode of the antenna and the enlarged electrode are bonded, in which both electrodes are adhesively bonded by an insulating adhesive filled in minute recesses dispersed on bonding faces of the electrode of the antenna and/or the enlarged electrode.Type: GrantFiled: November 9, 2004Date of Patent: February 19, 2008Assignee: Toray Engineering Company, LimitedInventors: Masanori Akita, Yoshiki Sawaki
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Patent number: 7320738Abstract: Method for conditioning of an electronic microcircuit designed for the production of an electronic module which can be glued by means of a simple glue or by soldering. For this purpose the microchip has a geometric shape compatible with a recess in a card provided to accommodate it and has a means serving as a mask compatible with the card. Ultimately this mask also serves to prevent an outflow of a resin coating used to protect a chip included in this type of module. The mask is glued to a support having, on a first face, the contact area, and on a second face the mask and the chip. The mask includes a window determining the placement of the chip.Type: GrantFiled: April 16, 2003Date of Patent: January 22, 2008Assignee: FCIInventors: Jean-Pierre Radenne, Yannick De Maquille, Jean-Jacques Mischler, Christophe Mathieu
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Patent number: 7312528Abstract: A semiconductor device includes first and second antenna connection electrodes placed on the periphery of a semiconductor chip, an on-chip antenna connection electrode placed in the inner area of the semiconductor chip compared to the first and second antenna connection electrodes, and an internal circuit formed in the semiconductor chip. The first and second antenna connection electrodes are connected to the internal circuit by internal lines. The on-chip antenna connection electrode is connected to the internal circuit and the second antenna connection electrode by internal lines. An on-chip antenna is connected to the second antenna connection electrode and the on-chip antenna connection electrode. An external antenna is connected to the first and second antenna connection electrodes.Type: GrantFiled: February 17, 2004Date of Patent: December 25, 2007Assignee: Hitachi Maxell, Ltd.Inventors: Hiroto Watanabe, Osamu Nakayama, Osamu Shiratsuchi, Kazuhiko Daido
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Publication number: 20070267732Abstract: A circuit card module and a method for fabricating the same are disclosed. The present invention includes the steps of providing a carrier having at least a first carrying region and a second carrying region that are co-planar; respectively mounting a substrate electrically connected to a first chip on the first carrying region, and a second chip electrically connected the substrate on the second carrying region, wherein the substrate is provided with at least an area of electrical connecting portion for being connected with external devices so as to reduce areas required for mounting a larger substrate or another substrate, thereby allowing a circuit card module to be fabricated with a minimized substrate.Type: ApplicationFiled: May 8, 2007Publication date: November 22, 2007Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Toniady Tan, Cheng-Chung Yu, Hung-Chi Wei, Chih-Hou Chang, Huan-Shiang Li
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Patent number: 7294917Abstract: The present invention provides an IC tag which has a structure comprising a first adhesive layer laminated on a surface of a substrate sheet, an electronic circuit containing a circuit line having a bypass line and an IC chip connecting to the electronic circuit which are formed on a surface of the first adhesive layer, a second adhesive layer laminated for covering the electronic circuit and the IC chip, and a release agent layer formed partly at the position corresponding to a circuit section consisting of the electronic circuit and the IC chip and located at the interface between the substrate sheet and the first adhesive layer, wherein the angle formed by the tangent of the bypass line at the connection between the bypass line and the circuit line and the tangent of the circuit line at the connection is 10 degree or greater. When the IC tag attached to an article is peeled off, the built-in electronic circuit is surely broken.Type: GrantFiled: November 20, 2003Date of Patent: November 13, 2007Assignee: Lintec CorporationInventors: Taiga Matsushita, Masateru Yamakage, Yasukazu Nakata
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Patent number: 7288834Abstract: The semiconductor device has a security coating with embedded magnetic particles and magnetoresistive sensors. This renders possible a measurement of the impedance of security elements defined by magnetoresistive sensors and security coating. If initial values of the impedance are stored, actual values can be compared therewith to see if the device has not been electrically probed or modified. Such a comparison can be used to check the authenticity of the device.Type: GrantFiled: December 8, 2005Date of Patent: October 30, 2007Assignee: NXP B.V.Inventors: Petra Elisabeth De Jongh, Reinder Coehoorn, Nynke Anne Martine Verhaegh
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Patent number: 7264992Abstract: A removable Flash integrated memory module card has a plastic shell and an integral Flash memory module. On the backside of the card, there are exposed contact pads. When the card is inserted into a card-hosting device, the card can communicate with the device through the exposed pads. The manufacturing method includes manufacturing of the memory module and utilizing plastic molding techniques for making the card outer body. The method involves preparing the substrate, mounting the components, testing the module, preparing the molding device, and molding the card body.Type: GrantFiled: August 6, 2004Date of Patent: September 4, 2007Inventors: Paul Hsueh, Jim Ni, Sun-Teck See, Kuang-Yu Wang
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Publication number: 20070176273Abstract: The invention relates to a card for contactless data and/or energy transmission by means of external devices, containing a multilayer card body which has a substrate layer for accommodating an antenna coil having exposed coil connections on a top side of the substrate layer which are connected in an electrically conductive manner to connections for a chip module containing a chip, the chip being enclosed in a recess in the substrate layer; the windings of the antenna coil extend on the top side of the substrate layer, and a compensation layer extends on the top side of the substrate layer; the compensation layer has a chip module opening for placing the chip module on the substrate layer, and has a bridge opening for the contacting of connections of an antenna bridge which extends transverse to the windings.Type: ApplicationFiled: December 18, 2006Publication date: August 2, 2007Applicant: VISIONCARD PERSONALISIERUNGSGMBHInventor: Robert Wolny
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Patent number: 7239024Abstract: A semiconductor package is disclosed with a recess (51) for an integrated circuit die (52). The recess is made by bending or deforming all layers of a package substrate, and therefore the recess contains circuitry to connect to the integrated circuit die. The integrated circuit die is electrically connected to the package substrate by either wirebonds (53a), TAB or die solder balls (53b). The package substrate (50), a single sided printed wiring board, has a thick metal core (100) and one or more thin build up layers.Type: GrantFiled: November 19, 2003Date of Patent: July 3, 2007Inventor: Thomas Joel Massingill
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Publication number: 20070126101Abstract: A memory card module includes a first circuit board, and a second circuit board. On one surface of the first circuit board, there are flash memories and a controller. The second circuit board is installed at one end of the first circuit board and is electrically connected with the first circuit board so as to form a transmitting interface port. On a first surface of the second circuit board, there are a plurality of interface connecting points. On a second surface of the second circuit board, part of the second surface is hollowed out. A space formed between the hollowed out area and the corresponding first circuit board increases the area for circuit layouts and the mounting components for the first circuit board. Therefore, quantity of accommodated memory components may be increased so as to increase the total storage capacity of the memory card under limitation of small dimensions.Type: ApplicationFiled: December 5, 2006Publication date: June 7, 2007Applicants: A-DATA TECHNOLOGY CO., LTD., PING-YANG CHUANGInventor: Ping-Yang Chuang
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Publication number: 20070126100Abstract: Wiring lines for the supply of a voltage to feed a drive voltage to an integrated circuit formed in a semiconductor chip are disposed so as to cover a main surface of the semiconductor chip, so that, if the wiring lines are removed for the purpose of analyzing information stored in the semiconductor chip, the integrated circuit does not operates and it is impossible to analyze the information. Further, there is provided a processing detector circuit for detecting that the wiring lines have been tampered with. When the processing detector circuit detects a change in the sate of the wiring lines, the integrated circuit is reset. Thus, it is possible to improve the security of information stored on the card.Type: ApplicationFiled: November 1, 2006Publication date: June 7, 2007Inventors: Hirotaka Mizuno, Yoshio Masumura, Takeo Kon, Yukio Kawashima
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Publication number: 20070114647Abstract: A carrier board structure with a semiconductor chip embedded therein is provided, which includes a carrier board having a first surface with at least one opening and a second surface. Allowing a semiconductor chip to be embedded in the opening in a manner that the active surface of the semiconductor chip is slightly lower than the first surface of carrier board. An adhesive material is used to fill in the gap between the carrier board and the semiconductor chip, and to cover a part of the active surface of the semiconductor chip for fixing the semiconductor chip in the opening. As the adhesive material is used to surround the periphery of the semiconductor chip, and the gap between the semiconductor chip and the carrier board can completely filled with the adhesive material without formation of voids therein, the semiconductor chip can be free from cracking issue. Further, the popcorn effect of the carrier board can be prevented form occurrence.Type: ApplicationFiled: June 20, 2006Publication date: May 24, 2007Inventor: Shih-Ping Hsu
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Patent number: 7208823Abstract: A semiconductor arrangement is disclosed, having transistors based on organic semiconductors and non-volatile read/write memory cells. The invention relates to a semiconductor arrangement, constructed from transistors, in the case of which the semiconductor path is composed of an organic semiconductor, and memory cells based on a ferroelectric effect perferably in a polymer, for use in RF-ID tags, for example.Type: GrantFiled: November 15, 2002Date of Patent: April 24, 2007Assignee: Infineon Technologies AGInventors: Gunter Schmid, Marcus Halik, Hagen Klauk
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Patent number: 7193305Abstract: A memory card comprising a leadframe having a die pad, and an insert having a plurality of contacts. Attached to the die pad is a semiconductor die which is electrically connected to the contacts of the insert. A body covers the die pad and the semiconductor die and partially covers the insert such that the contacts are exposed in an exterior surface of the body.Type: GrantFiled: November 3, 2004Date of Patent: March 20, 2007Assignee: Amkor Technology, Inc.Inventors: Jeffrey Alan Miks, Curtis Michael Zwenger, Brenda Concepcion Gogue, Stephen Gregory Shermer, Maximilien Jouchin d'Estries
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Publication number: 20070035000Abstract: A semiconductor device includes: a semiconductor substrate having an active face; a first electrode provided on or above the active face; an external connection terminal provided on or above the active face and electrically connected to the first electrode; and a connection terminal provided on or above the active face of the semiconductor substrate.Type: ApplicationFiled: August 7, 2006Publication date: February 15, 2007Inventor: Nobuaki Hashimoto
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Publication number: 20070034999Abstract: A chip module and to a chip card with a chip module which can be bent in such a way that a cross-sectional area runs along the greatest curvature of the bending line and parallel to one side of the chip module or the chip card. The module comprises contact areas within a surrounding line which are arranged in a plane perpendicular to the cross-sectional area, the surrounding line comprising a first line portion, which is adjacent the cross-sectional area, and a second line portion, which is opposite the first line portion. Furthermore, the module comprises a component, which is positioned in such a way that a first distance between the component and the first line portion is greater than a second distance between the component and the second line portion.Type: ApplicationFiled: August 11, 2006Publication date: February 15, 2007Applicant: INFINEON TECHNOLOGIES AGInventors: Peter Stampka, Frank Puschner, Erik Heinemann, Birgit Binder
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Publication number: 20070023885Abstract: The productivity of an IC card is to be improved. In a memory card of the type in which a memory body having a wiring substrate and a semiconductor chip mounted on a main surface of the wiring substrate is held so as to be sandwiched in between a first case and a second case, a planar outline of the memory body is smaller than half of a planar outline of the memory card. The memory body is disposed so as to be positioned closer to a first end side as one short side of the memory card with respect to a midline between the first end side and a second end side as an opposite short side of the memory card positioned on the side opposite to the first end side. The other area than the memory body-disposed area in the first and the second case is used as another functional area.Type: ApplicationFiled: September 28, 2006Publication date: February 1, 2007Inventors: Hirotaka Nishizawa, Kenji Osawa, Akira Higuchi, Junichiro Osako, Tamaki Wada
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Patent number: 7170162Abstract: A chip embedded package structure is provided. A stiffener is disposed on a tape. The tape has at least an alignment mark and the stiffener has at least a chip opening. A chip having a plurality of bonding pads thereon is disposed on the tape within the chip opening such that the bonding pads face the tape. A plurality of through holes is formed in the tape to expose the bonding pads respectively. After that, an electrically conductive material is deposited to fill the through holes and form a plurality of conductive vias that connects with the bonding pads respectively. A multi-layered interconnection structure is formed on the surface of the tape away from the chip. The multi-layered interconnection structure has an inner circuit that connects to the conductive vias. The inner circuit has a plurality of metallic pads disposed on the outer surface of the multi-layered interconnection structure.Type: GrantFiled: November 18, 2004Date of Patent: January 30, 2007Assignee: Via Technologies, Inc.Inventor: Wen-Yuan Chang
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Publication number: 20070007636Abstract: A parallel chip embedded printed circuit board and manufacturing method thereof are disclosed. With a method of manufacturing a parallel chip embedded printed circuit board, comprising: (a) forming a parallel chip by connecting in parallel a plurality of unit chips having electrodes or electrically connected members formed on the upper and lower surfaces thereof, using at least one conductive member; (b) joining an electrode on one side of the parallel chip to a first board; and (c) joining an electrode on the other side of the parallel chip to a second board, chips may be embedded in a printed circuit board at a low cost, as a plurality of unit chips can be embedded at once, and a mechanical drill or router can be used instead of a laser drill in perforating the cavity or via holes.Type: ApplicationFiled: June 27, 2006Publication date: January 11, 2007Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jin-Yong Ahn, Chang Ryu, Suk-Hyeon Cho, Joon Kim, Han Cho
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Publication number: 20060255440Abstract: A composite multi-layer substrate comprising a flat plate-like core member formed of a material having an excellent electric conductivity, an excellent heat conductivity, and a high rigidity, a front resin layer and a rear resin layer covering at least the front and rear surfaces of the core member, and a bottomless hole formed in the core member through the front and rear sides of the core member, wherein an electronic component is installed in the bottomless hole, whereby since the strength of the composite multi-layer substrate can be assured by the rigidity of the core member, conventional prior art glass cloth can be eliminated, deterioration in the electric characteristics caused by ion migration can be avoided and will result in reduced production cost.Type: ApplicationFiled: May 27, 2003Publication date: November 16, 2006Applicant: TAIYO YUDEN CO., LTDInventors: Masashi Miyazaki, Mitsuhiro Takayama, Tatsuro Sawatari
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Publication number: 20060255478Abstract: The invention relates to an electronic component, which comprises a semiconductor chip. The semiconductor chip is embedded in a plastic housing in such a way that is rear side and its lateral sides are embedded in a plastic molding compound. The lateral sides and/or the rear side of the semiconductor chip have an anchoring region, by means of which the semiconductor chip is in positive engagement with the surrounding plastic molding compound. The invention also relates to a method for producing the component.Type: ApplicationFiled: March 9, 2004Publication date: November 16, 2006Inventors: Robert-Christian Hagen, Simon Jerebic, Robert Hagen
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Patent number: 7132746Abstract: A process and electronic assembly for conducting heat from a semiconductor circuit device mounted to a substrate. The substrate is supported by a housing member equipped with a heat-conductive member. A surface of the device opposite the substrate is bonded to the heat-conductive member with a solder joint formed of indium and optionally one or more alloying constituents that increase the melting temperature of the solder joint above that of indium. The housing member, substrate, and device are assembled so that an indium-containing solder material is present between the heat-conductive member and the surface of the device opposite the substrate. The solder material is then reflowed to form the solder joint. The alloying constituent(s) are preferably introduced into the solder joint during reflow.Type: GrantFiled: August 18, 2003Date of Patent: November 7, 2006Assignee: Delphi Technologies, Inc.Inventors: Scott D. Brandenburg, Bruce A. Myers
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Patent number: 7112875Abstract: A memory card comprising a substrate which has a plurality of contacts, at least one die pad, and a plurality of traces. The contacts, the die pad and the traces are disposed in spaced relation to each other and each define opposed first and second surfaces. Mounted to the first surface of the die pad is at least one electronic component which is electrically connected to at least one of the contacts either directly or via one or more of the traces. A first encapsulation part covers the second surfaces of the die pad and the traces, with the second surfaces of the contacts being exposed in the first encapsulation part. A second encapsulation part covers the electronic component and the first surfaces of the die pad, the contacts, and the traces. The first and second encapsulation parts collectively define a body of the memory card which includes a bottom surface having the second surfaces of the contacts exposed therein.Type: GrantFiled: February 17, 2005Date of Patent: September 26, 2006Assignee: Amkor Technology, Inc.Inventors: Jeffrey Alan Miks, Ludovico E. Bancod
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Patent number: 7095104Abstract: An approach to DRAM memory chip packaging leveraging the chip center position for wire bond pads to minimize time-of-flight and impedance effects resulting from stacking in a BGA application. A top layer of a dual device stack of center bus chips is stacked with an offset in a single direction with respect to a bottom layer of the dual device stack. The top layer of chips may be wire bonded to the opposite side of the module substrate. The center bus may be made to traverse to the substrate between two memory devices on the lower layer. To assemble the offset stacking devices into a high density module, devices are placed sequentially on a module substrate such that approximately one half of the protruding lower memory device is used as a support for the overhanging upper memory device chip of the next device stack.Type: GrantFiled: November 21, 2003Date of Patent: August 22, 2006Assignee: International Business Machines CorporationInventor: Edmund D Blackshear
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Publication number: 20060138619Abstract: A conductive plastic lead frame and method of manufacturing the same, suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.Type: ApplicationFiled: February 14, 2006Publication date: June 29, 2006Inventors: Tongbi Jiang, Jerrold King
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Publication number: 20060138625Abstract: A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semiconductor device 14 disposed on the second surface of the wiring substrate 11 and having a connection terminal 14a connected to the flat type external connection terminal 12a, a molding resin 15 for coating the semiconductor device 14 on the second surface of the wiring substrate 11, a card type supporting frame 10a having a concave portion or a hole portion fitting the wiring substrate 11, the semiconductor device 14, and the molding resin 15 in such a manner that the flat type external connection terminal 12a is exposed to the first surface of the wiring substrate 11, and adhesive resin a adhering integrally the flat type external connection terminal 12a, the wiring substrate 11, the semiconductor device 14, the molding resin 15, and the card type supporting frame 10a.Type: ApplicationFiled: February 3, 2006Publication date: June 29, 2006Applicant: Kabushiki Kaisha ToshibaInventor: Hiroshi Iwasaki