Abstract: A stacked die assembly for an IC includes a first interposer; a second interposer; a first integrated circuit die, a second integrated circuit die, and a plurality of components. The first integrated circuit die is interconnected to the first interposer and the second interposer, and the second integrated circuit die is interconnected to the second interposer. The plurality of components interconnect the first integrated circuit die to the first interposer and the second interposer. The plurality of components that interconnect the first integrated circuit die to the first interposer and the second interposer are located outside an interconnect restricted area of the first interposer and the second interposer, and signals are routed between the first integrated circuit die and the second integrated circuit die via the first integrated circuit die avoiding the interconnect restricted area of the first interposer and the second interposer.

Abstract: Semiconductor packages are provided. The semiconductor packages may include an upper package including a plurality of upper semiconductor devices connected to an upper package substrate. The semiconductor packages may also include a lower package including a lower semiconductor device connected to a lower package substrate. The upper and lower packages may be connected to each other.

Abstract: A semiconductor device includes a first semiconductor device and second semiconductor device stacked on the first semiconductor device. The first semiconductor device includes a first interconnect substrate, a first semiconductor element provided on an upper surface of the first interconnect substrate, a first electrode provided on the upper surface of the first interconnect substrate, and an insulating layer having an opening portion through which part of the first electrode is exposed. The second semiconductor device includes a second interconnect substrate, a second semiconductor element provided on an upper surface of the second interconnect substrate, a second electrode provided on a lower surface of the second interconnect substrate, and an inter-device connection terminal connected to the second electrode. Part of the first electrode exposed through the opening portion has a smaller area than an area of the opening portion.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; applying a molded under-fill on the base substrate; forming a substrate contact extender through the molded under-fill and in direct contact with the base substrate; mounting a stack device over the molded under-fill; attaching a coupling connector from the substrate contact extender to the stack device; and forming a base encapsulation on the stack device, the substrate contact extender, and encapsulating the coupling connector.

Abstract: A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit.

Abstract: An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.

Abstract: Systems and methods of the present disclosure provide for three-dimensional stacks of microelectromechanical (MEMS) systems, such as sensors. The stacks may be encapsulated and sealed, and can be positioned within biological tissue, for example to monitor biological signals within the volume of the sensor, provide stimulating signals to a brain, and so forth.

Abstract: An integrated circuit package-on-package stacking system includes: providing a first integrated circuit package, mounting a metalized interposer substrate over the first integrated circuit package, attaching a stiffener integrated with the metalized interposer substrate and having dimensions within package extents, and attaching a second integrated circuit package on the metalized interposer substrate adjacent the stiffener.

Abstract: A plurality of semiconductor chips may be stacked on the substrate, and each of them may include at least one electrode pad. At least one of the plurality of semiconductor chips may include at least one redistribution pad configured to electrically connect with the at least one electrode pad.

Abstract: A semiconductor device includes: a first semiconductor element having a first terminal surface on which a first terminal is disposed and a first rear surface on which no terminal is disposed; a second semiconductor element having a second terminal surface on which a second terminal is disposed and a second rear surface on which no terminal is disposed, the second rear surface being bonded to the first rear surface; a terminal member having a surface set substantially flush with the second terminal surface; and a conductive wire connecting the terminal member and the first terminal.

Abstract: The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment.

Abstract: In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.

Abstract: The present stacked semiconductor packages include a bottom package and a top package. The bottom package includes a substrate, a solder mask layer, a plurality of conductive pillars and a die electrically connected to the substrate. The solder mask layer has a plurality of openings exposing a plurality of pads on the substrate. The conductive pillars are disposed on at least a portion of the pads, and protrude from the solder mask layer.

Abstract: An exemplary embodiment of the present invention provides a chip for use in fabricating a three-dimensional integrated circuit, the chip comprising a wafer, one or more metallic-filled, electrical vias, and one or more hollow, fluidic vias. The wafer can comprise a first surface and a second surface. The one or more metallic-filled, electrical vias can extend through the wafer. Each electrical via can be in electrical communication with an electrical interconnect proximate the first surface, providing electrical communication between chips in the integrated circuit. The one or more hollow, fluidic vias can extend through the wafer. Each fluidic via can be in fluid communication with a fluidic interconnect, providing fluid communication between adjacent chips in the integrated circuit. Each fluidic interconnect can comprise a first end proximate the first surface, a second end, and a cap proximate the second end, defining an air-filled space within the fluidic interconnect.

Abstract: In accordance with the present invention, there is provided multiple embodiments of a package-in-package semiconductor device including an RF package and a semiconductor die which are provided in a stacked arrangement and are each electrically connected to an underlying substrate through the use of conductive wires alone or in combination with conductive bumps. In certain embodiments of the present invention, the RF package and the semiconductor die are separated from each other by an intervening spacer which is fabricated from aluminum, or from silicon coated with aluminum. If included in the semiconductor device, the spacer is also electrically connected to the substrate, preferably through the use of conductive wires. The RF package, the semiconductor die, the spacer (if included) and a portion of the substrate are at least partially covered or encapsulated by a package body of the semiconductor device.

Abstract: An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.

Abstract: The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

Abstract: A PoP (package-on-package) package includes a bottom package with a substrate encapsulated in an encapsulant with a die coupled to the top of the substrate. At least a portion of the die is exposed above the encapsulant on the bottom package substrate. A top package includes a substrate with encapsulant on both the frontside and the backside of the substrate. The backside of the top package substrate is coupled to the topside of the bottom package substrate with at least part of the die being located in a recess in the encapsulant on the backside of the top package substrate.

Abstract: A plurality of microelectronic assemblies are made by severing an in-process unit including an upper substrate and lower substrate with microelectronic elements disposed between the substrates. In a further embodiment, a lead frame is joined to a substrate so that the leads project from this substrate. Lead frame is joined to a further substrate with one or more microelectronic elements disposed between the substrates.

Abstract: Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.

Abstract: A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

Abstract: A stack package structure is provided, including: a substrate; an insulating layer formed on the substrate and having openings for exposing die attach pads and conductive pads of the substrate, respectively; a plurality of first and second conductive terminals formed on the insulating layer and electrically connected to the die attach pads and the conductive pads, respectively; a dielectric layer formed on the insulating layer and having a cavity for exposing the first conductive terminals and a plurality of openings exposing the second conductive terminals; copper pillars formed respectively in the openings of the dielectric layer; a semiconductor chip disposed in the cavity and electrically connected to the first conductive terminals; solder balls formed respectively on the copper pillars that are located proximate to the die attach area; and a package structure disposed on and electrically connected to the solder balls.

Abstract: A semiconductor package includes a substrate, a first semiconductor chip module attached to the substrate, a conductive connection member attached to the first semiconductor chip module, and a second semiconductor chip module attached to the conductive connection member. The first and second semiconductor chip modules are formed to have step like shapes to and extend laterally in opposite directions so as to define a zigzag arrangement together.

Abstract: A method for stacking and interconnecting integrated circuits includes providing at least two substrates; forming a trench in each substrate; filling the trench with an insulating material; forming, in each substrate, at least one conductive area; thinning each substrate until reaching at least the bottom of the trench, to obtain in each substrate at least one electrically insulated region within the closed perimeter delineated by the trench; bonding the substrates together; making at least one hole through the bonded substrates so that the hole passes at least partially through the conductive areas and passes through the insulated region of each substrate; and filling the hole with an electrically conductive material so as to obtain a conductive column that traverses the isolated region of each substrate and is in lateral electrical contact with the conductive areas.

Abstract: A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.

Abstract: A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.

Abstract: A semiconductor circuit substrate includes a transistor-forming substrate and a circuit-forming substrate. The transistor-forming substrate is a GaN substrate and has a Bipolar Junction Transistor (BJT) located in its top surface. The bottom surface of the transistor-forming substrate is flat and has contact regions. The circuit-forming substrate is a material other than a compound semiconductor and has no semiconductor active elements. The circuit-forming substrate has a flat top surface, contact regions buried in and exposed at the top surface, and passive circuits. The transistor-forming substrate and the circuit-forming substrate are directly bonded together without any intervening film, such as an insulating film.

Abstract: A packaging structure having an embedded semiconductor element includes: a substrate having opposite first and second surfaces and at least an opening penetrating the first and second surfaces; a first metallic frame disposed around the periphery of the opening on the first surface; a semiconductor chip received in the opening and having an active surface formed with a plurality of electrode pads and an opposite inactive surface; two first dielectric layers formed on the active surface and the inactive surface of the chip, respectively; a first wiring layer formed on the first dielectric layer of the first surface; and a first built-up structure disposed on the first dielectric layer and the first wiring layer. A shape of the opening is precisely controlled through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate.

Abstract: Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. A first die and a first through-casing interconnects are electrically coupled to the first interposer substrate. A first casing at least partially encapsulates the first device such that a portion of each first interconnect is accessible at a top portion of the first casing. A second known good packaged microelectronic device is coupled to the first device in a stacked configuration. The second device can include a second interposer substrate having a plurality of second interposer pads and a second die electrically coupled to the second interposer substrate. The exposed portions of the first interconnects are electrically coupled to corresponding second interposer pads.

Abstract: A package on package structure is provided. The package on package structure may include a first substrate having a first center region and a first C-shaped edge region at a first end of the first center region. In example embodiments, the first C-shaped edge region may faun a first space. The package structure may further include at least two first connection pads on an inner surface of the first C-shaped edge region and the at least two first connection pads may be arranged to face one another. In example embodiments, at least one first solder ball may be arranged in the first space and the at least one first solder ball may be connected to the at least two first connection pads.

Abstract: In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein, a first wiring electrode and a second wiring electrode extend to the inside of a interposed groove part from a first device region and a second device region respectively, and are separated from each other. In the laminated semiconductor substrate, a through hole which the first wiring electrode appears is formed. The laminated semiconductor substrate has a through electrode. The through electrode is contact with all of the first wiring electrodes appearing in the through hole. The laminated semiconductor substrate has a plurality of laminated chip regions.

Abstract: A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.

Abstract: A packaged integrated circuit (“IC”) has a daughter IC die stacked on a backside of a parent IC die. Backside fill material is applied to the backside of the parent IC die to provide a planarized surface.

Abstract: Disclosed herein is a semiconductor device including: an input terminal receiving, if a preceding-stage semiconductor device is layered on a predetermined one of an upper layer and a lower layer, a bit train outputted from the preceding-stage semiconductor device; a semiconductor device identifier hold block holding a semiconductor device identifier for uniquely identifying the semiconductor device; a semiconductor device identifier computation block executing computation by using the semiconductor device identifier to update the semiconductor device identifier held in the semiconductor device identifier hold block according to a result of the computation; a control block once holding data of a bit train entered from the input terminal to control updating of the semiconductor device identifier executed by the semiconductor device identifier computation block based on the held data; and an output terminal outputting the bit train held in the control block to a succeeding-stage semiconductor device layered on a

Abstract: A method of forming a bonded shingle stacked die package is provided. The method includes providing a wafer, singulating the wafer into a plurality of strips, applying to at least a portion of at least one mating surface of each of the plurality of strips a material capable of reacting with the other mating surface, stacking the plurality of strips in an overlapping stair-step configuration, exposing the stacked strips to conditions sufficient to bond the plurality of strips together, and dicing the stacked strips into individual die shingle stack configurations.

Abstract: A semiconductor package includes a substrate, a first semiconductor chip module attached to the substrate, a conductive connection member attached to the first semiconductor chip module, and a second semiconductor chip module attached to the conductive connection member. The first and second semiconductor chip modules are formed to have step like shapes to and extend laterally in opposite directions so as to define a zigzag arrangement together.

Abstract: The microelectronic assembly includes a first microelectronic element having a front surface, a plurality of contacts exposed at the front surface, and a rear surface remote from the front surface; a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond an edge of the first microelectronic element, the second microelectronic element having a plurality of contacts exposed at its front surface; a dielectric region overlying the front surfaces of the microelectronic elements, the dielectric region having a major surface facing away from the microelectronic elements; metallized vias within openings in the dielectric region extending from the plurality of contacts of the first and second microelectronic elements; and leads extending along a major surface of the dielectric region from the vias to terminals exposed at the major surface.

Abstract: The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack.

Abstract: A chip stacked structure and method of fabricating the same are provided. The chip stacked structure includes a first chip and a second chip stacked on the first chip. The first chip has a plurality of metal pads disposed on an upper surface thereof and grooves disposed on a side surface thereof. The metal pads are correspondingly connected to upper openings of the grooves. The second chip has a plurality of grooves on a side surface of the second chip, locations of which are corresponding to that of the grooves on the side surface of the first chip. Conductive films are formed on the grooves of the first chip and the second chip and the metal pads to electronically connect the first chip and second chip. The chip stacked structure may simplify the process and improve the process yield rate.

Abstract: A multi-die building block for a stacked-die package is described. The multi-die building block includes a flex tape having a first surface and a second surface, each surface including a plurality of electrical traces. A first die is coupled, through a first plurality of interconnects, to the plurality of electrical traces of the first surface of the flex tape. A second die is coupled, through a second plurality of interconnects, to the plurality of electrical traces of the second surface of the flex tape.

Abstract: A battery protection package assembly is disclosed. The assembly includes a power control integrated circuit (IC) with pins for a supply voltage input (VCC) and a ground (VSS) on a first side of the power control IC. First and second common-drain metal oxide semiconductor field effect transistors (MOSFETs) are electrically coupled to the power control IC. The power control IC and the first and second common-drain metal oxide semiconductor field effect transistors (MOSFET) are co-packaged on a common die pad. The power control IC is vertically stacked on top of one or more of the first and second common-drain MOSFETs. Leads coupled to a supply voltage input (VCC) and a ground (VSS) of the power control IC are on a first side of the common die pad.

Abstract: A semiconductor package may include a package substrate having a first surface and a boundary that may be defined by edges of the package substrate. The package further includes a first semiconductor chip having a front surface and a back surface. The back surface of a first portion of the first semiconductor chip may be disposed on the first surface of the package substrate with the back surface of a second portion of the first semiconductor chip extending beyond of the defined boundary of the package substrate. The semiconductor package may also include a second semiconductor chip disposed on the back surface of the second portion of the first semiconductor chip that extends beyond the defined boundary of the package substrate.

Abstract: Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.

Abstract: Stacked die having vertically-aligned conductors and methods for making the same are disclosed for providing a non-volatile memory, such as flash memory (e.g., NAND flash memory), for use in an electronic device.

Abstract: A semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface, a heat dissipation member, defined with a cavity, disposed on the first surface of the first semiconductor chip and having a plurality of metal pillars which contact the first semiconductor chip, and one or more second semiconductor chips stacked on the first surface of the first semiconductor chip in the cavity to be electrically connected with one another and with the first semiconductor chip.

Abstract: An integrated circuit package system includes: connecting a first interconnect between a carrier and a bottom integrated circuit thereover; forming a film, having an overhang portion, over the bottom integrated circuit with the overhang portion over the first interconnect; mounting a top integrated circuit over the film; connecting a second interconnect between the top integrated circuit and the carrier with the overhang portion between the first interconnect and the second interconnect; and forming an encapsulation over the carrier covering the top integrated circuit, the film, the first interconnect, and the second interconnect.

Abstract: An electronic device is disclosed which can suppress the formation of voids in a region below an overhanging portion of a first semiconductor device overhanging a support member. The support member is disposed over a package substrate. The first semiconductor device is disposed over the support member and, when seen in plan, at least a part of the first semiconductor device overhangs the support member. A first resin layer fills up a space below the first semiconductor device in at least a part of the overhanging portion of the first semiconductor device around the support member. The first resin layer is in contact with the support member. A second resin layer seals the first semiconductor device and the support member.

Abstract: A power semiconductor device having a first active semiconductor component and a second active semiconductor component, the electrical connections of which are routed out of the semiconductor components in the form of connecting legs is disclosed. In one embodiment, the first semiconductor component is at least partially electrically connected to the second semiconductor component by means of a plug-in connection. The plug-in connection is realized by virtue of the connecting legs of the second semiconductor component engaging in the electrical connections of the first semiconductor component.

Abstract: Provided are semiconductor packages and electronic systems including the same. A substrate is provided. A plurality of semiconductor chips may be stacked the substrate, and each of them may include at least one electrode pad. At least one of the plurality of semiconductor chips may include at least one redistribution pad configured to electrically connect with the at least one electrode pad.

Abstract: Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.