Foil-like Cooling Fins Or Heat Sinks (epo) Patents (Class 257/E23.103)
  • Patent number: 11695311
    Abstract: An interference suppression module for an electrically commutated electric motor has the following components: a circuit carrier, an electronic circuit arrangement, which is arranged on the circuit carrier, an encapsulation, which surrounds the electronic circuit arrangement in a form-fitting and material-bonding manner, and at least one interface, which is provided for the purpose of electrical contact-connection of the electronic circuit arrangement to a control unit of the electrically commutated electric motor. The specification details an interference suppression module, a method for producing an interference suppression module, and a vehicle equipped with an interference suppression module.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: July 4, 2023
    Assignee: Vitesco Tehcnologies Germany GmbH
    Inventors: Andreas Albert, Juergen Henniger, Matthias Keuten
  • Patent number: 11678465
    Abstract: In some embodiments, an apparatus comprises an integrated circuit module comprising two layers of thermal interface material, a printed circuit assembly disposed between the two layers of thermal interface material and comprising a plurality of integrated circuits disposed on both sides of a circuit board, wherein at least one of the integrated circuits is thermally coupled with one of the layers of thermal interface material, and two heat spreaders adapted to removably retain one another, and when retaining one another to enclose and become thermally coupled with the two layers of thermal interface material; and a printed circuit board having a connector disposed thereon, wherein a connector edge of the printed circuit assembly is disposed within the connector. In other embodiments, a frame is adapted to retain the two heat spreaders.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: June 13, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Kevin Conn, Pinche Tsai, Keith Sauer
  • Patent number: 11432430
    Abstract: The heat dissipation device comprises a fluid direction changing part that changes a fluid traveling direction in which a fluid travels. The fluid direction changing part has a base end and a tip. The base end is fixed to a second surface facing a first surface inside a tubular body. The tip is arranged to face multiple fin ends of multiple fins of a heat sink. The fluid direction changing part is entirely or partially arranged downstream of the fluid traveling direction from an upstream end surface of the heat sink. The fluid flows into the heat sink through the upstream end surface, and also passes through a flow path without fin other than a flow path between fins for passage of a fluid formed between the multiple fins to flow into the heat sink through parts of the multiple fin ends exposed at upstream positions from the tip of the fluid direction changing part.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: August 30, 2022
    Assignee: FANUC CORPORATION
    Inventors: Ryuutarou Mitsuzawa, Kazuhiro Yamamoto, Kenichi Okuaki
  • Patent number: 10644608
    Abstract: An electric power conversion device is provided with a case (60) including a mounting portion (61) extending along a plane defined by a first direction and a second direction that are orthogonal to each other, and a side wall (62) provided along a periphery of the mounting portion, a primary side connection portion (23) and a secondary side connection portion (27) provided on the case, a plurality of reactors arranged along the second direction in the case and connected in parallel to one another, and a switching unit including a plurality of switching devices positioned in the case on one side of the reactors in the first direction, arranged along the first direction, and respectively connected to the reactors.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: May 5, 2020
    Assignee: Honda Motor Co., Ltd.
    Inventors: Yusuke Shindo, Jun Kato, Ryota Kitamoto, Shinnosuke Sato, Toshiki Ikeda, Takanori Sakaguchi, Kosuke Nishiyama, Takaaki Fushimi
  • Patent number: 9820395
    Abstract: A hermetically sealed electronic device and method of fabrication are provided. A base layer of a wafer is created using a substrate formed from ultra-thin glass or ceramic using panel or roll to roll processing. One or more layers are bonded to the base layer. The wafer is singulated into a plurality of electronic devices having a top surface and a plurality of sides. A hermetic sealant is applied to each electronic device to completely encase the top surface and the sides while bonding to the base layer. At least one of the layers is a metallization layer formed by metal deposition. Full metallization may be applied over the entire wafer and a pattern subsequently transferred to the full metallization by one of laser and chemical etching. The electronic device may further include at least one electronic component attached to one of the layers and encased by the hermetic sealant.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, John U. Knickerbocker, Minhua Lu, Jae-Woong Nah, Robert John Polastre
  • Patent number: 9418909
    Abstract: A method and apparatus are provided which improve the adhesion of a lid to an IC die of an IC (chip) package. In one embodiment, a chip package assembly is provided that includes an IC die, a package substrate and a lid. The IC die is coupled to the package substrate. The lid has a first surface and a second surface. The second surface of the lid faces away from the first surface and towards the IC die. The second surface of the lid has a plurality of engineered features. The adhesive couples the plurality of engineered features of the lid to the IC die.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: August 16, 2016
    Assignee: XILINX, INC.
    Inventors: Raghunandan Chaware, Inderjit Singh
  • Patent number: 8963324
    Abstract: In a semiconductor device, a semiconductor module is pressed against a cooler by a spring member. The spring member is compressed by a beam member that is connected with a strut fixed to the cooler. The cooler has a pressed part in which the semiconductor module is pressed, and a strut fixing part to which the strut is fixed. The strut fixing part has higher rigidity than the pressed part.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: February 24, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Takato Sato, Yukio Onishi, Hiroyuki Kono, Hiroaki Yoshizawa, Toshio Watari, Hiromi Yamasaki
  • Patent number: 8907472
    Abstract: A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wensen Hung
  • Patent number: 8847381
    Abstract: A semiconductor element housing package includes a substrate, a frame body disposed on the substrate; an insulating substrate disposed in a frame-body-surrounded region of the substrate; a first mounting member disposed on the insulating substrate, for mounting a power semiconductor element thereon; a second mounting member disposed on the insulating substrate so as to be spaced away from the first mounting member; a first lead member having a first bend; and a second lead member having a second bend. The first lead member is disposed so as to pass through the frame body from an exterior thereof and extend over the first mounting member and makes connection therewith through the first bend. The second lead member is disposed so as to pass through the frame body from the exterior thereof and extend over the second mounting member and makes connection therewith through the second bend.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: September 30, 2014
    Assignee: Kyocera Corporation
    Inventors: Yoshiaki Ueda, Shinji Nakamoto, Hiroshi Mizushima, Nobuyuki Tanaka
  • Patent number: 8790964
    Abstract: A device comprising a substrate, an integrated circuit (IC) die attached to the substrate on one side, a plurality of contact pads on an active side of the IC die, a plurality of thermally and electrically conductive legs, each of the legs attached to a respective one of the contact pads, and an encapsulating material formed around the substrate, the IC die, and a portion of the legs. A contact end of each of the legs is exposed, and one of the contact ends conducts a signal from a transistor in the IC die.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: July 29, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Min Ding
  • Patent number: 8749052
    Abstract: An electric device with an insulating substrate consisting of an insulating layer and at least one metallization on a surface side of the insulating layer, the metallization being structured and having an electric component on the metallization. The metallization has a layer thickness that is stepped and is greater in an area adjoining the component.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: June 10, 2014
    Assignee: Curamik Electronics GmbH
    Inventors: Jürgen Schulz-Harder, Andreas Meyer
  • Patent number: 8648462
    Abstract: A semiconductor power module includes an active element and a passive element serving as semiconductor elements each having a first electrode on a front surface and a second electrode on a back surface thereof, a heat pipe having a first region defined as arrangement parts of the active element and the passive element on its one end side and electrically connected to one of the first and second electrodes of the active element and the passive element arranged in the first region, a cooling fin arranged in a second region defined on the other end side of the heat pipe, and a heat pipe provided to sandwich the active element, the passive element, and the cooling fin arranged on the heat pipe along with the heat pipe and electrically connected to the other of the first and second electrodes of the active element and passive element.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: February 11, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Koichi Ushijima
  • Patent number: 8618585
    Abstract: A semiconductor apparatus according to embodiments of the invention can include a first semiconductor device made of silicon, the first semiconductor devices being arranged collectively, whereby to form a first device group, and a second semiconductor device made of silicon carbide, the second semiconductor devices being arranged collectively, whereby to form a second device group. The apparatus can also include a wiring conductor connecting the first semiconductor device and the second semiconductor device, a cooling fin base comprising a projection formed thereon, whereby to dissipate heat generated from the first and second semiconductor devices, and the projections arranged under the second device group being spaced apart from each other more widely than the projections arranged under the first device group.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: December 31, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Kenichiro Sato
  • Patent number: 8536687
    Abstract: A technology with which the reliability of a package making up a semiconductor device can be enhanced is provided. A feature of the technical idea of the invention is that: a heat sink unit and an outer lead unit are separated from each other: and the outer lead unit is provided with chip placement portions and each of the chip placement portions and each heat sink are joined together. As a result, when a sealing body is formed at a resin sealing step, tying portions function as a stopper for preventing resin leakage and the formation of resin burr in a package product can be thereby prevented. In addition, camber does not occur in the heat sink unit and cracking in a sealing body caused by winding (camber) can be suppressed.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Toshiyuki Hata
  • Patent number: 8405204
    Abstract: A semiconductor package includes a main body having a semiconductor device accommodating portion accommodating a basic circuit including a semiconductor device, external connection terminal members protruding outside the main body, and a cooling structure reducing heat generated by the device from the main body. The cooling structure includes a coolant flowing portion including a coolant supply port to which coolant is supplied, a coolant moving space which is positioned adjacent to the accommodating portion and in which the coolant moves in a back side of the basic circuit of the accommodating portion, and a coolant discharge port which discharges the coolant from the moving space. The semiconductor package assembly includes a package support body which supports the package and which includes a coolant circulation structure supplying coolant to the flowing portion of the main body through the supply port and collecting the supplied coolant through the discharge port.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: March 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuyoshi Hasegawa
  • Publication number: 20130056885
    Abstract: An encapsulated semiconductor device includes: a first conduction path formative plate (1); a second conduction path formative plate (5) joined to the first conduction path formative plate; a power element (12) bonded to the first conduction path formative plate; a heatsink (14) held by the first conduction path formative plate with an insulation sheet (13) interposed between the heatsink and the first conduction path formative plate; and an encapsulation resin (9) configured to encapsulate the first and second conduction path formative plates. A through hole (3) or a lead gap (1b) is formed in a region of the first conduction path formative plate in contact with the insulation sheet. The insulation sheet is press-fitted into the through hole or the lead gap.
    Type: Application
    Filed: March 26, 2012
    Publication date: March 7, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Masanori Minamio, Tatsuo Sasaoka
  • Patent number: 8391011
    Abstract: A cooling device includes a heat sink having a top plate, a bottom plate spaced from the top plate and fins between the top and bottom plates, a first metal member laminated to the side of the top plate that is opposite from the fins, and a first insulator laminated to the first metal member. The top plate, the bottom plate and the first metal member are each made of a clad metal that is composed of a base metal and a brazing metal, so that the fins are brazed to the top and bottom plates, the first metal member is brazed to the top plate, and the first insulator is brazed to the first metal member.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: March 5, 2013
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Shogo Mori, Eiji Kono
  • Patent number: 8368205
    Abstract: A method for the assembly of a semiconductor package that includes cleaning a surface of a chip and a surface of a heat removal device by reverse sputtering is given. The method includes sequentially coating the surface of the chip and the surface of the heat removal device with an adhesive layer, a barrier layer, and a protective layer over a target joining area. The chip and the heat removal device are placed into carrier fixtures and preheated to a target temperature. Then a metallic thermal interface material (TIM) preform is mechanically rolled onto the surface of the chip and the first and the second carrier fixtures are attached together such that the metallic TIM layer on the surface of the chip is joined to the coated surface of the heat removal device through a fluxless process. The method includes heating the joined carrier fixtures in a reflow oven.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: February 5, 2013
    Assignee: Oracle America, Inc.
    Inventors: Seshasayee Ankireddi, Vadim Gektin, James A. Jones, Margaret B. Stern
  • Patent number: 8294272
    Abstract: A power module includes a pair of power devices that are stacked with a plate-shaped output electrode arranged therebetween, and an N-electrode and a P-electrode that are stacked with the pair of power devices arranged therebetween. The output electrode is anisotropic such that the thermal conductivity in a direction orthogonal to the stacking direction is greater than the thermal conductivity in the stacking direction. Also, the output electrode extends in the orthogonal direction from a stacked area where the pair of power devices are stacked. The N-electrode and the P-electrode extend in the orthogonal direction while maintaining an opposing positional relationship.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: October 23, 2012
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Yasushi Yamada, Hiroshi Osada, Gentaro Yamanaka, Norifumi Furuta, Akio Kitami, Tadafumi Yoshida, Hiromichi Kuno
  • Patent number: 8283775
    Abstract: A semiconductor device including a semiconductor element 1 having an active element region 1a, a plurality of element electrodes 2 formed on a principal face of the semiconductor element, external terminals 6 and 7 connected to one or more element electrodes via connection members 8 and 9, one or more first heat-dissipation protrusions 4 formed on the principal face of the semiconductor element, an insulation resin layer 10 covering the principal face of the semiconductor element and the first heat-dissipation protrusions, and a heat-dissipation medium 11 contacting a face of the insulation resin layer on a side opposite to a side contacting front faces of the first heat-dissipation protrusions.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: October 9, 2012
    Assignee: Panasonic Corporation
    Inventors: Nozomi Shimoishizaka, Yoshifumi Nakamura, Kouichi Nagao
  • Patent number: 8283776
    Abstract: An electrical package with improved thermal management. The electrical package includes a die having an exposed back surface. The package further includes a plurality of fins extending outwardly from the back surface for dissipating heat from the package. The die can be arranged in a multi-die stacking configuration. In another embodiment, a method of forming a die for improved thermal management of an electrical package is provided.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: October 9, 2012
    Assignee: QUALCOMM Incorporated
    Inventor: Arvind Chandrasekaran
  • Patent number: 8269248
    Abstract: Apparatus may be provided including a high power light emitting diode (LED) unit, at least one printed circuit board, and an interfacing portion of a heat sink structure. The high power LED unit includes at least one LED die, at least one first lead and at least one second lead, and a heat sink interface. The at least one printed circuit board includes a conductive pattern configured to connect both the at least one first lead and the at least one second lead to a current source. The interfacing portion of the heat sink structure is that portion through which a majority of heat of the heat sink interface is transmitted. The interfacing portion is directly in touching contact with a majority of a heat transfer area of the heat sink interface.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: September 18, 2012
    Inventor: Joseph B. Thompson
  • Publication number: 20120126390
    Abstract: A semiconductor device is provided that may include an insulating substrate having a ceramic substrate and metal coating layers on opposite surfaces of the ceramic substrate, a semiconductor chip mounted on one surface of the insulating substrate, and a heat sink directly or indirectly fixed to the other surface of the insulating substrate and thermally connected to the semiconductor chip through the insulating substrate. The heat sink may include a housing that is made of a metal sheet and radiating fins that are fixed in the housing and made of aluminum. The metal sheet may have a coefficient of thermal expansion between those of the insulating substrate and the radiating fin.
    Type: Application
    Filed: January 30, 2012
    Publication date: May 24, 2012
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Shogo MORI, Eiji KONO, Keiji TOH
  • Publication number: 20120126387
    Abstract: An electronic device includes an integrated circuit (IC) die attached to a substrate, and electrical conductors connecting the IC die to the substrate. The electronic device also includes a heat spreader located over the IC die and having a concaved portion located over the IC die along with a lateral portion extending from the concaved portion. The lateral portion has a surface area greater than a surface area of the concaved portion. A support member is further included that extends from the lateral portion to and contacts the substrate. An encapsulant covers the support member leaving the lateral and concaved portions exposed on outer sides thereof. In another aspect, a method of manufacturing an electronic device is also included.
    Type: Application
    Filed: November 24, 2010
    Publication date: May 24, 2012
    Applicant: LSI Corporation
    Inventors: Clifford R. Fishley, Abiola Awujoola
  • Patent number: 8115303
    Abstract: Semiconductor package structures are provided which are designed to have liquid coolers integrally packaged with first level chip modules. In particular, apparatus for integrally packaging a liquid cooler device within a first level chip package structure include structures in which a liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate. The liquid cooler device is mechanically coupled to the package substrate through a metallic stiffener structure that is bonded to the flexible package substrate to provide mechanical rigidity to the flexible package substrate.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: February 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Raschid Jose Bezama, Evan George Colgan, Michael Gaynes, John Harold Magerlein, Kenneth C. Marston, Xiaojin Wei
  • Patent number: 8102046
    Abstract: Through heat discharge only by wiring connected to a conventional semiconductor chip, sufficient heat discharge performance may not be achieved in a recent semiconductor device. A semiconductor device according to an aspect of the present invention includes: a flexible substrate including a first main surface and a second main surface; a semiconductor chip; a first heat conductive layer formed on the first main surface of the flexible substrate and electrically connected to the semiconductor chip; and a second heat conductive layer formed on the second main surface of the flexible substrate and electrically insulated from the semiconductor chip.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: January 24, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuaki Iwata, Chihiro Sasaki
  • Patent number: 8089085
    Abstract: An LED assembly can include a heat sink base, at least one LED die attached to the heat sink base, and a lens. One or more layers of phosphor can be formed upon the lens. A heat sink, such as a finned heat sink, can attach the heat sink base to the lens. Heat from the LED die can flow through the heat sink base to the heat sink, from which the heat can be dissipated. Similarly, heat from phosphors can flow through the lens to the heat sink, from which the heat can be dissipated. By removing heat from the LED die, more current can be used to drive the LED die, thus providing brighter light. By removing heat from the phosphors, desired colors can be more reliably provided.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: January 3, 2012
    Assignee: Bridgelux, Inc.
    Inventor: Wei Shi
  • Patent number: 8030758
    Abstract: A semiconductor module (10) includes a heat sink (1), an electronic component (2), a semiconductor device (3), and a thermally-conductive sheet member (4). The thermally-conductive sheet member (4) covers a part of the semiconductor device (3) and has a lower part (4b) and a side part (4c). The lower part (4b) is in contact with a mounting face (11a) of the heat sink (1). The side part (4c) extends from the lower part (4b) and covers a first side surface (3c) of the semiconductor device (3). The electronic component (2) is disposed across the side part (4c) of the thermally-conductive sheet member (4) from the semiconductor device (3).
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: October 4, 2011
    Assignee: Panasonic Corporation
    Inventor: Makoto Kitabatake
  • Patent number: 8030755
    Abstract: An integrated circuit package system is provided forming a substrate having an integrated circuit die thereon, thermally connecting a heat slug and a resilient thermal structure to the integrated circuit die, and encapsulating the resilient thermal structure.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: October 4, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Sangkwon Lee, Tae Keun Lee
  • Publication number: 20110180925
    Abstract: An electrical package with improved thermal management. The electrical package includes a die having an exposed back surface. The package further includes a plurality of fins extending outwardly from the back surface for dissipating heat from the package. The die can be arranged in a multi-die stacking configuration. In another embodiment, a method of forming a die for improved thermal management of an electrical package is provided.
    Type: Application
    Filed: January 26, 2010
    Publication date: July 28, 2011
    Applicant: QUALCOMM INCORPORATED
    Inventor: Arvind Chandrasekaran
  • Patent number: 7964958
    Abstract: A heatsink structure for solid-state image sensors includes a foil-like heatsink sheet made of a high heat conductivity material. The heatsink sheet has a first fixed portion fixed to a solid-state image sensor and a second fixed portion fixed to another member. The heatsink sheet also has a plurality of cutout portions formed along directions from the first fixed portion toward the second fixed portion. Thus, the heatsink structure can cool the solid-state image sensor while reducing any external-force loads applied to the solid-state image sensor with a relatively simple structure.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: June 21, 2011
    Assignee: Panasonic Corporation
    Inventors: Yukihiro Iwata, Shinya Ogasawara, Miyoko Irikiin
  • Patent number: 7923826
    Abstract: A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: April 12, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Noriyuki Takahashi, Mamoru Shishido
  • Patent number: 7919854
    Abstract: A semiconductor module with two cooling surfaces and method. One embodiment includes a first carrier with a first cooling surface and a second carrier with a second cooling surface. The first cooling surface is arranged in a first plane, the second cooling surface is arranged in a second plane, at an angle different from 0° relative to the first plane.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: April 5, 2011
    Assignee: Infineon Technologies AG
    Inventor: Thilo Stolze
  • Patent number: 7911051
    Abstract: An electronic circuit arrangement includes a heat sink and a first circuit carrier which is thermally coupled to the heat sink, lies flat on the latter and is intended to wire electronic components of the circuit arrangement. Provided for at least one electronic component is a special arrangement which is associated with a considerably increased heat dissipation capability for the relevant component and, in addition, also affords further advantages in connection with changes in the population and/or line routing which might occur in practice. The important factor for this is that the component is arranged under a second circuit carrier which is held in a recess in the first circuit carrier. The recess passes through to the top side of the heat sink.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: March 22, 2011
    Assignee: Continental Automotive GmbH
    Inventors: Robert Ingenbleek, Erik Jung, Alfred Kolb, Andreas Rekofsky, Roland Schöllhorn, Daniela Wolf
  • Patent number: 7903417
    Abstract: An electrical circuit assembly includes an electrical circuit substrate having a first side; a heat sink including a metal base plate having a first side and a second side, and a plurality of fins extending from the second side; and a thermally conductive and electrically insulating adhesive directly interconnecting at least a portion of the first side of the electrical circuit substrate with the first side of the base plate.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: March 8, 2011
    Assignee: Deere & Company
    Inventors: Ronnie Dean Stahlhut, Clement Vanden Godbold, Jeffrey Gerald Hopman, Kartheek Karna, James Arthur Springer, John Lopes Alves, Lise Alves, legal representative
  • Patent number: 7875911
    Abstract: A semiconductor device includes a semiconductor substrate including an active element or an integrated circuit and a plurality of connection electrodes to be electrically connected to the integrated circuit; a first resin layer formed on a surface of the semiconductor substrate on which the connection electrodes are formed in such a manner avoiding the connection electrodes; a connection wiring layer formed between the semiconductor substrate and the first resin layer and connected to one of the plurality of connection electrodes; a Cu wiring layer connected at one end thereof to the connection wiring layer and formed on the surface of the first resin layer; a passive element composed of the connection wiring layer and the Cu wiring layer; a second resin layer for covering a surface of the Cu wiring layer; and an external terminal electrically connected to some of the plurality of connection electrodes and formed such that a portion of the second resin layer protrudes from the second resin layer.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: January 25, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Shigekazu Takagi
  • Publication number: 20110012254
    Abstract: An air cavity package is manufactured by attaching a die to a surface of a copper heat sink, dispensing a bead of epoxy around a periphery of the heat sink surface after the die is attached to the copper heat sink so that the bead of epoxy generally surrounds the die and placing a ceramic window frame on the bead of epoxy. The epoxy is cured to attach a bottom surface of the ceramic window frame to the copper heat sink.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 20, 2011
    Applicant: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
    Inventors: Anwar A. Mohammed, Julius Chew, Alexander Komposch, Christian Andrada
  • Patent number: 7868450
    Abstract: A semiconductor package includes a base plate having first and second surfaces both facing in opposite directions, and a plurality of anisotropic heat conducting members disposed in the base plate and spaced away from each other. A semiconductor element having a heat generating unit is mounted on the first surface, and the second surface is supported on a supporting member having a thermal conductivity. Each anisotropic heat conducting member has a sheet shape intersecting with the first and second surfaces, and orientates a direction of higher thermal conductivity than the thermal conductivity of the base plate in a direction from the first surface toward the second surface.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: January 11, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Ito, Tsuyoshi Hasegawa
  • Patent number: 7864534
    Abstract: An electronics enclosure is provided. The electronics enclosure includes a heat dissipating body comprising: a heat conducting surface, a first flange adjacent to the heat conducting surface, and a first part of a latch mechanism adjacent to the heat conducting surface. The first part of the latch mechanism is adjacent an edge of the heat conducting surface opposite to the first flange, such that a portion of the heat conducting surface is between the first flange and the first part of the latch mechanism. The electronics enclosure also includes a plurality of electronic modules configured to mount to the heat dissipating body.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: January 4, 2011
    Assignee: ADC Telecommunications, Inc.
    Inventors: Michael J. Wayman, Michael J. Nelson
  • Publication number: 20100314743
    Abstract: In one aspect, an embodiment of an IC package includes an IC chip electrically connected to a substrate, a heatspreader disposed over the IC chip, wherein the heatspreader does not directly contact the IC chip, and an encapsulant material encapsulating at least a portion of the IC chip and a portion of the heatspreader such that a top portion of the heatspreader is exposed to the surroundings of the IC package. In another embodiment, the heatspreader comprises at least one castellation to improve adhesion to the encapsulation compound. A method of manufacturing such IC package is also disclosed.
    Type: Application
    Filed: July 29, 2009
    Publication date: December 16, 2010
    Applicant: GREEN ARROW ASIA LIMITED
    Inventor: Tung Lok LI
  • Publication number: 20100289135
    Abstract: A semiconductor chip package is disclosed. One embodiment provides at least one semiconductor chip including contact elements on a first surface of the chip. An encapsulation layer covers the semiconductor chip. A metallization layer is applied above the first surface of the chip and the encapsulation layer. The metallization layer includes contact areas connected with the contact elements of the chip. External pins are connected with the contact areas.
    Type: Application
    Filed: May 15, 2009
    Publication date: November 18, 2010
    Applicant: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer
  • Patent number: 7834433
    Abstract: In one embodiment the present invention includes a semiconductor power device. The semiconductor power device includes a single gauge lead frame, a semiconductor die, and a heat sink. The semiconductor die is attached to a first level of the lead frame. The heat sink is attached to a second level of the lead frame. A molding compound encapsulates the semiconductor die and a portion of the lead frame, such that a portion of the heat sink is outside of the molding compound. The resulting device may be efficiently manufactured as compared to dual gauge lead frame devices or devices where the semiconductor die is not attached to the lead frame.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: November 16, 2010
    Assignee: Shanghai Kaihong Technology Co., Ltd.
    Inventors: Tan Xiaochun, Li Yunfang
  • Publication number: 20100258844
    Abstract: A semiconductor device comprising a silicon substrate, a compound semiconductor material, an insulating material between the silicon substrate and the compound semiconductor material, and a top surface comprising means of electrical connection, and passivation material, where the passivation material is silicon nitride, silicon dioxide, or a combination of both. The present invention eliminates the need for a thick electrical insulator between a heat sink and the back surface of a surface mounted device by the inclusion of an AlN seed layer to electrically isolate the silicon substrate of the device. The sidewalls of the device are also electrically isolated from the active area of the device.
    Type: Application
    Filed: April 8, 2010
    Publication date: October 14, 2010
    Inventors: Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao
  • Patent number: 7786565
    Abstract: A semiconductor apparatus includes a semiconductor chip 61 including a power semiconductor device using a wide band gap semiconductor, base materials 62 and 63, first and second intermediate members 65 and 68a, a heat conducting member 66, a radiation fin 67, and an encapsulating material 68 for encapsulating the semiconductor chip 61, the first and second intermediate member 65 and 68a and the heat conducting member 66. The tips of the base materials 62 and 63 work respectively as external connection terminals 62a and 63a. The second intermediate member 68a is made of a material with lower heat conductivity than the first intermediate member 65, and a contact area with the semiconductor chip 61 is larger in the second intermediate member 68a than in the first intermediate member.
    Type: Grant
    Filed: September 6, 2004
    Date of Patent: August 31, 2010
    Assignee: Panasonic Corporation
    Inventors: Makoto Kitabatake, Osamu Kusumoto, Masao Uchida, Kunimasa Takahashi, Kenya Yamashita
  • Publication number: 20100187680
    Abstract: A radiator includes: an insulating substrate, a heating element or a semiconductor chip is mounted; and a heat sink that is provided the insulating substrate through a stress relaxation member that has a stress absorbing space, in which the heat sink dissipates heat from the semiconductor chip. The insulating substrate, the stress relaxation member, and the heat sink are braze-bonded to each other. The heat sink has: a top plate that is bonded to the stress relaxation member; and a bottom plate that is bonded to the top plate, and the top plate and the bottom plate forms a passage of coolant therebetween. A thickness proportion between the top plate and the bottom plate falls within a range of 1:3 to 1:5.
    Type: Application
    Filed: December 18, 2009
    Publication date: July 29, 2010
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Kenji Otsuka, Masaru Nakashima
  • Patent number: 7746653
    Abstract: An assembly for clamping electrical components against a heat-dissipating surface of a heat sink may include the heat sink, one or more electrical components, two or more springs, and a fastener. Each of the springs may include a first surface, and a second surface opposite the first surface. The second surface of each of the springs may include an attachment region and two contact regions. The attachment region may be between the two contact regions. The second surface of one of the springs may overlap the first surface of another one of the springs. Each of the springs may be positioned to hold the electrical components against the heat dissipating surface of the heat sink. Each of the two contact regions of each of the springs may be positioned to hold the electronic components against the heat-dissipating surface. The fastener may couple the springs together in the attachment region of each of the springs and may further couple the springs to the heat sink.
    Type: Grant
    Filed: January 2, 2008
    Date of Patent: June 29, 2010
    Assignee: Harman International Industries Incorporated
    Inventor: Florin Negrut
  • Publication number: 20100084761
    Abstract: A semiconductor device includes a mounting substrate, a plurality of semiconductor chips mounted on the mounting substrate, and a heat-dissipation area formed above the plurality of semiconductor chips. A distance between one of the plurality of semiconductor chips which generates a greatest amount of heat and the heat-dissipation area is smaller than a distance between the other semiconductor chips and the heat-dissipation area.
    Type: Application
    Filed: August 10, 2009
    Publication date: April 8, 2010
    Inventor: Masatoshi Shinagawa
  • Patent number: 7692291
    Abstract: A circuit board having heating elements and a hermetically sealed multi-chip package. The multi-chip package includes a plurality of semiconductor chips, a substrate electrically coupled to the plurality of semiconductor chips, heat dissipation means, and a plurality of thermal interfaces disposed between the semiconductor chips and the heat dissipation means. The heat dissipation means forms a hermetically sealed cavity that encloses the semiconductor chips and at least a portion of the substrate. The circuit board includes a chip mounting surface, a chip mounting area on the chip mounting surface, the chip mounting area including a plurality of lands, and heating elements connected to the lands, the heating elements capable heating a joint formed between the lands and electrode pads of a semiconductor chip.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: April 6, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jeong Moon, Kyu-Jin Lee
  • Patent number: RE41559
    Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom. The metal clip or drain clip has a plurality, a parallel spaced fins extending from its outwardly facing surface.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: August 24, 2010
    Assignee: International Rectifier Corporation
    Inventor: Charles S. Cardwell
  • Patent number: RE41869
    Abstract: In the semiconductor device, a control power MOSFET chip 2 is disposed on the input-side plate-like lead 5, and the drain terminal DT1 is formed on the rear surface of the chip 2, and the source terminal ST1 and gate terminal GT1 are formed on the principal surface of the chip 2, and the source terminal ST1 is connected to the plate-like lead for source 12. Furthermore, a synchronous power MOSFET chip 3 is disposed on the output-side plate-like lead 6, and the drain terminal DT2 is formed on the rear surface of the chip 3 and the output-side plate-like lead 6 is connected to the drain terminal DT2. Furthermore, source terminal ST2 and gate terminal GT2 are formed on the principal surface of the synchronous power MOSFET chip 3, and the source terminal ST2 is connected to the plate-like lead for source 13. The plate-like leads for source 12 and 13 are exposed, and therefore, it is possible to increase the heat dissipation capability of the MCM 1.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: October 26, 2010
    Assignee: Renesas Electronics Corp.
    Inventors: Tetsuya Kawashima, Akira Mishima