Abstract: The present invention provides a conductor package structure that comprises a conductive base. An adhesive layer is formed on the conductive base. An electronic element is formed on the adhesive layer. Conductors form a signal connection between the surface of a filling material and the bottom of the filling material, wherein the filling material is filled in the space between the electronic element and the conductors.

Abstract: A high reliability power module which includes a plurality of hermetically sealed packages each having electrical terminals formed from an alloy of tungsten copper and brazed onto a surface of a ceramic substrate.

Abstract: A method of enabling alignment of a wafer in at least one exposure step of an integrated circuit process after a UV-blocking metal layer is formed over the whole wafer covering a patterned upmost metal layer of the integrated circuit is described, wherein the wafer has an edge portion where a composite dielectric layer corresponding to the dielectric layers of the integrated circuit is formed. The method includes forming a cavity in the composite dielectric layer over the edge portion of the wafer in the patterning process of the upmost metal layer, such that an alignment mark is formed after the UV-blocking metal layer is formed.

Abstract: On a single semiconductor package PK1, m semiconductor chips CP1 to CPm are mounted, and the semiconductor package PK1 has external terminals T shared by m pad electrodes PD1 to PDm of the m semiconductor chips CP1 to CPm. An electrostatic protection circuit CD is mounted on only one CPm of the m semiconductor chips CP1 to CPm.

Abstract: A chip package including a shielding layer conformally covering the underlying molding compound for is provided. The shielding layer can smoothly cover the molding compound and over the rounded or blunted, top edges of the molding compound, which provides better electromagnetic interferences shielding and better shielding performance.

Abstract: An electronic device comprises an electronic element package and a mounting substrate on which the electronic element package is mounted. The electronic element package has an LGA electrode. The mounting substrate has a through-hole having a conductor which covers an inner wall. The LGA electrode has an area larger than an opening area of the through-hole on a side facing the LGA electrode. The electronic element package is mounted on the mounting substrate so that at least a part of the opening of the through-hole overlaps with the LGA electrode. The LGA electrode and the conductor of the through-hole are electrically connected to a conductive material provided inside the through-hole. In the LGA electrode, at least a part of the region that does not overlap with the opening of the through-hole is joined to the mounting substrate by an adhesive.

Abstract: An electronic device includes a packaged integrated circuit having an integrated circuit die having an active surface, and a molding compound overlaying the active surface of the integrated circuit die. In a particular embodiment, the packaged integrated circuit includes at least approximately five weight percent (5 wt %) zinc relative to the molding compound. In another embodiment, the packaged integrated circuit includes approximately 0.3 ?mol/cm2 of zinc in an area parallel to the active surface of the integrated circuit die.

Abstract: A semiconductor device is made by forming an interconnect structure over a substrate. A semiconductor die is mounted to the interconnect structure. The semiconductor die is electrically connected to the interconnect structure. A ground pad is formed over the interconnect structure. An encapsulant is formed over the semiconductor die and interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the interconnect structure to isolate the semiconductor die with respect to inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. A backside interconnect structure is formed over the interconnect structure, opposite the semiconductor die.

Abstract: An apparatus and method uses a first Faraday cage portion and a second Faraday cage portion to provide a Faraday cage enclosure surrounding at least one circuit device.

Abstract: A semiconductor package has a first substrate having a plurality of metal traces. At least one die is electrically coupled to the first surface of the first substrate. A plurality of land pads is formed on the first surface of the first substrate. A mold compound encapsulates portions of the die and portions of the first surface of the first substrate. A conductive coating is applied to the mold compound and electrically coupled to at least one metal trace. A non-conductive coating is formed over the conductive coating and portions of the mold compound. A plurality of vias is formed through the non-conductive coating and the mold compound to expose the land pads.

Abstract: A semiconductor device is made by providing a substrate having an interconnect structure, providing a plurality of semiconductor die each having a through silicon via (TSV), mounting the semiconductor die to the substrate to electrically connect the TSV to the interconnect structure, depositing an encapsulant between the semiconductor die, and forming a shielding layer over the encapsulant and semiconductor die. The shielding layer is electrically connected to the TSV which in turn electrically connects to the interconnect structure to isolate the semiconductor die from interference. The shielding layer is electrically connected to a ground potential through the TSV and interconnect structure. The semiconductor die includes solder bumps which are electrically connected to contact pads on the substrate. The substrate also includes solder bumps electrically connected to a conductive channel in the interconnect structure which is electrically connected to the TSV.

Abstract: A semiconductor package has a first conductive layer formed on a top surface of a substrate. A conductive via is formed between the first conductive layer and a bottom surface of the substrate. A semiconductor component is mounted to the substrate and electrically connected to the first electrical contact pad. The semiconductor component can be a flip chip semiconductor device, wire bond semiconductor device, or passive component. An encapsulant is deposited over the semiconductor component. The encapsulant extends into a channel formed on a side of the substrate from the top surface to the bottom surface of the substrate. An interconnect structure is formed over the bottom surface of the substrate. A heat spreader structure can be disposed over the semiconductor component. An EMI shield can be disposed over the semiconductor component. A plurality of semiconductor components can be stacked in a package-in-package arrangement.

Abstract: A semiconductor device is made by mounting a semiconductor die over a carrier. A ferromagnetic inductor core is formed over the carrier. A prefabricated pillar frame is formed over the carrier, semiconductor die, and inductor core. An encapsulant is deposited over the semiconductor die and inductor core. A portion of the pillar frame is removed. A remaining portion of the pillar frame provides an interconnect pillar and inductor pillars around the inductor core. A first interconnect structure is formed over a first surface of the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant. The first and second interconnect structures are electrically connected to the inductor pillars to form one or more 3D inductors. In another embodiment, a shielding layer is formed over the semiconductor die. A capacitor or resistor is formed within the first or second interconnect structures.

Abstract: A semiconductor device includes: an insulating substrate; a stepwise layer arranged on the insulating substrate and having an end portion whose inclination angle is equal to or greater than 60°; an insulating layer formed on the insulating substrate and the stepwise layer so as to be elevated on the stepwise layer; a first semiconductor layer arranged at a portion adjacent to the elevated insulating layer; and a second semiconductor layer structured with a material identical to that of the first semiconductor layer, and formed in an island shape on the elevated insulating layer.

Abstract: A semiconductor device has a substrate containing a conductive layer. An interconnect structure is formed over the substrate and electrically connected to the conductive layer. A semiconductor component is mounted to the substrate. An encapsulant is deposited over the semiconductor component and interconnect structure. A channel is formed in the encapsulant to expose the interconnect structure. Solder paste is deposited in the channel prior to forming the shielding layer. A shielding layer is formed over the encapsulant and semiconductor component. The shielding layer can be conformally applied over the encapsulant and semiconductor die and into the channel. The shielding layer extends into the channel and electrically connects to the interconnect structure. A docking pin is formed on the shielding layer, which extends into the channel and electrically connects to the interconnect structure. A chamfer area is formed around a perimeter of the shielding layer.

Abstract: A semiconductor device includes: a semiconductor substrate; a semiconductor element formed on a principal surface of the semiconductor substrate and having a multiple-layered interconnect layer; and a heterostructure magnetic shield covering the semiconductor element. The heterostructure magnetic shield includes a first magnetic shield layered structure and a second magnetic shield layered structure that covers the first magnetic shield layered structure. Each of a first and a second magnetic shield layered structures includes a magnetic shielding film composed of a magnetic substance and covering the semiconductor element and a buffer film disposed between the semiconductor element and the magnetic shield films and preventing a diffusion of the magnetic substance.

Abstract: A microelectronic device is made of a semiconductor substrate, a heat generating component in a layer thereof, and a body within the remaining semiconductor substrate. The body is made of materials which have a high thermal inertia and/or thermal conductivity. When high thermal conductivity materials are used, the body acts to transfer the heat away from the substrate to a heat sink.

Abstract: Integrated circuit devices include a semiconductor substrate and a flux line generating passive electronic element on the semiconductor substrate. A dummy gate structure is arranged on the semiconductor substrate in a region below the passive electronic element. The dummy gate includes a plurality of segments, each segment including a first longitudinally extending part and a second longitudinally extending part. The second longitudinally extending part extends at an angle from an end of the first longitudinally extending part. Ones of the segments extend at a substantially same angle and are arranged displaced from each other in an adjacent nested relationship.

Abstract: A panel has a baseplate with an upper first metallic layer and a multiplicity of a vertical semiconductor components. The vertical semiconductor components in each case have a first side with a first load electrode and a control electrode and an opposite second side with a second load electrode. The second side of the semiconductor components is in each case mounted on the metallic layer of the baseplate. The semiconductor components are arranged in such a way that edge sides of adjacent semiconductor components are separated from one another. A second metallic layer is arranged in separating regions between the semiconductor components.

Abstract: An electronic device includes a substrate, an active circuit, and a shielding structure. The active circuit is formed on the substrate. The shielding structure is disposed surrounding the active circuit, and includes a first heavy ion-doped region, first metal stack, second heavy ion-doped region, second metal stack and top metal. The first heavy ion-doped is formed in the substrate and located at a first side of the active circuit. The first metal stack is formed on the first heavy ion-doped region of the substrate, wherein the first metal stack is connected to a ground voltage. The second heavy ion-doped region is formed in the substrate and located at a second side of the active circuit. The second metal stack is formed on the second heavy ion-doped region of the substrate. The top metal is formed on the first metal stack and second metal stack and passing over the active circuit.

Abstract: A semiconductor device includes a pre-fabricated shielding frame mounted over a sacrificial substrate and semiconductor die. An encapsulant is deposited through an opening in the shielding frame around the semiconductor die. A first portion of the shielding frame to expose the encapsulant. Removing the first portion also leaves a second portion of the shielding frame over the semiconductor die as shielding from interference. A third portion of the shielding frame around the semiconductor die provides a conductive pillar. A first interconnect structure is formed over a first side of the encapsulant, shielding frame, and semiconductor die. The sacrificial substrate is removed. A second interconnect structure over the semiconductor die and a second side of the encapsulant. The shielding frame can be connected to low-impedance ground point through the interconnect structures or TSV in the semiconductor die to isolate the die from EMI and RFI, and other inter-device interference.

Abstract: A technology is provided which allows a reduction in the size of a semiconductor device without degrading an electromagnetic shielding effect and reliability against reflow heating. After a plurality of components are mounted over a component mounting surface of a module substrate, a resin is formed so as to cover the mounted components. Further, over surfaces (upper and side surfaces) of the resin, a shield layer including a laminated film of a Cu plating film and an Ni plating film is formed. In the shield layer, a plurality of microchannel cracks are formed randomly along grain boundaries and in a net-like configuration without being coupled to each other in a straight line, and form a plurality of paths extending from the resin to a surface of the shield layer by the microchannel cracks.

Abstract: An electronic device and a method of packaging an electronic device are disclosed. In one embodiment, the electronic device can include a first die. The electronic device can also include a dielectric layer defining a first opening. The first die can be disposed within the first opening. Further, the electronic device can include an encapsulating material disposed adjacent to the first die. The encapsulating material can have a different composition as compared to the dielectric layer. In a particular embodiment, the electronic device can also include an electrically conductive carrier contacting the dielectric layer and the encapsulating material.

Abstract: An improved photodiode detector shielding apparatus and method are provided which shield a photodiode detector from electromagnetic interference and ambient light, without affecting the wavelengths of light that reach the photodiode. The improved photodiode detector shield has two layers. A bottom layer is substantially made from an electrically conducting material and is fixed over a photodiode in order to shield it from EMI and ambient light. A top layer is substantially made from a lustrous, shiny, reflective material that reflects an equal amount of light across a band of wavelengths. Both layers have areas with optically transmissive openings, which are aligned to allow for the unobstructed passage of light of a band of wavelengths to the photodiode. Light within a band of wavelengths is evenly reflected off the top of the first surface and also reaches the photodiode.

Abstract: An integrated circuit structure is disclosed. The integrated circuit structure includes a first package substrate including a radiating element, the radiating element having a radiating element connection extending from the radiating element. The integrated circuit structure further includes a first chip positioned adjacent to the radiating element connection, the first chip having a first chip connection on a surface of the first chip, wherein the first chip connection forms a capacitive coupling with the radiating element connection. A method of forming an integrated circuit structure is also disclosed.

Abstract: A semiconductor device includes: a first region, a second region and a third region surrounding the second region; an integrated circuit including an active element in the first region and provided in and above a first substrate; an antenna which is provided in the second region, connected to the integrated circuit and configured to receive or transmit a high-frequency signal; and a first shield layer which is grounded and includes a stack of a plurality of conductive layers in the third region.

Abstract: A semiconductor device 100 includes a semiconductor substrate 14, a connection electrode 12 disposed on an upper surface of the semiconductor substrate 14 and connected to an integrated circuit thereon, a through electrode 20 which penetrates the semiconductor substrate 14 and the connection electrode 20, and an insulation portion 30 interposed between the semiconductor substrate 14 and the through electrode 20. The through electrode 20 is integrally formed to protrude outward from upper surfaces of the semiconductor substrate 14 and the connection electrode 12, and connected to the connection electrode 12 in a region where the through electrode 20 penetrates the connection electrode 12.

Abstract: An electronic part (100) that shields parts on a substrate (101) includes a plurality of chip parts (102) each having on a respective end portion a ground terminal (103A) and an electrode terminal (103B) that supplies a voltage source, and located at regular intervals on the substrate with the respective ground terminals aligned, the ground terminal and the electrode terminal being electrically connected to a ground terminal land (107A) and an electrode terminal land (107B) of the substrate respectively; and a shielding case (104) that shields the plurality of chip parts and includes an opening (105) through which a resin is to be provided for securing strength of the respective electrical connection points of the ground terminal land and the electrode terminal land of the substrate with the ground terminal and the electrode terminal of the chip parts; the opening being formed such that an edge (106) of the opening becomes parallel to the ground terminal of the respective chip parts, and such that upon being

Abstract: A semiconductor product including a substrate, a semiconductor chip fitted to the substrate, and a layer, which contains coated particles, located adjacent to the semiconductor chip, wherein the coated particles have a ferromagnetic, ferrimagnetic or paramagnetic core and a coating.

Abstract: A semiconductor device comprises a copper redistribution line, a copper inductor and aluminum wire bond pads and the integration of the resulting device with an integrated circuit on a single chip, resulting in the decreased size of the chip.

Abstract: A semiconductor package including at least a sensing component and a shielding layer is provided. While the shielding layer disposed over the molding compound can protect the semiconductor package from EMI radiations, the sensing component of the package is not blocked by the shielding layer for the feasibility of receiving the sensing signal.

Abstract: A security chip is disclosed. The security chip includes: a substrate; an integrated circuit disposed on the substrate, the integrated circuit including circuit elements, circuit interconnect layers connecting the circuit elements together, and interlayer contacts supporting the circuit interconnect layers; a shield to at least partially shield the integrated circuit; and at least one lightwell in the shield and the integrated circuit, wherein each lightwell has a closed shape formed from parts of the circuit interconnect layers and interlayer contacts, wherein no exploitable voltage can be measured on the parts of the circuit interconnect layers and interlayer contacts, and wherein each lightwell forms a path for light to penetrate to the substrate preventing the light from reaching the circuit elements. Related apparatus and methods are also disclosed.

Abstract: A chip package including at least a shielding layer for better electromagnetic interferences shielding is provided. The shielding layer disposed over the top surface of the laminate substrate can protect the chip package from the underneath EMI radiation. The chip package may further include another shielding layer over the molding compound of the chip package.

Abstract: A shield for an integrated circuit comprising an upper wall and a side wall assembly. The upper wall includes a top surface, a bottom surface and a perimeter. The side wall assembly depends from the perimeter of the upper wall. The side wall assembly has a proximal end, a distal end, an inner surface and an outer surface. The distal end defines a lower edge. At least a portion of the side wall assembly includes a plurality of surface variations along a length thereof, to, in turn, define a lower edge of the side wall assembly having a non-linear configuration. Such a non-linear configuration increases the rigidity of the shield.

Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a grounding element disposed adjacent to a periphery of a substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit. The grounding element includes an indented portion that is disposed adjacent to a lateral surface of the substrate unit. The semiconductor device package also includes an EMI shield that is electrically connected to the grounding element and is inwardly recessed adjacent to the indented portion of the grounding element.

Abstract: Light in the visible spectrum is modulated using an array of modulation elements, and control circuitry connected to the array for controlling each of the modulation elements independently, each of the modulation elements having a surface which is caused to exhibit a predetermined impedance characteristic to particular frequencies of light. The amplitude of light delivered by each of the modulation elements is controlled independently by pulse code modulation. Each modulation element has a deformable portion held under tensile stress, and the control circuitry controls the deformation of the deformable portion. Each deformable element has a deformation mechanism and an optical portion, the deformation mechanism and the optical portion independently imparting to the element respectively a controlled deformation characteristic and a controlled modulation characteristic. The deformable modulation element may be a non-metal.

Abstract: A package structure for a wireless communication module is disclosed and includes: a substrate having an upper surface defining a supporting region, an annular ground pad surrounding the supporting region, and at least one auxiliary ground pad formed in the supporting region; at least one chip mounted on the supporting region and electrically connected to the substrate; and a shielding lid having a receiving space for receiving the chip, a ground end surface electrically connected to the annular ground pad of the substrate, and at least one auxiliary ground portion electrically connected to the auxiliary ground pad for forming at least one auxiliary ground pathway to adjust the characteristic of the enhanced peak generated by the cavity-resonance effect of the shielding lid. Thus, the enhanced peak can be shifted out of a regulated frequency range of the EMI shielding test, so that the yield thereof can be increased.

Abstract: This invention provides a magnetic shielding package structure of a magnetic memory device, in which at least a magnetic memory device is embedded between a magnetic shielding substrate and a magnetic shielding layer. A plurality of through vias is formed in the magnetic shielding substrate or the magnetic shielding layer, and a plurality of conductive contacts passes through the through vias such that electrical connection between the magnetic memory device and the external is established.

Abstract: Pad structures and methods for forming such pad structures are provided. For the pad structure, the first conductive material layer has a first hardness over about 200 kg/mm2. The second conductive material layer is over the first conductive material layer and has a second hardness over about 80 kg/mm2. For the method of forming the pad structure, a plurality of first conductive material layers is formed within each of a plurality of openings of a substrate. The substrate has a plurality of openings therein. The first conductive material layers are formed within each of the openings of the substrate. The first conductive material layers substantially have a round top surface. The second conductive material layers are formed and substantially conformal over the first conductive material layers. The second conductive material layers cover a major portion of the round top surface of the first conductive material layers.

Abstract: An apparatus on a wafer, comprising; a first metal layer of a wall, a second metal layer of the wall, a third metal layer of the wall comprising; one or more base frames, a fourth metal layer of the wall comprising; one or more vertical frame pairs each on top of the one or more base frames and having a pass-thru therein, a fifth metal layer of the wall comprising; one or more top frames each over the pass-thru; and a metal lid.

Abstract: A method and apparatus for thermally processing a substrate is provided. A substrate is disposed within a processing chamber configured for thermal processing by directing electromagnetic energy toward a surface of the substrate. An energy blocker is provided to block at least a portion of the energy directed toward the substrate. The blocker prevents damage to the substrate from thermal stresses as the incident energy approaches an edge of the substrate.

Abstract: A semiconductor chip package includes a main board; a ceramic substrate having a cavity within which at least one chip is electrically mounted, the cavity being placed at a lower portion of the ceramic substrate facing the main board; and a conductive shielding layer provided with a predetermined thickness on the outside of the ceramic substrate. The ceramic substrate includes: at least one first ground line electrically connecting the conductive shielding layer with the main board; at least one second ground line electrically connecting the conductive shielding layer with the chip; and at least one signal line electrically connecting the chip with the main board. Thus, manufacturing costs are lowered because of the reduced number of components being used, miniaturization in device design can be achieved because of the small volume of the package, and the ground performance can be improved.

Abstract: Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., M1). An inductor is formed in a second metal level (e.g., M5) above the first metal level and is aligned over and electrically connected in parallel to the ESD device by a single vertical via stack. The inductor is configured to nullify, for a given application frequency, the capacitance value of the ESD device. The quality factor of the inductor is optimized by providing, on a third metal level (e.g., M3) between the second metal level and the first metal level, a shield to minimize inductive coupling. An opening in the shield allows the via stack to pass through, trading off Q factor reduction for size-scaling and ESD robustness improvements.

Abstract: A semiconductor package includes a wire board, a plurality of semiconductor chips configured to be stacked over the wire board and to be electrically coupled with the wire board, and at least one shielding unit configured to be formed between the plurality of semiconductor chips and to be maintained at a predetermined voltage.

Abstract: To provide a technique that can improve the data retention characteristic of an MRAM device by improving the resistance against an external magnetic field in a semiconductor device including the MRAM device. A first magnetic shield material is disposed over a die pad via a first die attach film. Then, a semiconductor chip is mounted over the first magnetic shield material via a second die attach film. Furthermore, a second magnetic shield material is disposed over the semiconductor chip via a third die attach film. That is, the semiconductor chip is disposed so as to be sandwiched by the first magnetic shield material and the second magnetic shield material. At this time, while the planar area of the second magnetic shield material is smaller than that of the first magnetic shield material, the thickness of the second magnetic shield material is thicker than that of the first magnetic shield material.

Abstract: A semiconductor device has a substrate comprising at least one dielectric layer and at least one metal layer on a first surface of the substrate. A die is attached to the first surface of the substrate. A mold compound is used to encapsulate the die and partially encapsulate the first surface of the substrate. The mold compound has a protrusion proximate to the at least one metal layer. A conductive material covers the mold compound, including the protrusion, and contacts the at least one metal layer.

Abstract: A high reliability radiation shielding integrated circuit apparatus comprising a plurality of package layers; a radiation shielding lid or base coupled to the plurality of package layers; wherein the circuit die are shielded from receiving an amount of radiation greater than the total dose of tolerance of the circuit die. In one embodiment, an integrated circuit apparatus for use in high reliability applications is disclosed. The integrated circuit apparatus is designed to be highly reliable and protect integrated circuit die from failing or becoming unreliable due to radiation, mechanical forces, thermal exposure, or chemical contaminates.

Abstract: A total ionizing dose suppression architecture for a transistor and a transistor circuit uses an “end cap” metal structure that is connected to the lowest potential voltage to overcome the tendency of negative charge buildup during exposure to ionizing radiation. The suppression architecture uses the field established by coupling the metal structure to the lowest potential voltage to steer the charge away from the critical field (inter-device) and keeps non-local charge from migrating to the “birds-beak” region of the transistor, preventing further charge buildup. The “end cap” structure seals off the “birds-beak” region and isolates the critical area. The critical area charge is source starved of an outside charge. Outside charge migrating close to the induced field is repelled away from the critical region. The architecture is further extended to suppress leakage current between adjacent wells biased to differential potentials.

Abstract: A semiconductor package includes an electromagnetic shielding member for shielding electromagnetic waves. An antenna is disposed on an upper face of the electromagnetic shielding member and includes an antenna part with a plurality of conductive particles electrically connected with each other and an insulation part disposed on the upper face of the electromagnetic shielding member and insulating the antenna part. Ball lands are disposed on the electromagnetic shielding member and are electrically connected with the antenna part. A Radio Frequency Identification (RFID) chip is electrically connected to the ball lands.

Abstract: An integrated circuit is disclosed having through silicon vias spaced apart one from another and conductors, each coupled to one or more of the through silicon vias, the conductors in aggregate in use forming a segmented conductive plane maintained at a same potential and forming an electromagnetic shield.