Abstract: A disclosed substrate having a built-in semiconductor chip includes the built-in semiconductor chip, a resin member having the built-in semiconductor chip contained therein and external connection terminals. The resin member contains a resin and 60 to 90% by weight of spherical filler.

Abstract: An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at least one of the plurality of conductive contacts. A conductive material is positioned in the at least one through hole substantially filling the through hole. At least one conductive member is positioned on the conductive material in the through hole and in electrical contact with the conductive material. The electronic package improves field operating life of an assembly which includes a semiconductor chip attached to a second surface of the substrate and a printed wiring board attached to the conductive members.

Abstract: In a method for producing a cover for a region of a substrate, first a frame structure is produced in the region of the substrate, and then a cap structure is attached to the frame structure so that the region under the cap structure is covered. Thus, sensitive devices may be protected easily and at low cost from external influences and particularly from a casting material for casting the entire packaged device, which results when a diced chip is cast.

Abstract: A method and system to form a refractory metal layer over a substrate includes introduction of a reductant, such as PH3 or B2H6, followed by introduction of a tungsten containing compound, such as WF6, to form a tungsten layer. It is believed that the reductant reduces the fluorine content of the tungsten layer while improving the step coverage and resistivity of the tungsten layer. It is believed that the improved characteristics of the tungsten film are attributable to the chemical affinity between the reductants and the tungsten containing compound. The chemical affinity provides better surface mobility of the adsorbed chemical species and better reduction of WF6 at the nucleation stage of the tungsten layer. The method can further include sequentially introducing a reductant, such as PH3 or B2H6, and a tungsten containing compound to deposit a tungsten layer. The formed tungsten layer can be used as a nucleation layer followed by bulk deposition of a tungsten layer utilizing standard CVD techniques.

Abstract: The present invention reduces the effective dielectric constant of the interlayer insulating film while inhibiting the decrease of the reliability of the semiconductor device, which otherwise is caused by a moisture absorption. A copper interconnect comprising a Cu film 209 is formed in multilayer films comprising a L-Ox™ film 203 and a SiO2 film 204. Since the L-Ox™ film 203 comprises ladder-shaped siloxane hydride structure, the film thickness and the film characteristics are stable, and thus changes in the film quality is scarcely occurred during the manufacturing process.

Abstract: Methods and apparatuses for wafer support and release using sacrificial materials in wafer processing. In one embodiment, a solution of a sacrificial polymer is spray-coated on the wafer bump side to form a thin layer of the sacrificial polymer after solvent vaporization. An adhesive layer is then used to attach the wafer bump side onto a wafer support substrate over the sacrificial polymer to support the wafer in backside processing. After wafer thinning and backside metal deposition, the wafer is exposed to heat to thermally decompose the sacrificial polymer into gases. The decomposition of the sacrificial polymer reduces the adhesion of the adhesive layer to the bump side of the wafer such that, when the support substrate is detached from the wafer, the adhesive layer is detached together with the support substrate from the wafer bump side, leaving almost no residual traces.

Abstract: Solder joints coupling pins to a microelectronic package substrate are enshrouded with an encapsulation material. In this manner, pin movement is limited even if the pin solder subsequently melts.

Abstract: Numerous embodiments of an apparatus and method to stress and warpage of semiconductor packages are described. In one embodiment, a semiconductor die is disposed above a substrate. An encapsulating material is disposed above the substrate and semiconductor die, in which the encapsulating material has a combination of a low coefficient of thermal expansion material and a high coefficient of thermal expansion material.

Abstract: Integrated circuit packages and their manufacture are described, wherein the packages comprise dendrimers or hyperbranched polymers. In some implementations, the dendrimers or hyperbranched polymers include repeat units having one or more ring structures and having surface groups to react with one or more components of a plastic. In some implementations, the dendrimers or hyperbranched polymers have a glass transition temperature of less than an operating temperature of the integrated circuit and form at least a partially separate phase.

Abstract: An electrical component having improved impact resistance and improved tolerance for thermal cycling, without sacrificing high-temperature performance, and without requiring unconventional and expensive manufacturing techniques includes an electric device mounted on a substrate circuit board, and a composite material underfilling, overmolding or encapsulating the electronic device, wherein the composite material includes a thermoset matrix phase and a discontinuous liquid crystal polymer phase dispersed throughout the thermoset matrix phase.