Abstract: A semiconductor device, includes: a semiconductor element having element main surface and element back surface spaced apart from each other in thickness direction and including a plurality of main surface electrodes arranged on the element main surface; a die pad having a die pad main surface where the semiconductor element is mounted; a plurality of leads including at least one first lead arranged on one side in first direction orthogonal to the thickness direction with respect to the die pad, and arranged around the die pad when viewed in the thickness direction; a plurality of connecting members including a first connecting member bonded to the at least one first lead, and configured to electrically connect the main surface electrodes and the leads; and a resin member configured to seal the semiconductor element, a part of the die pad, parts of the leads, and the connecting members.

Abstract: An imaging apparatus is mounted on a moving object and configured to capture an image while moving along a moving direction of the moving object. The imaging apparatus includes a sensor unit including a sensor substrate on which an image sensor is mounted, and a main unit including a main substrate on which an electronic component configured to process an output signal from the sensor substrate is mounted. The imaging apparatus further includes a heat dissipation fin configured to dissipate heat generated in at least one of the sensor unit and the main unit. The heat dissipation fin is provided in a direction substantially parallel to the moving direction.

Abstract: Disclosed is a semiconductor package comprising a lower substrate including a conductive line; a first semiconductor chip on the lower substrate; an under-fill layer between the first semiconductor chip and the lower substrate, the under-fill layer including a central part below the first semiconductor chip and an edge part isolated from direct contact with the central part in a first direction parallel to a top surface of the lower substrate, and a recess region between the central part and the edge part. The recess region may be defined by a sidewall of the central part, a sidewall of the edge part, and a top surface of the conductive line in the lower substrate.

Abstract: Various embodiments described herein provide analog sense points for circuit die, which can form part of an integrated circuit (IC) package and can facilitate measurement of at least a portion of the circuit die using a Kelvin method of measurement.

Abstract: An apparatus includes a first substrate including one or more electrical connection features; and an assembly including: a second substrate; conductive features formed on the second substrate, one or more of which are electrically connected to corresponding electrical connection features of the first substrate; and an electronic component between the second substrate and the first substrate and electrically connected to one or more of the conductive features.

Abstract: A semiconductor device includes a semiconductor chip having a passivation film, a stress relieving layer provided on the passivation film, and a groove formed in a periphery of a surface of the semiconductor chip, the groove being provided inside of an edge of the semiconductor chip, wherein the stress relieving layer is partly disposed in the groove.

Abstract: The invention relates to an optoelectronic component having: a carrier; an optoelectronic semiconductor chip; an insulation layer, which has an electrically insulating material; and a first contact layer, which has an electrically conductive material. According to the invention, the insulation layer is arranged on the carrier and has a cavity; the semiconductor chip is arranged in the cavity; the first contact layer is arranged between the semiconductor chip and the carrier and between the insulation layer and the carrier; and the first contact layer has at least one interruption, such that the carrier is free of the first contact layer at least in some parts in the region of the cavity.

Abstract: A package includes a first package structure and a second package structure stacked on the first package structure. The first package structure includes a redistribution structure, an integrated circuit, an encapsulant, and conductive structures. The integrated circuit is disposed on the redistribution structure and includes a first chip, a second chip, a third chip, and a fourth chip. The first chip includes a semiconductor substrate that extends continuously throughout the first chip. The second and the third chips are disposed side by side on the first chip. The fourth chip is disposed over the first chip and includes a semiconductor substrate that extends continuously throughout the fourth chip. Sidewalls of the first chip are aligned with sidewalls of the fourth chip. The encapsulant laterally encapsulates the integrated circuit. The conductive structures penetrate through the encapsulant.

Abstract: A thermosetting resin composition according to the invention contains: a thermosetting resin component; and silica having an average particle diameter equal to or greater than 0.2 ?m and treated with isocyanate. It is preferable that the content of the silica is in a range of 50% by mass to 300% by mass with respect to the thermosetting resin component. It is also preferable that the thermosetting resin composition contains core shell rubber having content in a range of 20% by mass to 80% by mass with respect to the thermosetting resin component.

Abstract: A light emitting module includes: a base board; and a plurality of divisional planar light emitters disposed adjacent to each other on one surface of the base board. The base board includes: a plurality of conductive parts, a flexible base part joined to the conductive parts, and an insulating base part joined to the flexible base part. Each of the plurality of divisional planar light emitters includes: a plurality of wiring parts electrically connected with corresponding ones of the conductive parts of the base board, a plurality of light emitting elements each disposed on corresponding ones of the wiring parts, and a sealing part sealing the plurality of light emitting elements and facing the insulating base part.

Abstract: Disclosed is a method for packaging a chip, comprising the following steps: providing a baseplate formed with an open slot thereon penetrating through opposite sides of the baseplate; providing a release base material, wherein the release base material is bonded to a first side of the baseplate and covers the open slot; providing a chip, wherein the chip is mounted on the release base material at the position of the open slot; packaging a second side of the baseplate facing away from the release base material so as to form a packaging layer which packages the chip and fixes it on the baseplate; removing the release base material so as to obtain a package structure for the chip.

Abstract: An antenna module includes a first antenna unit including at least one first patch antenna pattern, at least one first feed via, and at least one first dielectric layer, a second antenna unit including at least one second patch antenna pattern, at least one second feed via, and at least one second dielectric layer, a first connection portion, a first rigid substrate electrically connecting the first connection portion to the first antenna unit and having a first surface on which the first antenna unit is disposed, a base connection portion, a flexible substrate having a first surface on which the first connection portion is disposed and a second surface on which the base connection portion is disposed, and an IC electrically connected to the flexible substrate through the second surface of the flexible substrate or the first rigid substrate.

Abstract: An optical ferrule connector is provided. The optical ferrule connector includes a body including a beveled surface, a plurality of optical fibers embedded in the body, each of the plurality of optical fibers extending along a transmission direction and terminating in a fiber tip that is oriented coplanar to the beveled surface, and a plurality of optical elements, each optical element of the plurality of optical elements located at an associated fiber tip of an associated optical fiber, each optical element operable to manipulate or otherwise focus light into or out of a core of the associated optical fiber.

Abstract: A package-embedded board includes: a core layer having a through-hole portion; a package at least partially disposed in the through-hole portion and including a die pad, an electronic component disposed on the die pad, and a molded portion covering the electronic component; and a core insulating material disposed in the through-hole portion and covering the core layer and the package.

Abstract: A semiconductor package includes a first semiconductor chip on a wiring structure, a plurality of internal terminals between the wiring structure and the first semiconductor chip; a high thermal conductivity layer is between the wiring structure and the first semiconductor chip; and an encapsulator on the high thermal conductivity layer and contacting the second semiconductor chip. Sidewalls of at least the wiring structure and the encapsulator are substantially coplanar.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a surface. The semiconductor device includes a conductive pad over a portion of the surface. The conductive pad has a curved top surface, and a width of the conductive pad increases toward the substrate. The semiconductor device includes a device over the conductive pad. The semiconductor device includes a solder layer between the device and the conductive pad. The solder layer covers the curved top surface of the conductive pad, and the conductive pad extends into the solder layer.

Abstract: An electrical apparatus includes a semiconductor element, conductors and a covering resin. The conductors are connected to the semiconductor element. At least one of the conductors extends in a first direction. The covering resin covers the semiconductor element and a portion of each of the conductors. The conductors respectively include covering portions and exposing portions. Each of the covering portions is covered by the covering resin. Each of the exposing portions is exposed from the covering resin. The conductors are aligned in a second direction. Two of the exposing portions closest to each other are spaced apart in each of the second direction and a third direction. The third direction is perpendicular to the first direction and the second direction. A shortest separation distance between two closest covering portions is shorter than a shortest separation distance between two closest exposing portions.

Abstract: A packaged semiconductor device includes a first bond pad, a second bond pad, a first bond wire that includes a first end bonded to the first bond pad and a second end bonded to the second bond pad, and a second bond wire that includes a first end that is electrically connected to the first bond pad and a second end that is electrically connected to the second bond pad. The first end of the second bond wire is bonded to the first end of the first bond wire. A method of bonding a bond wire includes bonding a first end of a first bond wire to a contact surface of a first bond pad and bonding a first end of a second bond wire to a surface of the first end of the first bond wire.

Abstract: The present inventions, in one aspect, are directed to micromachined resonator comprising: a first resonant structure extending along a first axis, wherein the first axis is different from a crystal axis of silicon, a second resonant structure extending along a second axis, wherein the second axis is different from the first axis and the crystal axis of silicon and wherein the first resonant structure is coupled to the second resonant structure, and wherein the first and second resonant structures are comprised of silicon (for example, substantially monocrystalline) and include an impurity dopant (for example, phosphorus) having a concentrations which is greater than 1019 cm?3, and preferably between 1019 cm?3 and 1021 cm?3.

Abstract: An antenna module includes a first antenna unit including at least one first patch antenna pattern, at least one first feed via, and at least one first dielectric layer, a second antenna unit including at least one second patch antenna pattern, at least one second feed via, and at least one second dielectric layer, a first connection portion, a first rigid substrate electrically connecting the first connection portion to the first antenna unit and having a first surface on which the first antenna unit is disposed, a base connection portion, a flexible substrate having a first surface on which the first connection portion is disposed and a second surface on which the base connection portion is disposed, and an IC electrically connected to the flexible substrate through the second surface of the flexible substrate or the first rigid substrate.

Abstract: Provided is a semiconductor package comprising a lower package that includes a lower substrate and a lower semiconductor chip, an interposer substrate on the lower package and having a plurality of holes that penetrate the interposer substrate, a thermal radiation structure that includes a supporter on a top surface of the interposer substrate and a plurality of protrusions in the holes of the interposer substrate, and a thermal conductive layer between the lower semiconductor chip and the protrusions of the thermal radiation structure.

Abstract: A package structure and a manufacturing method for the same are provided. The package structure includes a circuit, a mold sealing layer, a conductive metal board, and a conductive layer. The circuit board includes a substrate and a first electronic element disposed on the substrate. The mold sealing layer is disposed on the substrate and covers the first electronic element. The mold sealing layer has a top surface, a bottom surface corresponding to the top surface, and a side surface connected between the top surface and the bottom surface. The conductive metal board is disposed on the top surface and adjacent to the first electronic element. The conductive layer is disposed on the side surface and electrically connected to the conductive metal board. The conductive metal board and the conductive layer are each an independent component.

Abstract: In described examples, a method for fabricating a semiconductor device and a three dimensional structure, and packaging them together, includes: fabricating the integrated circuit on a substrate, immersing the substrate in a liquid encapsulation material, and illuminating the liquid encapsulation material to polymerize the liquid encapsulation material. Immersing the semiconductor device is performed to cover a layer of a platform in the liquid encapsulation material. The platform is a lead frame, a packaging substrate, or the substrate. The illuminating step targets locations of the liquid encapsulation material covering the layer. Illuminated encapsulation material forms solid encapsulation material that is fixedly coupled to contiguous portions of the semiconductor device and of the solid encapsulation material. The immersing and illuminating steps are repeated until a three dimensional structure is formed. The integrated circuit and the three dimensional structure are encapsulated in a single package.

Abstract: A method of forming a chip package is provided. The method includes providing a malleable carrier with a layer of an electrically conductive material formed thereon, and positive fitting the malleable carrier to a chip to at least partially enclose the chip with the malleable carrier. The layer at least partially physically contacts the chip, such that the layer electrically contacts a chip contact of the chip. The layer forms a redistribution layer.

Abstract: A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

Abstract: This disclosure discloses a light-emitting display module display. The light-emitting display module comprises: a board; and a plurality of light-emitting diode modules arranged in an array configuration on the board; wherein one of the light-emitting diode modules comprises a plurality of encapsulated light-emitting units spaced apart from each other; and one of the encapsulated light-emitting units comprises a plurality of optoelectronic units, a first supporting, and a fence; and wherein the plurality of optoelectronic units are covered by the first supporting structure, and the fence surrounds the first supporting structure and the plurality of optoelectronic units.

Abstract: A lead frame includes: a lead portion; a plating layer that is provided on a connected area of the lead portion, the connected area being an area connected with a semiconductor element; a recessed portion that is provided around the plating layer on the lead portion; and an oxidized layer that is provided on a surface including the recessed portion of the lead portion.

Abstract: Packaged surface acoustic wave devices are provided. The packaged surface acoustic wave devices are relatively thin and can have a height of less than 220 micrometers. The packaged surface acoustic wave device includes a photosensitive resin over a conductive structure which may be formed by a plating process. The conductive structure may overlie a cavity-defining structure encapsulating a surface acoustic wave device, the cavity-defining structure including walls and a roof. The photosensitive resin can include a phenol resin. The photosensitive resin can be relatively thin. Edge portions of a piezoelectric substrate can be free from the photosensitive resin.

Abstract: A packaged current sensor integrated circuit includes a primary conductor having an input portion and an output portion configured to carry a current to be measured by a magnetic sensing element supported by a semiconductor die adjacent to the primary conductor. The primary current path contains a mechanical locking feature. The thickness of the molded body of the package is reduced to improve vibration immunity.

Abstract: A heat dissipation structure adapted to dissipate heat from a heat-generating structure includes a heat dissipation unit and a liquid metal layer. The heat dissipation unit includes a heat dissipation body and an anti-corrosion metal layer formed on the heat dissipation body. The liquid metal layer is disposed between the heat-generating structure and the anti-corrosion metal layer, and is opposite to the heat dissipation body. An electronic device that adopts the heat dissipation structure is also disclosed.

Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.

Abstract: Radio-frequency (RF) integrated circuit (IC) (RFIC) packages employing a substrate sidewall partial shield for electro-magnetic interference (EMI) shielding. A RFIC package includes an IC die layer that includes a RFIC die(s) mounted on a substrate that includes substrate metallization layers, a substrate core, and substrate antenna layers. The RFIC package includes an EMI shield surrounding the IC die layer and extending down shared sidewalls of the IC die layer and the substrate. The EMI shield extends down the sidewalls of the IC die layer and substrate metallization layers of the substrate to at least the interface between the substrate metallization layers and the substrate core, and without extending adjacent to the sidewall of the substrate antenna layers. In this manner, antenna performance of the antenna module may not be degraded, because extending the EMI shield down sidewalls of the substrate antenna layers can create a resonance cavity in the substrate.

Abstract: The present disclosure provides a wafer-level chip scale packaging structure and a method for manufacturing the same. The method includes the following steps: 1) providing a first supporting substrate; 2) placing a first chip on the first supporting substrate, and forming a first packaging layer on the first chip; 3) separating the first chip and the surface of the first packaging layer in contact with the first chip from the first supporting substrate, and attaching the other surface of the first packaging layer to a second supporting substrate; 4) disposing a second packaging layer on the surface of the first packaging layer which is in contact with the first chip; 5) forming a rewiring layer on the second packing layer, the rewiring layer is electrically connected to the first chip; and 6) electrically connecting a second chip to the rewiring layer.

Abstract: A semiconductor package includes a first substrate, a second substrate, a conductive component, an electronic component and a passive component. The conductive component is disposed between the first substrate and the second substrate, wherein the first substrate and the second substrate are separated from each other by an interval. The electronic component and the passive component are disposed within the interval.

Abstract: Multi-component modules (MCMs) including configurable electromagnetic interference (EMI) shield structures, and related methods are disclosed. An EMI shield enclosing an IC or another electrical component in an MCM can protect other components within the MCM from EMI generated by the enclosed component. The EMI shield also protects the enclosed component from the EMI generated by other electrical components. An EMI shield with side-wall structures, in which vertical conductors supported by a wall medium electrically couple a lid of the EMI shield to a ground layer in a substrate, provides configurable EMI protection in an MCM. The EMI shield may also be employed to increase heat dissipation. The side-wall structures of the EMI shield are disposed on one or more sides of an electrical component and are configurable to provide a desired level of EMI isolation.

Abstract: A semiconductor device includes a substrate that includes an opening extending through a thickness of the substrate, a frame that includes an integrated circuit (IC) die pad in the opening and a plurality of arms extending outwardly from the IC die pad, an IC mounted on the IC die pad, a plurality of bonding elements electrically coupling the substrate with the IC without the frame being an intermediary coupling element, and an encapsulant surrounding the IC, the plurality of bonding elements, and the plurality of arms. The substrate has a first major surface and a second major surface. Each arm is devoid of a contact pad. Each arm has a distal end coupled to the first major surface of the substrate, and each arm has a proximal end disposed over the first major surface of the substrate.

Abstract: In one example, a semiconductor device, comprises a first redistribution layer (RDL) substrate comprising a first dielectric structure and a first conductive structure through the first dielectric structure and comprising one or more first conductive redistribution layers, an electronic component over the first RDL substrate, wherein the electronic component is coupled with the first conductive structure, a body over a top side of the first RDL substrate, wherein the electronic component is in the body, a second RDL substrate comprising a second dielectric structure over the body, and a second conductive structure through the second dielectric structure and comprising one or more second conductive redistribution layers, and an internal interconnect coupled between the first conductive structure and the second conductive structure. Other examples and related methods are also disclosed herein.

Abstract: An acoustic wave device includes an element substrate having piezoelectricity, a functional electrode on a first main surface of the element substrate, an extended wiring line electrically connected to the functional electrode and extending from the first main surface to a side surface of the element substrate, an external terminal electrically connected to the extended wiring line and on a second main surface of the element substrate, a first resin portion to seal the acoustic wave device, and a second resin portion at least between the extended wiring line on the side surface and the first resin portion. The second resin portion has a lower Young's modulus than the first resin portion.

Abstract: A process for producing molded products having portions formed with two separate materials is provided. The process involves forming a first component over a structural core in a first step, and forming a second component that is secured to the first component and the core in a second step. The second component can be formed directly over the first component or can be secured thereto after formation. The first and second components can additionally be formed with indicia thereon, or with recesses within which inserts containing the desired indicia can be positioned. Additionally, the first component can be formed with a ridge disposed on a projection formed on the first component that effectively seals off a portion of the first component when the second component is formed around the core and the first component to ensure the portion of the first component surrounded by the ridge remains visible after formation of the second component.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a package leadframe assembly. The package leadframe includes a plurality of leads. An adhesive is placed on a portion of the plurality of leads. A die pad is placed onto the adhesive. A portion of the die pad overlaps the portion of the plurality of leads. A semiconductor die is attached to the die pad. A molding compound encapsulates the semiconductor die and a portion of the package leadframe assembly.

Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.

Abstract: A dual band transponder comprises a carrier substrate having at least one planar substrate layer. An ultra-high frequency loop antenna is mounted on a first surface of one of the planar substrate layers of the carrier substrate. A high frequency loop antenna is mounted on two opposite surfaces of one of the planar substrate layers of the carrier substrate. The ultra-high frequency loop antenna encloses the high frequency loop antenna in a plane parallel to the at least one planar substrate layer entirely. A textile label includes a textile label substrate and a corresponding dual band transponder mounted onto the textile label substrate.

Abstract: In one example, a semiconductor device, comprises a first redistribution layer (RDL) substrate comprising a first dielectric structure and a first conductive structure through the first dielectric structure and comprising one or more first conductive redistribution layers, an electronic component over the first RDL substrate, wherein the electronic component is coupled with the first conductive structure, a body over a top side of the first RDL substrate, wherein the electronic component is in the body, a second RDL substrate comprising a second dielectric structure over the body, and a second conductive structure through the second dielectric structure and comprising one or more second conductive redistribution layers, and an internal interconnect coupled between the first conductive structure and the second conductive structure. Other examples and related methods are also disclosed herein.

Abstract: The present disclosure provides a method for manufacturing a thermal print head. The method includes: forming an electrode layer on a substrate; and forming a resistor layer including a plurality of heat generating portions connected to the electrode layer. The electrode layer includes a plurality of individual electrodes including a plurality of first striped portions extending in a secondary scan direction and spaced apart in a main scan direction, and a common electrode including a plurality of second striped portions extending in the secondary scan direction. The forming of the resistor layer includes: a coating process of applying a resistor paste in a stripe that overlaps the first striped portions and the second striped portions; a firing process of firing the resistor paste to form a resistor film; and a removal process of removing a removal region in the resistor paste or the resistor film.

Abstract: A component package includes a printed circuit board; a first electronic component disposed in a first region on the printed circuit board; a second electronic component disposed in a second region on the printed circuit board; and a metal wall disposed on the printed circuit board and spatially partitioning the first region and the second region on a plane. The metal wall is directly connected to the printed circuit board.

Abstract: A power converter module includes power transistors and a substrate having a first surface and a second surface that opposes the first surface. A thermal pad is situated on the second surface of the substrate, and the thermal pad is configured to be thermally coupled to a heat sink. The power converter module also includes a control module mounted on a first surface of the substrate. The control module also includes control IC chips coupled to the power transistors. A first control IC chip controls a first switching level of the power converter module and a second control IC chip controls a second switching level of the power converter module. Shielding planes overlay the substrate. A first shielding plane is situated between the thermal pad and the first control IC chip and a second shielding plane is situated between the thermal pad and a second control IC chip.

Abstract: This invention provides an electro-optical module with reduced noise in driving voltage. The invention can include a power supply substrate that is arranged separately from the flexible substrate having a driver, so that the noise of the driving voltage supplied from the power supply substrate is reduced. The electro-optical module includes a first connecting portion connecting a first end of the flexible substrate to a display panel and configured to receive a signal from the driver, and a second connecting portion connecting the first end of the flexible substrate to the display panel and configured to receive the driving voltage from a third connecting portion at a second end of the flexible substrate.

Abstract: A semiconductor device including an insulating circuit board. The insulating circuit board has an insulating plate, a plurality of circuit patterns disposed on a front surface of the insulating plate, any adjacent two of the circuit patterns having a gap therebetween, each circuit pattern having at least one corner, each corner being in a corner area that covers the corner and a portion of each gap adjacent to the corner, and a buffer material containing resin, applied at a plurality of corner areas, to fill the gaps in the plurality of corner areas.

Abstract: A semiconductor package structure includes a chip, a conductive pillar, a dielectric layer, a first patterned conductive layer and a second patterned conductive layer. The chip has a first side with at least a first metal electrode pad and a second side with at least a second metal electrode pad. The conductive pillar, which has a first end and a second end, is disposed adjacent to the chip. The axis direction of the conductive pillar is parallel to the height direction of the chip. The dielectric layer covers the chip and the conductive pillar and exposes the first and second metal electrode pads of the chip and the first and second ends of the conductive pillar. The first patterned conductive layer is disposed on a second surface of the dielectric layer and electrically connected between the second metal electrode pad and the second end of the conductive pillar.