Abstract: A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semiconductor device 14 disposed on the second surface of the wiring substrate 11 and having a connection terminal 14a connected to the flat type external connection terminal 12a, a molding resin 15 for coating the semiconductor device 14 on the second surface of the wiring substrate 11, a card type supporting frame 10a having a concave portion or a hole portion fitting the wiring substrate 11, the semiconductor device 14, and the molding resin 15 in such a manner that the flat type external connection terminal 12a is exposed to the first surface of the wiring substrate 11, and adhesive resin a adhering integrally the flat type external connection terminal 12a, the wiring substrate 11, the semiconductor device 14, the molding resin 15, and the card type supporting frame 10a.

Abstract: A technique of accurately recognizing a semiconductor device and of specifying a package type thereof. By forming, on the package surface, projections having a geometric pattern such as a circle pattern using an ejector pin and by judging only presence or absence of the circular projections using an image processor, it is possible to reduce a risk of recognition failure of the geometric pattern even if the pattern has some omission in the constitutive line thereof or has any addition of a new line. For example, when the circular projections are provided on the surface of a package, an image processor reads only presence or absence of the circular projections even if disconnection of the line or addition of a line should occur, and this allows the circular projections to be always read as being “present”.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present inventions relate to devices, systems and/or methods of encapsulating and fabricating electromechanical structures or elements, for example, accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), filter or resonator. The fabricating or manufacturing microelectromechanical systems of the present invention, and the systems manufactured thereby, employ backside substrate release and/or seal or encapsulation techniques.

Abstract: An electronic package designed to package silicon carbide discrete components for silicon carbide chips. The electronic package allows thousands of power cycles and/or temperature cycles between ?55° C. to 300° C. The present invention can also tolerate continuous operation at 300° C., due to high thermal conductivity which pulls heat away from the chip. The electronic package can be designed to house a plurality of interconnecting chips within the package. The internal dielectric is able to withstand high voltages, such as 1200 volts, and possibly up to 20,000 volts. Additionally, the package is designed to have a low switching inductance by eliminating wire bonds. By eliminating the wire bonds, the electronic package is able to withstand an injection mold.

Abstract: The invention relates to a method for encapsulating an electronic component, in particular a semiconductor, fixed on a carrier, comprising the processing steps of: a) placing at least one foil layer in a mould, b) placing the carrier in contact with the foil layer with the side remote from the component, and c) encapsulating the electronic component with encapsulating material, wherein the foil layer undergoes a treatment whereby the adhesion of the foil layer is increased such that it adheres to the carrier. The invention also relates to a foil material for applying during such a method.

Abstract: A universal substrate and a semiconductor device utilizing the substrate are disclosed in the present invention. The universal substrate mainly comprises a plurality of inner pads and a plurality of outer pads. A plurality of bifurcate wirings and a plurality of fuses are formed on a surface of the substrate. The fuses are connected with the bifurcate wirings in series. By the bifurcate wirings and the fuses, each of the inner pads is electrically connected to all of the outer pads to provide optional electrical disconnections therebetween. Accordingly, the universal substrate can be utilized for connecting chips having various serial arrangements of bonding pads without replacing or manufacturing another substrate.

Abstract: A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semiconductor device 14 disposed on the second surface of the wiring substrate 11 and having a connection terminal 14a connected to the flat type external connection terminal 12a, a molding resin 15 for coating the semiconductor device 14 on the second surface of the wiring substrate 11, a card type supporting frame 10a having a concave portion or a hole portion fitting the wiring substrate 11, the semiconductor device 14, and the molding resin 15 in such a manner that the flat type external connection terminal 12a is exposed to the first surface of the wiring substrate 11, and adhesive resin a adhering integrally the flat type external connection terminal 12a, the wiring substrate 11, the semiconductor device 14, the molding resin 15, and the card type supporting frame 10a.

Abstract: A die for encapsulating an IC structural body having bonding wires with a molten resin is provided with at least one first half having an ejector-pin-through-hole and at least one second half coupled together to form a cavity therebetween. An ejector pin having a mirror-finished surface at a tip end thereof is inserted into the ejector-pin-through-hole and positioned at a position where a surface of the tip end of the ejector pin coincides with an intermediate surface height of a satin-finished surface formed on an upper inner wall of the cavity of the first half. The IC structural body is then encapsulated with a molten resin, and the mirror-finished surface of the ejector pin and the satin-finished surface of the upper inner wall surface of the cavity are stamped on the semiconductor package in substantially the same plane.

Abstract: A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semiconductor device 14 disposed on the second surface of the wiring substrate 11 and having a connection terminal 14a connected to the flat type external connection terminal 12a, a molding resin 15 for coating the semiconductor device 14 on the second surface of the wiring substrate 11, a card type supporting frame 10a having a concave portion or a hole portion fitting the wiring substrate 11, the semiconductor device 14, and the molding resin 15 in such a manner that the flat type external connection terminal 12a is exposed to the first surface of the wiring substrate 11, and adhesive resin a adhering integrally the flat type external connection terminal 12a, the wiring substrate 11, the semiconductor device 14, the molding resin 15, and the card type supporting frame 10a.

Abstract: Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each of the plurality of wire bonds being conductively coupled to a conductive exposed portion, a portion of the conductive exposed portion being positioned in the plane defined by the backside surface, and an encapsulant material positioned adjacent the integrated circuit chip and the plurality of wire bonds.

Abstract: A method for molding digital storage memory cards such as, for example, multimedia cards (MMC), secure digital cards (SD), and similar small form factor digital memory cards. A PCA subassembly including, for example, a leadframe (TSOP) package for enclosing a flash IC and a (e.g., land grad array) controller package for enclosing a controller IC are mounted on a printed wiring board within a mold cavity. A high melt flow index resin is injected into the mold cavity to form an integral, solid body within which to completely encapsulate the flash IC and controller packages and form a cover over top the flash IC package so as to maintain the required memory card height tolerance. In one embodiment, the resin material is injected downwardly into the mold cavity from locations above the respective rows of leads of the flash IC package.

Abstract: Improved encapsulated, overmolded and/or underfilled electrical components having a complete encapsulation, overmolding and/or underfilling with a coefficient of thermal expansion that is uniform and substantially free of gradients includes a polymeric matrix and an inorganic filler having a platelet geometric structure. The platelet structure of the filler allows a desirable coefficient of thermal expansion to be achieved using a very low level of filler material. This low level of filler material facilitates lower viscosity during forming of the encapsulation and/or overmolding, thereby facilitating complete filling of a mold cavity and underfilling of space between a circuit board and a semi-conductor chip electrically connected to the circuit board. In addition, the low viscosity has processing advantages that reduce the potential for damage to electrical components during encapsulation, overmolding and/or underfilling.

Abstract: Provided is a semiconductor package accomplishing a fan-out structure through wire bonding in which a pad of a semiconductor chip is connected to a printed circuit board through wire bonding. A semiconductor package can be produced without a molding process and can be easily stacked on another semiconductor package while the appearance cracks and the warpage defects can be prevented.

Abstract: The present invention provides a method of manufacturing semiconductor device. The method includes providing a semiconductor wafer having a main surface; defining a chip forming region which includes chip regions defined by scribe lines, and a peripheral region which surrounds the chip forming region, on the main surface; forming circuit elements and electrode pads connected to the circuit elements on the chip areas; forming an insulating film, which exposes respective portions of the electrode pads, on the main surface; forming protruded electrodes on the insulating film provided in the chip areas so that the protruded electrodes are arranged at predetermined intervals in the chip area; forming an encapsulating material, which exposes top faces of the protruded electrodes, on the insulating film; and cutting the semiconductor wafer along the scribe lines.

Abstract: A method for hermetically sealing a package includes applying a light or energy active resist to a fill port to act as a temporary hermetic seal, patterning the resist, and applying a solder to the fill port, wherein the solder is configured to serve as a hermetic seal.

Abstract: Methods and apparatus are provided for encapsulating electronic devices, comprising: providing one or more electronic devices (62) with primary faces (63) having electrical contacts (69), opposed rear faces (65) and edges (64) therebetween. A sacrificial layer (70) is provided on the primary faces (63). The devices (62) are mounted on a temporary support (80) so that the sacrificial layer (70) faces toward the temporary support (80). A plastic encapsulation (86)is formed in contact with at least the lateral edges (64) of the electronic devices (62). The plastic encapsulation (86) is at least partially cured and the devices (62) and plastic encapsulation (86) separated from the temporary support (80), thereby exposing the sacrificial layer (70). The sacrificial layer (70) is removed. The devices (62) and edge-contacting encapsulation are mounted on a carrier (90) with the primary faces (63) and electrical contacts (69) exposed and, optionally, further cured.

Abstract: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.

Abstract: A semiconductor component includes a leadframe, a die, upper and lower body segments encapsulating the die, and dummy segments on the leadframe. The dummy segments are configured to vent trapped air in a molding compound during molding of the body segments, such that corners of the body segments do not include the trapped air.

Abstract: A method of making a comparatively small substrate (12) compatible with manufacturing equipment for a larger-size standard substrate is disclosed. The standard substrate (1) has a surface (10) in which a depression (8) is formed, in which depression the small substrate is connected by means of a layer of a bonding material (13). The depression is formed so as to have a flat bottom (9) extending parallel to the surface. The depression has a depth such that, after the small substrate has been connected with its rear side to the bottom of the depression of the standard substrate by means of the layer of bonding material, the front side (14) of the small substrate forms a free surface which practically coincides with the surface (10) of the carrier wafer.

Abstract: A system for degating a packaged semiconductor device that includes a tape substrate includes a first element and a second element. The first element of the system is positionable adjacent to a first major surface of the packaged semiconductor device and includes a receptacle for receiving a portion of a gate of the packaged semiconductor device. A second element of the degating system is positionable adjacent to a second major surface of the packaged semiconductor device and includes a degating element alignable with the gate. The degating element is extendable through the gate to force a portion of the gate and a sprue therein into the receptacle of the first element.

Abstract: A semiconductor package is disclosed with a recess (51) for an integrated circuit die (52). The recess is made by bending or deforming all layers of a package substrate, and therefore the recess contains circuitry to connect to the integrated circuit die. The integrated circuit die is electrically connected to the package substrate by either wirebonds (53a), TAB or die solder balls (53b). The package substrate (50), a single sided printed wiring board, has a thick metal core (100) and one or more thin build up layers.

Abstract: A buffer layer is formed on a substrate and then electronic devices are packed on the buffer layer in the present invention, and problems of lower hermeticity and complex process in the conventional arts can be avoided. Therefore, the present invention provides a packaging structure and method with a better hermeticity and a simpler process. Especially, due to the buffer layer, the planarization for flip-chip bonding can be improved and reduce negative effects of the packing process.

Abstract: In the stacked semiconductor package, on a first semiconductor chip, a second semiconductor chip is stacked offset such that a portion of the first semiconductor chip is exposed. At least one first conductor electrically connects the exposed portion of the first semiconductor chip to the second semiconductor chip. The first conductor may be formed such that the first conductor does not extend beyond a periphery of the first semiconductor chip. The first conductor electrically connects at least one bond pad on the first semiconductor chip with at least one bond pad on the second semiconductor chip, and a redistribution pattern electrically connects the bond pad on the second semiconductor chip to a differently positioned bond pad on the second semiconductor chip.

Abstract: Disclosed are a wafer level stacked package and its manufacturing method. As one example, in such a wafer level stacked package, a first semiconductor die is electrically connected to an upper surface of a substrate and a second semiconductor die is electrically connected to a lower surface of the substrate. That is, with respect to one substrate, semiconductor dies can be stacked on upper and lower surfaces of the substrate. Also, underfill is formed between the respective semiconductor dies and the substrate, thereby enhancing bonding forces between the respective semiconductor dies and the substrate. In addition to stacking the semiconductor dies, packages can be stacked with each other. That is, it is possible to stack a plurality of completed wafer level packages with each other in an up-and-down direction.

Abstract: A module includes a component, a circuit board having the component mounted thereon, a first grounding pattern formed on an outermost periphery of a surface portion of the circuit board; a first sealer provided on the circuit board and having a dimension projected on the circuit board, and a metal film covering the sealer and connected to the grounding pattern. The dimension of the first dealer is smaller than an outside dimension of the circuit board. The first sealer is made of first resin and sealing the component. The module has a low profile and is adequately shielded.

Abstract: To prevent short-circuit due to contact of bonding wires each other and to make a semiconductor device compact. A semiconductor chip with a rectangular main surface may comprise: a first side composing the main surface; a second side opposed to the first side; a main electrode pad group composed of a plurality of main electrode pads, which plurality of main electrode pads is arranged on the main surface along the first side; a first electrode pad group composed of a plurality of first electrode pads, which plurality of first electrode pads is arranged between the first side and the main electrode pad group; a second electrode pad group composed of a plurality of second electrode pads, which plurality of second electrode pads is arranged on the main surface along the second side; a first interconnection connecting the main electrode pad with the first electrode pad; and a second interconnection connecting the main electrode pad with the second electrode pad.

Abstract: An electrical component having improved impact resistance and improved tolerance for thermal cycling, without sacrificing high-temperature performance, and without requiring unconventional and expensive manufacturing techniques includes an electric device mounted on a substrate circuit board, and a composite material underfilling, overmolding or encapsulating the electronic device, wherein the composite material includes a thermoset matrix phase and a discontinuous liquid crystal polymer phase dispersed throughout the thermoset matrix phase.

Abstract: A structure for a chip or chip package is disclosed, with final passivation and terminal metallurgy which are mechanically decoupled but electrically coupled to the multilayer on-chip interconnects. This decoupling allows the chip to survive packaging stresses in the final passivation region, with strain relief from the decoupling region and compliant leads therein, so that on-chip interconnect levels do not feel these external packaging or other stresses. This structure is particularly preferred for on-chip interconnects consisting of Cu and low-k dielectric, the latter having inferior mechanical properties relative to SiO2. The decoupled region extends over all chips on the wafer. It may also extend into the edgeseal or dicing channel region so as to allow chip dicing and retention of this mechanical decoupling all around every chip on the wafer.