Capacitive Arrangements Or Effects Of, Or Between Wiring Layers (epo) Patents (Class 257/E23.144)
  • Patent number: 10446487
    Abstract: A stacked and electrically interconnected structure is disclosed. The stacked structure can include a first element comprising a first contact pad and a second element comprising a second contact pad. The first contact pad and the second contact pad can be electrically and mechanically connected to one another by an interface structure. The interface structure can comprise a passive equalization circuit that includes a resistive electrical pathway between the first contact pad and the second contact pad and a capacitive electrical pathway between the first contact pad and the second contact pad. The resistive electrical pathway and the capacitive electrical pathway form an equivalent parallel resistor-capacitor (RC) equalization circuit.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: October 15, 2019
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Shaowu Huang, Javier DeLaCruz
  • Patent number: 10438636
    Abstract: Write assist circuitry facilitates increased voltage applied to a memory device such as a memory cell or bitcell in changing a logical state of the memory device during a write operation. The write assist circuitry includes a second capacitive line or “metal cap” in addition to a first capacitive line coupled to one of a pair of bitlines to which voltage may be selectively applied. The capacitive lines provide increased write assistance to the memory device. The second capacitive line structurally lies in a second orientation and is formed in an integrated circuit second metal layer relative to the first capacitive line in some embodiments. The additional capacitive line provides negative bitline assistance by selectively driving its corresponding bitlines to be negative during a write operation.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: October 8, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tawfik Ahmed, Amlan Ghosh, Keith A. Kasprak, Ricardo Cantu
  • Patent number: 9947615
    Abstract: An electronic circuit includes a generating circuit for generating a first group of signals and a second group of signals, and a transmission path for transmitting the first group of signals and the second group of signals. The first group of signals are composed of signals synchronized with a first edge that is one of the rising edge and the falling edge of a reference clock, and the second group of signals are composed of signals synchronized with a second edge that is the other of the rising edge and falling edge. The transmission path includes first transmission lines for transmitting the signals composing the first group and second transmission lines for transmitting the signals composing the second group, and the first and second transmission lines are alternately arranged.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: April 17, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideo Kobayashi, Kazuo Yamazaki, Hiroki Hiyama
  • Patent number: 9379021
    Abstract: Embodiments described herein generally relate to methods for forming gate structures. Various processes may be performed on a gate dielectric material to reduce the K value of the dielectric material. The gate dielectric having a reduced K value may provide for reduced parasitic capacitance and an overall reduced capacitance. The gate dielectric may be modified without thermodynamic constraint.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: June 28, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ellie Y. Yieh, Ludovic Godet, Srinivas D. Nemani
  • Patent number: 8928139
    Abstract: Embodiments described herein provide enhanced integrated circuit (IC) devices. In an embodiment, an IC device includes a substrate, an IC die coupled to a surface of the substrate, a first wirelessly enabled functional block located, on the IC die, the first wirelessly enabled functional block being configured to wirelessly communicate with a second wirelessly enabled functional block located on the substrate, and a ground ring configured to provide electromagnetic shielding for the first and second wirelessly enabled functional blocks.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: January 6, 2015
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Michael Boers, Ahmadreza Rofougaran, Arya Behzad, Jesus Castaneda
  • Patent number: 8884428
    Abstract: Embodiments described herein provide enhanced integrated circuit (IC) devices. In an embodiment, an IC device includes a substrate, an IC die coupled to a surface of the substrate, a first wirelessly enabled functional block located, on the IC die, the first wirelessly enabled functional block being configured to wirelessly communicate with a second wirelessly enabled functional block located on the substrate, and a ground ring configured to provide electromagnetic shielding for the first and second wirelessly enabled functional blocks.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: November 11, 2014
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Michael Boers, Ahmadreza Rofougaran, Arya Behzad, Jesus Castaneda
  • Patent number: 8847349
    Abstract: An integrated circuit (IC) package including an IC die and a conductive ink printed circuit layer electrically connected to the IC die.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 30, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Matthew David Romig, Lance Cole Wright, Leslie Edward Stark, Frank Stepniak, Screenivasan K. Koduri
  • Patent number: 8847356
    Abstract: Embodiments of the present invention provide a component-built-in wiring board capable of preventing a defect, such as a crack, resulting from stress concentration at a corner, when a component is accommodated in a housing portion of a core material with resin filler filled therebetween. The component-built-in wiring board can include a component accommodated in the housing portion of a core material, and a laminate portion in which insulating layers and conductor layers are laminated alternately on the core material. A gap between the housing portion of the core material and the component can be filled with a resin filler. In an inner circumferential portion of the housing portion of the core material a first straight chamfered portion is formed at each corner of a rectangle, and in an outer circumferential portion of the component a second straight chamfered portion is formed at each corner of a rectangle.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: September 30, 2014
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Kenichi Saita, Shinya Miyamoto, Daisuke Yamashita, Shinya Suzuki, Hirohito Hashimoto
  • Patent number: 8802532
    Abstract: Disclosed are example bipolar transistors capable of reducing the area of a collector, reducing the distance between a base and a collector, and/or reducing the number of ion implantation processes. A bipolar transistor may includes a trench formed by etching a portion of a semiconductor substrate. A first collector may be formed on the inner wall of the trench. A second collector may be formed inside the semiconductor substrate in the inner wall of the trench. A first isolation film may be formed on the sidewall of the first collector. An intrinsic base may be connected to the third collector. An extrinsic base may be formed on the intrinsic base and inside the first isolation film. A second isolation film may be formed on the inner wall of the extrinsic base. An emitter may be formed by burying a conductive material inside the second isolation film.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: August 12, 2014
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Nam Joo Kim
  • Patent number: 8766449
    Abstract: Disclosed is a variable interconnect geometry formed on a substrate that allows for increased electrical performance of the interconnects without compromising mechanical reliability. The compliance of the interconnects varies from the center of the substrate to edges of the substrate. The variation in compliance can either be step-wise or continuous. Exemplary low-compliance interconnects include columnar interconnects and exemplary high-compliance interconnects include helix interconnects. A cost-effective implementation using batch fabrication of the interconnects at a wafer level through sequential lithography and electroplating processes may be employed.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: July 1, 2014
    Assignee: Georgia Tech Research Corporation
    Inventors: Suresh K. Sitaraman, Karan Kacker, Thomas Sokol
  • Patent number: 8729706
    Abstract: A method for forming a semiconductor structure includes forming a sacrificial layer over a substrate. A first dielectric layer is formed over the sacrificial layer. A plurality of conductive structures are formed within the sacrificial layer and the first dielectric layer. The sacrificial layer is treated through the first dielectric layer, at least partially removing the sacrificial layer and forming at least one air gap between two of the conductive structures. A surface of the first dielectric layer is treated, forming a second dielectric layer over the first dielectric layer, after the formation of the air gap. A third dielectric layer is formed over the second dielectric layer. At least one opening is formed within the third dielectric layer such that the second dielectric layer substantially protects the first dielectric layer from damage by the step of forming the opening.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: May 20, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu
  • Patent number: 8723244
    Abstract: A semiconductor device includes a first storage electrode, a second storage electrode, a first landing pad, a capacitive insulating film, and a plate electrode. The second storage electrode is arranged above the first storage electrode. The first landing pad is arranged between a top surface of the first storage electrode and a bottom surface of the second storage electrode. The first landing pad connects the first storage electrode and the second storage electrode. The first landing pad has a first landing surface larger than the bottom surface of the second storage electrode. The second storage electrode is placed on the first landing surface. The capacitive insulating film is laminated on the first and second storage electrodes and on an outer circumferential surface of the first landing pad. The plate electrode contacts the capacitive insulating film.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: May 13, 2014
    Inventor: Takashi Miyajima
  • Patent number: 8723321
    Abstract: The peeling stress between a Cu line and a capping layer thereon, after via patterning, is reduced by varying the shape of the via and positioning the via to increase the space between the via and the line edge, thereby increasing electromigration lifetime. Embodiments include varying the shape of the via, as by forming an oval or rectangular shape via, such that the ratio of the minor axis of the oval to the line with or the ratio of the width of the rectangle to the line width is less than about 0.7.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: May 13, 2014
    Assignee: GLOBALFOUNDIES Inc.
    Inventors: Christy Woo, Jun “Charlie” Zhai, Paul Besser, Kok-Yong Yiang, Richard C. Blish, Christine Hau-Riege
  • Patent number: 8653666
    Abstract: A semiconductor storage device comprises a peripheral circuit region including a wiring layer having wiring patterns, a cavity formed in a non-wiring region between the wiring patterns of the wiring layer, and an insulating film forming at least a part of a wall defining the cavity, and a memory cell region.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: February 18, 2014
    Inventor: Keizo Kawakita
  • Patent number: 8618607
    Abstract: One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: December 31, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, David Doman, Marc Tarabbia, Irene Lin, Jeff Kim, Chinh Nguyen, Steve Soss, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 8618632
    Abstract: There is provided a semiconductor device in which a wiring inductance of a DC/DC converter formed on a multi-layered wiring substrate can be reduced and the characteristics can be improved. In the semiconductor device, in an input-side capacitor, one capacitor electrode is electrically connected to a power-supply pattern between a control power MOSFET and a synchronous power MOSFET, and the other capacitor electrode is electrically connected to a ground pattern therebetween. The multi-layered wiring substrate includes: a via conductor arranged at a position of the one capacitor electrode for electrically connecting among a plurality of power-supply patterns in a thickness direction; and a via conductor arranged at a position of the other capacitor electrode for electrically connecting among a plurality of ground patterns in a thickness direction.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: December 31, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuya Kawashima, Takayuki Hashimoto
  • Patent number: 8604557
    Abstract: A semiconductor memory device includes: a first n-type transistor; a first p-type transistor; a first wiring layer having a first interconnecting portion for connecting a drain of the first n-type transistor and a drain of the first p-type transistor; and a second wiring layer having a first conductive portion electrically connected to the first interconnecting portion.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: December 10, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Narumi Ohkawa
  • Patent number: 8604594
    Abstract: A semiconductor chip includes a through-silicon via (TSV), a device region, and a cross-talk prevention ring encircling one of the device region and the TSV. The TSV is isolated from substantially all device regions comprising active devices by the cross-talk prevention ring.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: December 10, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chen-Cheng Kuo
  • Patent number: 8587095
    Abstract: A method for establishing and closing at least one trench of a semiconductor component, in particular a micromechanical or electrical semiconductor component, having the following steps: applying at least one metal layer over the trench to be formed; forming a lattice having lattice openings in the at least one metal layer over the trench to be formed; forming the trench below the metal lattice, and closing the lattice openings over the trench.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: November 19, 2013
    Assignee: Robert Bosch GmbH
    Inventors: Jochen Reinmuth, Eckhard Graf
  • Patent number: 8558380
    Abstract: A semiconductor package includes a first semiconductor chip having first bumps which are projectedly formed thereon; a first copper foil attachment resin covered on the first semiconductor chip to embed the first semiconductor chip, and formed such that a first copper foil layer attached on an upper surface of the first copper foil attachment resin is electrically connected with the first bumps; a second copper foil attachment resin including a second copper foil layer which is electrically connected with the first copper foil layer, and disposed on the first copper foil attachment resin; and a second semiconductor chip embedded in the second copper foil attachment resin in such a way as to face the first semiconductor chip, and having second bumps formed thereon which are electrically connected with the second copper foil layer.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: October 15, 2013
    Assignee: SK Hynix Inc.
    Inventors: Si Han Kim, Woong Sun Lee
  • Patent number: 8531012
    Abstract: A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: September 10, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: SinJae Lee, JinGwan Kim, JiHoon Oh, JaeHyun Lim, KyuWon Lee
  • Patent number: 8518277
    Abstract: A method of removing portions of a conductive layer comprising a transparent conductive material and/or a metallic material disposed on a plastic substrate used for capacitive touchscreen devices includes providing a plastic substrate having a conductive layer disposed on a surface thereof and removing portions of the conductive layer at the surface of the plastic substrate to establish a pattern of electrically isolated conductive portions on the surface of the plastic substrate. The conductive portions or traces are electrically connected to a touchscreen controller, which is operable to determine a location of a touch or proximity of an object at or near the surface of the plastic substrate responsive to a detected change in capacitance. The removal process may comprise etching or laser ablating portions of the conductive layer at the surface of the plastic substrate.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: August 27, 2013
    Assignee: TPK Touch Solutions Inc.
    Inventors: Yang Yun, Ryan T. Gerlach
  • Patent number: 8502342
    Abstract: Circuits, architectures, a system and methods for reducing the effect(s) of cross talk in neighboring I/O signal paths. The circuitry includes input/output (I/O) pads having I/O signal lines coupled thereto, and a capacitor having terminals coupled to the I/O pads and/or signal lines. The method includes transmitting or receiving a signal along a first I/O signal line in an integrated circuit, the first I/O signal line communicating with a first I/O pad on the integrated circuit, and the integrated circuit having a second I/O signal line communicating with a second I/O pad; and capacitively coupling the first signal to the second I/O pad and/or the second I/O signal line, to reduce the effect(s) of cross talk in the second I/O signal line. The present invention can significantly reduce the effects of cross talk in neighboring I/O signal paths, for both input and output signals.
    Type: Grant
    Filed: November 23, 2012
    Date of Patent: August 6, 2013
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventor: Liav Ben Artsi
  • Patent number: 8461668
    Abstract: A Power Management Integrated Circuit (PMIC) that includes a substrate, a high-side (HS) region on the substrate, a low-side (LS) region spaced from the first region, a device isolation layer interposed between the HS region and the LS region, a metal interconnection connected to the HS region across the device isolation layer and configured to permit a high-voltage current to flow in the HS region, and at least one electric field shield between the metal interconnection and the device isolation layer. Since the electric field shield is disposed under the metal interconnection, a sufficient breakdown voltage can be ensured for the HS region and the LS region.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: June 11, 2013
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Jong Min Kim, Jae Hyun Yoo
  • Patent number: 8441127
    Abstract: A device includes a package component, and a metal trace on a surface of the package component. A first and a second dielectric mask cover a top surface and sidewalls of the metal trace, wherein a landing portion of the metal trace is located between the first and the second dielectric masks. The landing portion includes a first portion having a first width, and a second portion connected to an end of the first portion. The second portion has a second width greater than the first width, wherein the first and the second widths are measured in a direction perpendicular to a lengthwise direction of the metal trace.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: May 14, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Tsai Hou, Liang-Chen Lin
  • Patent number: 8373249
    Abstract: The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus includes a semiconductor die having an upper surface, a first capacitor deployed above the upper surface of the semiconductor die, a separation layer deployed above the first capacitor, and a bond pad deployed above the separation layer such that at least a portion of the bond pad lies above the first capacitor.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: February 12, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Sion C. Quinlan, Bryan Almond, Ken S. Hunt, Andrew M. Lever, Joe A. Ward
  • Publication number: 20130032925
    Abstract: A semiconductor device comprises a first external terminal having a first size, a plurality of second external terminals each having a second size smaller than the first size, an external terminal area in which the first external terminal and the second external terminals are arranged, and a plurality of wires connecting between the second external terminals and a plurality of circuits formed adjacent to the external terminal area and corresponding to the second external terminals. The second external terminals and the wires constitute a plurality of interfaces. Each of the interfaces includes at least one adjustment portion that adjusts a time constant of the wire so that the wires have the same time constant. At least part of the adjustment portions is located in a margin area produced in the external terminal area by a difference between the first size and the second size.
    Type: Application
    Filed: July 20, 2012
    Publication date: February 7, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Tomohiro KITANO, Hisayuki NAGAMINE
  • Patent number: 8324711
    Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: December 4, 2012
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
  • Patent number: 8319342
    Abstract: A method for forming a semiconductor structure includes forming a sacrificial layer over a substrate. A first dielectric layer is formed over the sacrificial layer. A plurality of conductive structures are formed within the sacrificial layer and the first dielectric layer. The sacrificial layer is treated through the first dielectric layer, at least partially removing the sacrificial layer and forming at least one air gap between two of the conductive structures. A surface of the first dielectric layer is treated, forming a second dielectric layer over the first dielectric layer, after the formation of the air gap. A third dielectric layer is formed over the second dielectric layer. At least one opening is formed within the third dielectric layer such that the second dielectric layer substantially protects the first dielectric layer from damage by the step of forming the opening.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: November 27, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 8319313
    Abstract: Circuits, architectures, a system and methods for reducing the effect(s) of cross talk in neighboring I/O signal paths. The circuitry generally includes first and second input/output (I/O) pads having first and second I/O signal lines coupled thereto, and a capacitor having first and second terminals coupled to the first I/O pad and/or signal line and the second I/O pad and/or signal line, respectively. The method generally comprises the steps of (1) transmitting or receiving a signal along a first I/O signal line in an integrated circuit, the first I/O signal line communicating with a first I/O pad on the integrated circuit, and the integrated circuit having a second I/O signal line communicating with a second I/O pad; and (2) capacitively coupling the first signal to the second I/O pad and/or the second I/O signal line, sufficiently to reduce the effect(s) of cross talk in the second I/O signal line.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: November 27, 2012
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Liav Ben Artsi
  • Patent number: 8310056
    Abstract: In a semiconductor device, a lower multi-layered interconnect structure, an intermediate via-level insulating interlayer, and an upper multi-layered interconnect structure are stacked in this order in a region overlapped with a bonding pad in a plan view; upper interconnects and vias of the upper multi-layered interconnect structure are formed so as to be connected to the bonding pad in the pad placement region; the intermediate via-level insulating interlayer has no electro-conductive material layer, which connect the interconnects or vias in the upper multi-layered interconnect structure with interconnects or vias in the lower multi-layered interconnect structure, formed therein; and the ratio of area occupied by the vias in the via-level insulating interlayers contained in the lower multi-layered interconnect structure is smaller than the ratio of area occupied by the vias in the via-level insulating interlayers contained in the upper multi-layered interconnect structure.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Noriaki Oda, Shinichi Chikaki
  • Patent number: 8304321
    Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: November 6, 2012
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Motohiko Sato, Kazuhiro Hayashi, Kenji Murakami, Motonobu Kurahashi, Yusuke Kaieda, Jun Otsuka, Manabu Sato
  • Patent number: 8252659
    Abstract: The present disclosure is related to method for producing a semiconductor device comprising the steps of: providing a semiconductor substrate (1), comprising active components on the surface of said substrate, depositing a top layer (2) of dielectric material on the surface of said substrate or on other dielectric layers present on said surface, etching at least one first opening (7) at least through said top layer, filling said opening(s) at least with a first conductive material (8), and performing a first CMP step, to form said first conductive structures (3,26), etching at least one second opening (13) at least through said top layer, filling said opening(s) at least with a second conductive material (10), and performing a second CMP step, to form said second conductive structures (4,24), wherein the method comprises the step of depositing a common CMP stopping layer (5,25) on said dielectric top layer, before the steps of etching and filling said first opening(s), so that said same CMP stopping layer is
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: August 28, 2012
    Assignee: IMEC
    Inventors: Cedric Huyghebaert, Jan Vaes, Jan Van Olmen
  • Patent number: 8237282
    Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: August 7, 2012
    Assignees: Renesas Electronics Corporation, Renesas Device Design Corp.
    Inventors: Takashi Okuda, Yasuo Morimoto, Yuko Maruyama, Toshio Kumamoto
  • Patent number: 8227902
    Abstract: A semiconductor chip includes a through-silicon via (TSV), a device region, and a cross-talk prevention ring encircling one of the device region and the TSV. The TSV is isolated from substantially all device regions comprising active devices by the cross-talk prevention ring.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: July 24, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chen-Cheng Kuo
  • Patent number: 8193092
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: June 5, 2012
    Assignee: Micron Technology, Inc.
    Inventor: David S. Pratt
  • Patent number: 8178965
    Abstract: A module includes a semiconductor chip and a conductive layer arranged over the semiconductor chip. The module also includes a spacer structure arranged to deflect the conductive layer away from the semiconductor chip.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: May 15, 2012
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Grit Sommer
  • Patent number: 8143162
    Abstract: An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: March 27, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Yung-Cheng Lu, Hui-Lin Chang, Ting-Yu Shen, Hung Chun Tsai
  • Patent number: 8143697
    Abstract: Some embodiments of the invention include thin film capacitors formed in a package substrate of an integrated circuit package. At least one of the thin film capacitors includes a first electrode layer, a second electrode layer, and a dielectric layer between the first and second electrode layers. Each of the first and second electrode layers and the dielectric layer is formed individually and directly on the package substrate. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: March 27, 2012
    Assignee: Intel Corporation
    Inventors: Huankiat Seh, Yongki Min
  • Patent number: 8129766
    Abstract: A memory includes first contact plugs; ferroelectric capacitors above the first contact plugs; second contact plugs in a first interlayer film being below an area which is between two adjacent ferroelectric capacitors, the second contact plug; first interconnections connected to the second contact plugs, the first interconnections extending in a first direction substantially perpendicular to an arrangement direction, in which the two ferroelectric capacitors are arranged, on the first interlayer film; a second interlayer film above the first interlayer film and the first interconnection; third contact plugs in the second interlayer film, the third contact plugs being respectively connected to the first interconnections at positions shifted from the second contact plugs in the first direction; and second interconnections electrically connecting the third contact plug to the upper electrodes of the two ferroelectric capacitors.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: March 6, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Susumu Shuto
  • Patent number: 8115318
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: February 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
  • Patent number: 8089149
    Abstract: A semiconductor device has a package structure provided with leads that are external connection terminals. A base substance is an island, and at least the surface thereof is formed of a conductive material. A semiconductor substrate is mounted on the surface of the base substance, and a ground potential is supplied from the surface of the base substance. A shunt capacitor is provided with an electrode pair of a first electrode and a second electrode formed in parallel, and mounted with the first electrode being electrically connected to the surface of the base substance. An internal bonding wire connects a pad provided on the semiconductor substrate for external connection, to the second electrode of the shunt capacitor. The lead is the external connection terminal of the semiconductor device. An external bonding wire connects the lead to the second electrode of the shunt capacitor.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: January 3, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Noriaki Hiraga
  • Patent number: 8080876
    Abstract: A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: December 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Paul S. Andry, John U. Knickerbocker, Michelle L. Steen, Cornelia K. Tsang
  • Patent number: 8076730
    Abstract: System and method for transistor level routing is disclosed. A preferred embodiment comprises a semiconductor device including a first semiconductor device formed on a first active area in a substrate, the first semiconductor device having a first gate stack comprising a first high-k dielectric layer, a first metal layer and a first poly-silicon layer. The semiconductor device further includes a second semiconductor device formed on a second active area in the substrate, the second semiconductor device having a second gate stack comprising a second high-k dielectric layer, a second metal layer and a second poly-silicon layer. An electrical connection connects the first semiconductor device with the second semiconductor device and overlies the first active area, the second active area and a portion of the substrate between the first active area and the second active area.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: December 13, 2011
    Assignee: Infineon Technologies AG
    Inventors: Martin Ostermayr, Chandraserhar Sarma
  • Patent number: 8049303
    Abstract: A semiconductor chip and a semiconductor device mounting the semiconductor chip capable of increasing a capacitance of a capacitor without reducing the number of signal bumps or power bumps of a package and the number of C4 solder balls of the semiconductor chip, and achieving a stable power supply with suppressing fluctuations of power at a resonance frequency without a limitation in a position to mount a capacitor for lowering noise of a signal transceiving interface block. In the semiconductor device, a via hole is provided to the semiconductor chip, a power-supply electrode connected to the via hole is provided to a back surface of the semiconductor chip, and a capacitor is mounted to the electrode on the back surface. And, a high-resistance material is used for a material of a power-supply via hole inside the semiconductor chip, thereby increasing the resistance and lowering the Q factor.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: November 1, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Osaka, Tatsuya Saito
  • Patent number: 8039924
    Abstract: A semiconductor device includes a first wiring layer which is provided above a semiconductor substrate and includes a first insulating film and a wiring buried in the first insulating film, a second insulating film provided above the first wiring layer, a third insulating film provided on the second insulating film, and a capacitor element provided on the third insulating film. The wiring includes an upper surface having a protruding portion. The capacitor element includes a lower electrode provided on the third insulating film, a capacitor insulating film provided on the lower electrode, and an upper electrode provided on the capacitor insulating film.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: October 18, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masayuki Furumiya, Takeshi Toda
  • Patent number: 8030779
    Abstract: A multi-layered metal interconnection includes a diffusion barrier directly formed on a conductive layer, an etching stop layer directly formed on the diffusion barrier, at least one dielectric layer formed over the etch stop layer, at least one of a via formed in the at least one dielectric layer and a trench formed in the at least one dielectric layer.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: October 4, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Hyuk Park
  • Patent number: 8026111
    Abstract: A method for improving signal levels between capacitively-coupled chips in proximity communication (PxC) includes depositing a high permittivity dielectric material layer over a signal pad of a first chip, and placing a second chip in close proximity to the first chip such that faces of the signal pads align to enable for capacitive signal coupling. The high permittivity dielectric material layer that fills at least a portion of a gap between the first chip and the second chip, and improves capacitive coupling between signal pads of the first chip and the second chip by providing for an increased permittivity in the gap between the first chip and the second chip. The increased permittivity ensures that electric fields are substantially confined to a space between the signal pad of the first chip and the signal pad of the second chip.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: September 27, 2011
    Assignee: Oracle America, Inc.
    Inventors: Ashok Krishnamoorthy, John E. Cunningham
  • Patent number: 8021974
    Abstract: An improved semiconductor structure consists of interconnects in an upper interconnect level connected to interconnects in a lower interconnect level through use of a conductive protrusion located at the bottom of a via opening in an upper interconnect level, the conductive protrusion extends upward from bottom of the via opening and into the via opening. The improved interconnect structure with the conductive protrusion between the upper and lower interconnects enhances overall interconnect reliability.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: September 20, 2011
    Assignee: Internatioanl Business Machines Corporation
    Inventors: Chih-Chao Yang, David Vaclav Horak, Takeshi Nogami, Shom Ponoth
  • Patent number: 8022548
    Abstract: A method of forming one or more capacitors on or in a substrate and a capacitor structure resulting therefrom is disclosed. The method includes forming a trench in the substrate, lining the trench with a first copper-barrier layer, and substantially filling the trench with a first copper layer. The first copper layer is substantially chemically isolated from the substrate by the first copper-barrier layer. A second copper-barrier layer is formed over the first copper layer and a first dielectric layer is formed over the second copper-barrier layer. The dielectric layer is substantially chemically isolated from the first copper layer by the second copper-barrier layer. A third copper-barrier layer is formed over the dielectric layer and a second copper layer is formed over the third copper-barrier layer. The second copper layer is formed in a non-damascene process.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: September 20, 2011
    Assignee: Atmel Corporation
    Inventors: Isaiah O. Oladeji, Alan Cuthbertson