Abstract: A semiconductor integrated circuit having a multilayer wiring structure is provided which includes: a top metal wiring layer (MTOP) including a plurality of top layer power supply wirings and a next-to-top metal wiring layer (MTOP-1) directly below the top metal wiring layer MTOP including a plurality of next-to-top layer power supply wirings. Each of the top layer and the next-to-top layer power supply wirings also includes first potential wirings for supplying a first potential to the circuit elements and second potential wirings for supplying a second potential to the circuit elements. The top layer power supply wirings and the next-to-top layer power supply wirings cross each other and have a top layer insulating film disposed between them. First and second contacts are provided in the insulating film for connecting the first potential wirings and second potential wirings in the top and the next-to-top metal wiring layers with each other.

Abstract: A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC film 210 formed thereon, a SiO2 film 212 and a SiCN film 214 formed thereon. The first SiOC film 204 has a barrier metal layer 216 and via 218 formed therein, and the second SiOC film 210 has a barrier metal layer 220 and wiring metal layer 222 formed therein. Carbon content of the second SiOC film 210 is adjusted larger than that of the first SiOC film 204. This makes it possible to improve adhesiveness of the insulating interlayer with other insulating layers, while keeping a low dielectric constant of the insulating interlayer.

Abstract: The present invention is an apparatus and system for reducing bondpad capacitance of an integrated circuit. Circuitry of the present invention may produce a negative capacitance approximately equal in magnitude to the capacitance associated with the bondpad and thereby effectively eliminate the bondpad capacitance. Values of the components of the circuitry may be selectively and independently chosen to synthesize a variable range of negative capacitance and thus produce a negative capacitance approximately equal in magnitude to a unique capacitance associated with the bondpad of a variety of integrated circuits.

Abstract: Structures, in various embodiments, are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. In an embodiment, a transmission line is disposed on a first layer of insulating material, where the first layer of insulating has a thickness equal to or less than 1.0 micrometer. The transmission line may be structured with a thickness and a width of approximately 1.0 micrometers. A second layer of insulating material is disposed on the transmission line.

Abstract: A semiconductor chip package has a substrate that includes circuit lines provided on first and/or second surfaces, a power plane provided on the second surface, bump lands provided on the second surface and coupled to the circuit lines, and ball lands provided on the first surface. The package further has a semiconductor chip attached to the second surface of the substrate and electrically coupled to the circuit lines, and a dielectric layer provided on the second surface of the substrate. The dielectric layer surrounds laterally the chip, covers the power plane, and exposes the bump lands. The package further has a ground plane provided on both the chip and the dielectric layer, vertical connection bumps provided within the dielectric layer and on the bump lands and electrically coupled to the ground plane, and solder balls provided on the ball lands.

Abstract: A new method is provided for the creation of a high-reliability metal capacitor as part of back-end processing. A first layer of metal interconnect is created, ac contact point is provided in the surface of the first layer of interconnect aligned with which a capacitor is to be created. A copper interconnect is formed overlying the contact point using TaN for the bottom plate, a high dielectric-constant dielectric material capacitor and using TaN for the top plate. The deposited layers are patterned and etched, a spacer layer is formed over sidewalls of the capacitor to prevent capacitor sidewall leakage. Top interconnect metal is then formed by first depositing a layer of etch stop material for further interconnection of the capacitor and the semiconductor devices provided in the underlying substrate.

Abstract: A semiconductor device of the present invention includes a semiconductor substrate including an active region and an isolating region provided so as to enclose the active region; a capacitance insulating film that is provided on the active region and is in contact with the isolating region; an upper electrode provided on the capacitance insulating film so as to be spaced away from the isolating region; an electrode pad provided on the isolating region; a lead conductive film provided over a part of the capacitance insulating film and a part of the isolating region for connecting the upper electrode and the electrode pad; and an interlayer insulating film provided over the substrate.

Abstract: A process for forming an interlayer dielectric layer is disclosed. The method comprises first forming a carbon-doped oxide (CDO) layer with a first concentration of carbon dopants therein. Next, the CDO layer is further formed with a second concentration of carbon dopants therein, wherein the first concentration is different than the second concentration.

Abstract: A semiconductor device that reduces the parasitic capacitance between a conductive trace and a substrate, and a method of fabricating the same. The semiconductor device includes a substrate, an insulator layer disposed upon the substrate, a conductive trace disposed upon the insulator layer, and an element disposed between the substrate and the conductive trace. A first capacitance exists between the conductive trace and the substrate and a second capacitance results between the conductive trace and the substrate due to the presence of the element. The second capacitance is in series with the first capacitance, thereby reducing an effective capacitance between the conductive trace and the substrate.

Abstract: An improved back end of the line (BEOL) interconnect structure comprising an ultralow k (ULK) dielectric is provided. The structure may be of the single or dual damascene type and comprises a dense thin dielectric layer (TDL) between a metal barrier layer and the ULK dielectric. Disclosed are also methods of fabrication of BEOL interconnect structures, including (i) methods in which a dense TDL is provided on etched opening of a ULK dielectric and (ii) methods in which a ULK dielectric is placed in a process chamber on a cold chuck, a sealing agent is added to the process chamber, and an activation step is performed.

Abstract: A semiconductor device assembly includes a semiconductor device and a lead frame having lead fingers for connection to the semiconductor device. The lead frame may include floating NC lead fingers with inner portions of the floating NC lead fingers electrically isolated from the semiconductor device and the associated outer portion of the floating NC lead fingers. Floating NC lead fingers may separate lead fingers prone to causing induction noise from lead fingers subject to induction effects. The floating NC lead fingers may thus reduce the inductance noise of the lead fingers. The floating NC lead fingers may also allow the semiconductor device to be securely adhered to the lead fingers with no air pockets therebetween. A method of forming a semiconductor device assembly is also provided.