Via Connections In Multilevel Interconnection Structure (epo) Patents (Class 257/E23.145)
  • Patent number: 10777510
    Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
  • Patent number: 10731273
    Abstract: Various embodiments include methods and apparatuses comprising methods for formation of and apparatuses including a source material for electronic devices. One such apparatus includes a vertical string of memory cells comprising a plurality of alternating levels of conductor and dielectric material, a semiconductor material extending through the plurality of alternating levels of conductor material and dielectric material, and a source material coupled to the semiconductor material. The source material includes a titanium nitride layer and a source polysilicon layer in direct contact with the titanium nitride layer. Other methods and apparatuses are disclosed.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John Mark Meldrim, Yushi Hu, Yongjun Jeff Hu, Everett Allen McTeer
  • Patent number: 10418314
    Abstract: At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device. The substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, a second patterned conductive layer adjacent to the second surface of the first dielectric layer and electrically connected to the first patterned conductive layer, and an external connection pad tapered from a top surface to a bottom surface. The second patterned conductive layer includes a pad and a trace adjacent to the pad. The external connection pad is disposed on the pad of the second patterned conductive layer. A bottom width of the external connection pad is greater than or equal to a width of the pad of the second patterned conductive layer.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: September 17, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10344398
    Abstract: Various embodiments include methods and apparatuses comprising methods for formation of and apparatuses including a source material for electronic devices. One such apparatus includes a vertical string of memory cells comprising a plurality of alternating levels of conductor and dielectric material, a semiconductor material extending through the plurality of alternating levels of conductor material and dielectric material, and a source material coupled to the semiconductor material. The source material includes a titanium nitride layer and a source polysilicon layer in direct contact with the titanium nitride layer. Other methods and apparatuses are disclosed.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: John Mark Meldrim, Yushi Hu, Yongjun Jeff Hu, Everett Allen McTeer
  • Patent number: 9966336
    Abstract: A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tien-I Bao
  • Patent number: 9941323
    Abstract: A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: April 10, 2018
    Assignee: Sony Corporation
    Inventor: Atsushi Okuyama
  • Patent number: 9859160
    Abstract: A method of fabricating a semiconductor interconnect structure by providing a semiconductor structure that includes two dielectric layers. The first dielectric layer has an embedded electrically conductive structure. A second dielectric layer is located above the first dielectric layer. The second dielectric layer and the first dielectric layer have a segment of a dielectric capping layer and a segment of a metal capping layer located between them. The segment of the dielectric capping layer is horizontally planar with the segment of the metal capping layer. The segment of metal capping layer covers and abuts at least a portion of a top surface of the first electrically conductive structure. The method includes forming an opening in the second dielectric layer and the metal capping layer that exposes at least a portion of the first electrically conductive structure and a portion of the dielectric capping layer.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Conal E. Murray, Chih-Chao Yang
  • Patent number: 9741659
    Abstract: Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a substrate, the substrate having a first direction of coefficient of thermal expansion mismatch. The semiconductor device includes a first opening through the post-passivation layer, the first opening comprising a plurality of elongated apertures. A longest of the plurality of elongated apertures comprises a first dimension, wherein the first dimension is aligned substantially perpendicular to the first direction of coefficient of thermal expansion mismatch.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Shih-Wei Liang
  • Patent number: 9524935
    Abstract: A methodology enabling filling of high aspect ratio cavities, with no voids or gaps, in an IC device and the resulting device are disclosed. Embodiments include providing active area and/or gate contacts in a first ILD; forming selective protective caps on upper surfaces of the contacts; forming a second ILD on upper surfaces of the protective caps and on an upper surface of the first ILD; forming a hard-mask stack on the second ILD; forming, in the second ILD and hard-mask stack, cavities exposing one or more protective caps; removing selective layers in the stack to decrease depths of the cavities; and filling the cavities with a metal layer, wherein the metal layer in one or more cavities connects to an upper surface of the one or more exposed protective caps.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: December 20, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jonathan Lee Rullan, Sunil Kumar Singh
  • Patent number: 9040418
    Abstract: Method of forming a capture pad on a semiconductor substrate. The method includes providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled TSVs extending between the active side and the inactive side; filling the TSVs with a metal; defining capture pad areas on at least one of the active side and the inactive side adjacent to the TSVs, the defined capture pad areas comprising insulator islands and open areas; filling the open areas with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion that follows an outline of each of the TSVs.
    Type: Grant
    Filed: November 10, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, John A. Griesemer, Gary Lafontant, Kevin S. Petrarca, Richard P. Volant
  • Patent number: 9041208
    Abstract: A laminate interconnect structure includes a core material and at least one additional layer adjacent the core material, a first electrically conductive via formed in the core material, and a second electrically conductive via formed in the core material, coaxial with the first electrically conductive via and separated from the first electrically conductive via by a non-conductive material.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: May 26, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Adam Gallegos, Mark Hinton, Nurwati Suwendi Devnani, John Connor
  • Patent number: 9035457
    Abstract: A substrate with integrated passive devices and method of manufacturing the same are presented. The substrate may include through silicon vias, at least one redistribution layer having a 1st passive device pattern and stacked vias, and an under bump metal layer having a 2nd passive device pattern.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: May 19, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chu-Fu Lin, Ming-Tse Lin, Yung-Chang Lin
  • Patent number: 9030013
    Abstract: A structure includes a substrate, a low-k dielectric layer over the substrate, and a conductive barrier layer extending into the low-k dielectric layer. The conductive barrier layer includes a sidewall portion. A metal line in the low-k dielectric layer adjoins the conductive barrier layer. An organic buffer layer is between the sidewall portion of the conductive barrier layer and the low-k dielectric layer.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsien Peng, Hsin-Yen Huang, Hsiang-Huan Lee, Shau-Lin Shue
  • Patent number: 9018649
    Abstract: A nanopatterned surface is prepared by forming a block copolymer film on a miscut crystalline substrate, annealing the block copolymer film, then reconstructing the surface of the annealed block copolymer film The method creates a well-ordered array of voids in the block copolymer film that is maintained over a large area. The nanopatterned block copolymer films can be used in a variety of different applications, including the fabrication of high density data storage media.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: April 28, 2015
    Inventors: Thomas P. Russell, Soojin Park, Ting Xu
  • Patent number: 9006804
    Abstract: A method for fabricating a semiconductor device is provided herein and includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate, wherein a periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, wherein a bottom surface of the patterned mask layer is leveled with a top surface of the first interlayer dielectric. A second interlayer dielectric is then formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: April 14, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao, Shih-Fang Tzou
  • Patent number: 8994184
    Abstract: A semiconductor device has a substrate with a plurality of conductive vias and conductive layer formed over the substrate. A semiconductor die is mounted over a carrier. The substrate is mounted to the semiconductor die opposite the carrier. An encapsulant is deposited between the substrate and carrier around the semiconductor die. A plurality of conductive TMVs is formed through the substrate and encapsulant. The conductive TMVs protrude from the encapsulant to aid with alignment of the interconnect structure. The conductive TMVs are electrically connected to the conductive layer and conductive vias. The carrier is removed and an interconnect structure is formed over a surface of the encapsulant and semiconductor die opposite the substrate. The interconnect structure is electrically connected to the conductive TMVs. A plurality of semiconductor devices can be stacked and electrically connected through the substrate, conductive TMVs, and interconnect structure.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Reza A. Pagaila
  • Patent number: 8987907
    Abstract: A semiconductor device may include a semiconductor layer including at least one unit device, a first interconnection on the semiconductor layer and electrically connected to the at least one unit device, a diffusion barrier layer on the first interconnection, an intermetallic dielectric layer on the diffusion barrier layer, a plug in a first region of the intermetallic dielectric layer and passing through the diffusion barrier layer so that a bottom surface thereof contacts the first interconnection, and a first dummy plug in a second region of the intermetallic dielectric layer, passing through the diffusion barrier layer, and disposed apart from the first interconnection so that a bottom surface of the first dummy plug does not contact the first interconnection.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-sung Kang, Se-myeong Jang
  • Patent number: 8981501
    Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: March 17, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Meng-Jia Lin, Chang-Sheng Hsu, Kuo-Hsiung Huang, Wei-Hua Fang, Shou-Wei Hsieh, Te-Yuan Wu, Chia-Huei Lin
  • Patent number: 8975753
    Abstract: A three-dimensional interconnect includes a first substrate bonded to a second substrate, the first substrate including a device layer and a bulk semiconductor layer, a metal pad disposed on the second substrate, an electrically insulating layer disposed between the first and second substrates. The structure has a via-hole extending through the device layer, the bulk semiconductor layer and the electrically insulating layer to the metal pad on the second substrate. The structure has a dielectric coating on a sidewall of the via-hole, and a plasma-treated region of the metal pad disposed on the second substrate. The structure includes a via metal monolithically extending from the plasma-treated region of the metal pad through the via-hole and electrically interconnecting the device layer of the first substrate to the metal pad of the second substrate.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: March 10, 2015
    Assignee: Research Triangle Institute
    Inventors: Charles Kenneth Williams, Christopher A. Bower, Dean Michael Malta, Dorota Temple
  • Patent number: 8975751
    Abstract: A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, first and second conductive vias connected to first and second pads exposed at the front surface, pluralities of first and second conductive interconnects extending within respective ones of the openings, and first and second conductive contacts exposed for interconnection with an external element. The plurality of first conductive interconnects can be separated from the plurality of second conductive interconnects by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating material. The distribution of the openings can include at least m openings spaced apart in a first direction and n openings spaced apart in a second direction transverse to the first direction.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: March 10, 2015
    Assignee: Tessera, Inc.
    Inventors: Ilyas Mohammed, Belgacem Haba, Cyprian Uzoh, Piyush Savalia
  • Patent number: 8970040
    Abstract: A method for forming a contact structure includes forming a stack of alternating active layers and insulating layers. The stack includes first and second sub stacks each with active layers separated by insulating layers. The active layers of each sub stack include an upper boundary active layer. A sub stack insulating layer is formed between the first and second sub stacks with an etching time different from the etching times of the insulating layers for a given etching process. The upper boundary active layers are accessed, after which the remainder of the active layers are accessed to create a stairstep structure of landing areas on the active layers. Interlayer conductors are formed to extend to the landing areas, the interlayer conductors separated from one another by insulating material.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: March 3, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Shih-Hung Chen
  • Patent number: 8970010
    Abstract: Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 3, 2015
    Assignee: Cree, Inc.
    Inventors: Fabian Radulescu, Helmut Hagleitner, Terry Alcorn, William T. Pulz
  • Patent number: 8962479
    Abstract: A metal cap is formed on an exposed upper surface of a conductive structure that is embedded within an interconnect dielectric material. During the formation of the metal cap, metallic residues simultaneously form on an exposed upper surface of the interconnect dielectric material. A thermal nitridization process or plasma nitridation process is then performed which partially or completely converts the metallic residues into nitrided metallic residues. During the nitridization process, a surface region of the interconnect dielectric material and a surface region of the metal cap also become nitrided.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Stephan A. Cohen
  • Patent number: 8962473
    Abstract: In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Shiang Kuo, Ken-Yu Chang, Ya-Lien Lee, Hung-Wen Su
  • Patent number: 8952535
    Abstract: A semiconductor device including a first insulation film including a first opening reaching a diffusion region of a transistor; a first barrier metal over the diffused region in the first opening; a first conduction layer formed over the first barrier metal in the first opening and formed of a first conductor; a second barrier metal formed over the first conduction layer in the first opening; a second conduction layer formed over the second barrier metal in the first opening and formed of a second conductor; a third barrier metal formed over the first gate electrode in the second opening; a fourth barrier metal formed in the second opening and contacting with the third barrier metal; and a third conduction layer formed of the second conductor contacting with the fourth barrier metal in the second opening.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: February 10, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masaki Haneda, Akiyoshi Hatada
  • Patent number: 8952542
    Abstract: The present invention provides a semiconductor device, a semiconductor package and a semiconductor process. The semiconductor process includes the following steps: (a) providing a semiconductor wafer having a first surface, a second surface and a passivation layer; (b) applying a first laser on the passivation layer to remove a part of the passivation layer and expose a part of the semiconductor wafer; (c) applying a second laser, wherein the second laser passes through the exposed semiconductor wafer and focuses at an interior of the semiconductor wafer; and (d) applying a lateral force to the semiconductor wafer. Whereby, the cutting quality is ensured.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: February 10, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Pei Hsing Hua, Hui-Shan Chang
  • Patent number: 8952538
    Abstract: A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 10, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hirohisa Matsuki
  • Patent number: 8946906
    Abstract: To provide a multilayer wiring substrate in which the connection reliability of via conductors is enhanced, via holes are formed in a resin interlayer insulation layer which isolates a lower conductor layer from an upper conductor layer, and via conductors are formed in the via holes for connecting the lower conductor layer and the upper conductor layer. The surface of the resin interlayer insulation layer is a rough surface, and the via holes open at the rough surface of the resin interlayer insulation layer. Stepped portions are formed in opening verge regions around the via holes such that the stepped portions are recessed from peripheral regions around the opening verge regions. The stepped portions are higher in surface roughness than the peripheral regions.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: February 3, 2015
    Assignee: NGK Spark Plug Co., Ltd.
    Inventor: Shinnosuke Maeda
  • Patent number: 8912076
    Abstract: An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: December 16, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey Alan West, Thomas D. Bonifield, Basab Chatterjee
  • Patent number: 8912658
    Abstract: An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ronald Filippi, Ping-Chuan Wang, Griselda Bonilla, Kaushik Chanda, Robert D. Edwards, Andrew H. Simon
  • Patent number: 8907458
    Abstract: Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shom Ponoth, David V. Horak, Takeshi Nogami, Chih-Chao Yang
  • Patent number: 8901741
    Abstract: A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
    Type: Grant
    Filed: June 23, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matthew E. Colburn, Satya V. Nitta, Sampath Purushothaman, Charles Black, Kathryn Guarini
  • Patent number: 8901725
    Abstract: A wiring board has a structure where multiple wiring layers are stacked one on top of another with insulating layers interposed therebetween. A sheet-shaped member is buried in an outermost insulating layer located on a side of the structure opposite to a side on which a semiconductor element is to be mounted. The sheet-shaped member has a modulus of elasticity and a coefficient of thermal expansion which are similar to a modulus of elasticity and a coefficient of thermal expansion of the semiconductor element. The sheet-shaped member is made of a material having a modulus of elasticity and a coefficient of thermal expansion which are enough to bring respective distributions thereof into a substantially symmetric form in a direction orthogonal to a surface of the wiring board in the case where the semiconductor element is mounted.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: December 2, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Akihiko Tateiwa, Masahiro Kyozuka, Fumimasa Katagiri
  • Patent number: 8896124
    Abstract: A circuit device is configured with robust circuit connectors. In connection with various example embodiments, an integrated circuit device includes one or more via network layers below a bond pad contact, connecting the bond pad contact with one or more underlying metal layers. Each via network layer includes a plurality of via strips extending about parallel to the bond pad contact and in different directions to structurally support the bond pad contact.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: November 25, 2014
    Assignee: NXP B.V.
    Inventors: Yuan Li, Som Nath, Maarten Jeroen Van Dort
  • Patent number: 8896123
    Abstract: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: November 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehun Jeong, Hansoo Kim, Jaehoon Jang, Hoosung Cho, Kyoung-Hoon Kim
  • Patent number: 8890304
    Abstract: A microelectronic package includes a microelectronic unit and a substrate. The microelectronic unit includes a microelectronic element having contacts on a front face. A dielectric material has a first surface substantially flush with the front face of the microelectronic element. Conductive traces have at least portions extending along the front face away from the contacts, at least some of which also extend along the first surface of the dielectric material. Contacts are connected with the traces, at least some of which are disposed at the first surface of the dielectric material. The substrate has first and second opposed surfaces and an edge extending therebetween, the first surface facing the front face of the microelectronic unit, and the second surface having a plurality of terminals thereon configured for electrical connection with at least one external component. Masses of conductive matrix material join the terminals with the redistribution contacts.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: November 18, 2014
    Assignee: Tessera, Inc.
    Inventors: Hiroaki Sato, Kiyoaki Hashimoto, Yoshikuni Nakadaira, Norihito Masuda, Belgacem Haba, Ilyas Mohammed, Philip Damberg
  • Patent number: 8884444
    Abstract: According to the nonvolatile memory device in one embodiment, contact plugs connect between second wires and third wires in a memory layer and a first wire connected to a control element. Drawn wire portions connect the second wires and the third wires with the contact plug. The drawn wire portion connected to the second wires and the third wires of the memory layer is formed of a wire with a critical dimension same as the second wires and the third wires and is in contact with the contact plug on an upper surface and both side surfaces of the drawn wire portion.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: November 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Nitta
  • Patent number: 8878203
    Abstract: A switching circuit comprises a first transistor and a second transistor formed in an active area of semiconductor substrate. The source and drain regions of the transistors are electrically connected to respective source wires and drain wires through a plurality of intermediate metal layers stacked above the transistor. Electrical connections between different layers are made with a plurality of vias. To improve switching performance, the intermediate wires are disposed such that intermediate wires electrically connected to the transistor source regions are not directly beneath the drain wires. Similarly, intermediate wires electrically connected to drain regions are arranged not to be directly underneath source wires.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takayuki Teraguchi
  • Patent number: 8872349
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: October 28, 2014
    Assignee: Intel Corporation
    Inventors: Chia-Pin Chiu, Zhiguo Qian, Mathew J. Manusharow
  • Patent number: 8871639
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece including an insulating material layer disposed thereon. The insulating material layer includes a trench formed therein. The method includes forming a barrier layer on the sidewalls of the trench using a surface modification process and a surface treatment process.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Hsueh Chang Chien, Yu-Ming Lee, Man-Kit Leung, Chi-Ming Yang
  • Patent number: 8872353
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 28, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8872347
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: October 28, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8872352
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 28, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8872303
    Abstract: A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wu-Te Weng, Ji-Shyang Nieh
  • Patent number: 8860223
    Abstract: A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. The metallization may form row lines in the array.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: October 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Cristina Casellato, Carmela Cupeta, Michele Magistretti, Fabio Pellizzer, Roberto Somaschini
  • Patent number: 8860222
    Abstract: Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: October 14, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Viren Khandekar, Karthik Thambidurai, Ahmad Ashrafzadeh, Amit Kelkar, Hien D. Nguyen
  • Patent number: 8859416
    Abstract: A computer-readable software product is provided for executing a method of determining the location of a plurality of power rail vias in a semiconductor device. The semiconductor device includes an active region and a power rail. Locations of a first via and a second via are assigned along the power rail. The spacing between the location of the first via and the location of the second via is a minimum spacing allowable. The spacing between the location of the second via and the locations of structures in the active region which may electrically interfere with the second via is determined. The location of the second via is changed in response to the spacing between the location of the second via and the location of one of the structures in the active region being less than a predetermined distance.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: October 14, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: David S. Doman, Mahbub Rashed, Marc Tarrabia
  • Patent number: 8860221
    Abstract: Provided are electrode-connecting structures or semiconductor devices, including a lower device including a lower substrate, a lower insulating layer formed on the lower substrate, and a lower electrode structure formed in the lower insulating layer, wherein the lower electrode structure includes a lower electrode barrier layer and a lower metal electrode formed on the lower electrode barrier layer, and an upper device including an upper substrate, an upper insulating layer formed under the upper substrate, and an upper electrode structure formed in the upper insulating layer, wherein the upper electrode structure includes an upper electrode barrier layer extending from the inside of the upper insulating layer under a bottom surface thereof and an upper metal electrode formed on the upper electrode barrier layer. The lower metal electrode is in direct contact with the upper metal electrode.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: October 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kun-Sang Park, Byung-Lyul Park, Su-Kyoung Kim, Kwang-Jin Moon, Suk-Chul Bang, Do-Sun Lee, Dong-Chan Lim, Gil-Heyun Choi
  • Patent number: 8853861
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 7, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8847403
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: September 30, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe