Via Connections In Multilevel Interconnection Structure (epo) Patents (Class 257/E23.145)
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Patent number: 8742591Abstract: A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.Type: GrantFiled: December 21, 2011Date of Patent: June 3, 2014Assignee: STATS ChipPAC, Ltd.Inventors: Won Kyoung Choi, Chang Bum Yong, Jae Hun Ku
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Patent number: 8736064Abstract: An interconnect element is provided. A monolithic dielectric element has a first exposed major surface, a plurality of first recesses extending inwardly from the first major surface, and a second exposed major surface remote from the first major surface, a plurality of second recesses extending inwardly from the second major surface. A plurality of first metal interconnect patterns are embedded in the plurality of first recesses and extend in one or more directions along the first major surface. A plurality of second metal interconnect patterns are embedded in the plurality of second recesses and extend in one or more directions along the second major surface. A plurality of non-hollow metal posts extend through the dielectric element between at least some of the plurality of first metal interconnect patterns and at least some of the plurality of second metal interconnect patterns.Type: GrantFiled: November 8, 2010Date of Patent: May 27, 2014Assignee: Invensas CorporationInventors: Hideki Kotake, Kiyoshi Hyodo, Inetaro Kurosawa, Yukio Hashimoto, Toku Yoshino, Tomoo Iijima
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Patent number: 8736033Abstract: An embedded-electronic-device package includes a core layer, an electronic device, a first dielectric layer, a second dielectric layer, a shielding-metal layer and conductive vias. The core layer includes a first surface, a second surface opposite to the second surface and a cavity penetrating the core layer. The electronic device is disposed in the cavity including an inner surface. The first dielectric layer disposed on the first surface is filled in part of the cavity and covers part of the electronic device. The second dielectric layer disposed on the second surface is filled in rest of the cavity, covers rest of the electronic device. The first and second dielectric layers cover the electronic device. The shielding-metal layer covers the inner surface. The conductive vias are respectively disposed in the first and second dielectric layers and extended respectively from outer surfaces of the first and second dielectric layers to the shielding-metal layer.Type: GrantFiled: March 13, 2013Date of Patent: May 27, 2014Assignee: Unimicron Technology Corp.Inventors: Yu-Chen Chuo, Wei-Ming Cheng
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Patent number: 8736070Abstract: A semiconductor component having improved thermomechanical durability has in a semiconductor substrate at least one cell comprising a first main electrode zone, a second main electrode zone and a control electrode zone lying in between. For making contact with the main electrode zone, at least one metallization layer composed of copper or a copper alloy is provided which is connected to at least one bonding electrode which likewise comprises copper or a copper alloy.Type: GrantFiled: October 15, 2013Date of Patent: May 27, 2014Assignee: Infineon Technologies Austria AGInventor: Matthias Stecher
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Patent number: 8735280Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A conductive layer is deposited on the substrate. A patterned hard mask is formed on the conductive layer and then a patterned photoresist is formed on the patterned hard mask and the conductive layer. A local metal catalyst layer is formed on the conductive layer in the openings of the patterned photoresist. Carbon nanotubes (CNTs) are grown from the local metal catalyst layer. The conductive layer is etched by using the CNTs and the patterned hard mask as etching mask to form metal features. An inter-level dielectric (ILD) layer is deposited between metal features.Type: GrantFiled: December 21, 2012Date of Patent: May 27, 2014Inventors: Ching-Fu Yeh, Hsiang-Huan Lee, Chao-Hsien Peng, Hsien-Chang Wu
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Patent number: 8729711Abstract: A semiconductor device includes a semiconductor substrate having a first surface being an element formation surface, and a second surface opposite to the first surface; a through-hole formed to penetrate the semiconductor substrate from the first surface to the second surface; an insulating film formed on an inner wall of the through-hole; a barrier film formed on the inner wall of the through-hole with the insulating film interposed therebetween; and a conductive portion formed to fill the through-hole provided with the insulating film and the barrier film. A gettering site is formed in a portion of the semiconductor substrate around the through-hole at least near a side of the first surface.Type: GrantFiled: July 30, 2012Date of Patent: May 20, 2014Assignee: Panasonic CorporationInventor: Taichi Nishio
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Patent number: 8729703Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.Type: GrantFiled: May 9, 2013Date of Patent: May 20, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
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Patent number: 8723328Abstract: To provide a multilayer wiring substrate in which the connection reliability of via conductors is enhanced, via holes are formed in a resin interlayer insulation layer which isolates a lower conductor layer from an upper conductor layer, and via conductors are formed in the via holes for connecting the lower conductor layer and the upper conductor layer. The surface of the resin interlayer insulation layer is a rough surface, and the via holes open at the rough surface of the resin interlayer insulation layer. Stepped portions are formed in opening verge regions around the via holes such that the stepped portions are recessed from peripheral regions around the opening verge regions. The stepped portions are higher in surface roughness than the peripheral regions.Type: GrantFiled: December 13, 2011Date of Patent: May 13, 2014Assignee: NGK Spark Plug Co., Ltd.Inventor: Shinnosuke Maeda
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Patent number: 8716065Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; forming a base encapsulation, having a base encapsulation top side, on the base substrate and around the base integrated circuit; forming a base conductive via, having a base via head, through the base encapsulation and attached to the base substrate adjacent to the base integrated circuit, the base via head exposed from and coplanar with the base encapsulation top side; mounting an interposer structure over the base encapsulation with the interposer structure connected to the base via head; and forming an upper encapsulation on the base encapsulation top side and partially surrounding the interposer structure with a side of the interposer structure facing away from the base encapsulation exposed.Type: GrantFiled: September 23, 2011Date of Patent: May 6, 2014Assignee: Stats Chippac Ltd.Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
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Patent number: 8716867Abstract: A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate.Type: GrantFiled: May 12, 2010Date of Patent: May 6, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Francis Ko, Chi-Chun Hsieh, Shang-Yun Hou, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
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Patent number: 8716857Abstract: A semiconductor fabrication technique cuts loops formed in a spacer pattern. The spacer pattern is a split loop pattern which generally includes a symmetric arrangement of one or more loops in each of four quadrants which are defines with respect to a reference point. The loops can be peaks or trenches. Each quadrant can include one loop, or multiple nested loops. Further, the space pattern includes a single cross, or multiple nested crosses, which extend between the loops. A cut out area is defined which extends outward from the reference point to closed ends of the loops, also encompassing a central portion of the cross. When a metal wiring layer pattern is formed using the spacer pattern with the cut out area, metal wiring is excluded from the cut out area. The loop ends in the metal wiring layer are broken and can be used as independent active lines.Type: GrantFiled: November 27, 2013Date of Patent: May 6, 2014Assignee: SanDisk Technologies Inc.Inventors: Kiyonori Ogisu, Yosuke Takahata
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Publication number: 20140117556Abstract: A through silicon via (TSV) stacked structure made of stacked substrates. Each substrate includes multiple tapered through silicon vias, wherein the wider end of each tapered through silicon via is provided with a recessed portion and the narrower end of each tapered through silicon via protrudes from the substrate. The substrates are stacked one after another with the narrower end of each tapered through silicon via being fitting and jointing into a corresponding recessed portion of the tapered through silicon via.Type: ApplicationFiled: October 25, 2012Publication date: May 1, 2014Inventor: Po-Chun Lin
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Patent number: 8710672Abstract: A semiconductor device of an embodiment includes: a substrate; a first catalytic metal film on the substrate; graphene on the first catalytic metal film; an interlayer insulating film on the graphene; a contact hole penetrating through the interlayer insulating film; a conductive film at the bottom portion of the contact hole, the conductive film being electrically connected to the graphene; a second catalytic metal film on the conductive film, the second catalytic metal film being subjected to plasma processing with at least one kind of gas selected from hydrogen, nitrogen, ammonia, and rare gas; and carbon nanotubes on the second catalytic metal film.Type: GrantFiled: July 5, 2012Date of Patent: April 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Katagiri, Yuichi Yamazaki, Makoto Wada, Tadashi Sakai, Naoshi Sakuma, Mariko Suzuki
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Patent number: 8709945Abstract: Using printing technologies to fill conductor materials into holes in silicon substrate, the preferred embodiments of the present improve cost efficiency of through-hole connections. Using silicon substrate as cathode terminal during electrical plating that fill holes in a silicon substrate with conductors, the preferred embodiments of the present improve alignment accuracy and cost efficiency of through-hole manufacturing processes.Type: GrantFiled: March 6, 2012Date of Patent: April 29, 2014Inventor: Jeng-Jye Shau
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Patent number: 8703507Abstract: A semiconductor device comprising a first insulating layer, a first metal conductor layer formed over the first insulating layer, a second insulating layer comprising a low-k insulating material formed over the first metal conductor, a second metal conductor layer formed over the second insulating layer, vias formed in the second insulating layer connecting the first metal conductor layer to the second metal conductor layer, and a plurality of metal lines. One of the metal lines is expanded around one of the vias compared to metal lines around other ones of the vias so that predetermined areas around each of the vias meets a minimum metal density.Type: GrantFiled: September 28, 2012Date of Patent: April 22, 2014Assignee: Freescale Semiconductor, Inc.Inventor: Douglas M. Reber
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Patent number: 8704377Abstract: An electrical interconnect providing an interconnect between contacts on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a resilient substrate with a plurality of through holes extending from a first surface to a second surface. A resilient material is located in the through holes. The resilient material includes an opening extending from the first surface to the second surface. A plurality of discrete, free-flowing conductive nano-particles are located in the openings of the resilient material. The conductive particles are substantially free of non-conductive materials. A plurality of first contact members are located in the through holes adjacent the first surface and a plurality of second contact members are located in the through holes adjacent the second surface. The first and second contact members are electrically coupled to the nano-particles.Type: GrantFiled: August 19, 2013Date of Patent: April 22, 2014Assignee: HSIO Technologies, LLCInventor: James Rathburn
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Patent number: 8704353Abstract: A method of manufacturing is provided that includes fabricating a first plurality of electrically functional interconnects on a front side of a first semiconductor chip and fabricating a first plurality of electrically non-functional interconnects on a back side of the first semiconductor chip. Additional chips may be stacked on the first semiconductor chip.Type: GrantFiled: March 30, 2012Date of Patent: April 22, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Michael Su, Bryan Black, Neil McLellan, Joe Siegel, Michael Alfano
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Patent number: 8698206Abstract: Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer.Type: GrantFiled: April 28, 2011Date of Patent: April 15, 2014Assignee: Infineon Technologies AGInventors: Thomas Schulz, Sergei Postnikov
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Patent number: 8692385Abstract: Device for connecting nano-objects to external electrical systems, and method for producing the device. According to the invention, which applies in particular to molecular characterization, a device including the following is produced: an upper layer equipped with upper contact pads to be connected to a nano-object; a lower layer, equipped with lower contact pads to be connected to an external electrical system; above the lower layer, a bonding layer including electrical through-vias in contact with the lower pads; and, between the bonding layer and the upper layer, at least two layers equipped with conductive lines and electrical vias, for connecting the upper pads to the lower pads.Type: GrantFiled: December 5, 2011Date of Patent: April 8, 2014Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Aurélie Thuaire, Xavier Baillin, Nicolas Sillon
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Patent number: 8692364Abstract: A semiconductor device includes an embedding layer in which one or more semiconductor element(s) is embedded and one or more interconnect layers as well as one or more insulation layers on one or both sides of the embedding layer. The embedding layer includes a woven cloth formed by reinforcement fibers. The woven cloth has an opening on its site embedding the semiconductor element. The opening is arranged so that direction of the reinforcement fibers will have a preset angle with respect to a direction of a side of or a tangent to at least a portion of the opening, the preset angle being other than a square angle or a zero angle (parallelism).Type: GrantFiled: August 6, 2010Date of Patent: April 8, 2014Assignee: NEC CorporationInventors: Katsumi Kikuchi, Yoshiki Nakashima, Kentaro Mori, Shintaro Yamamichi
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Publication number: 20140091474Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
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Publication number: 20140091438Abstract: A semiconductor device including a conductive element and an interface surface fabricated atop the conductive element, and a method for fabricating such a device are described. An exemplary device includes a substrate having a conductive element and a metal layer fabricated atop the conductive element. An oxide layer is fabricated atop the metal layer, thus forming an interface surface. During polishing (e.g., planarization), in which an upper portion of the interface surface is removed, the presence of the interface surface greatly reduces the loading on the conductive element. A second substrate fabricated using the same process may be stacked atop the first substrate and bonded using a hybrid bonding process.Type: ApplicationFiled: October 12, 2012Publication date: April 3, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
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Publication number: 20140091476Abstract: A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Paul A. Nyhus, Swaninathan Sivakumar
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Patent number: 8685793Abstract: An assembly and method of making same are provided. The assembly can be formed by juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element. An opening can be formed extending through the conductive pad of the second semiconductor element and exposing a surface of the first conductive element. The opening may alternatively be formed extending through the first conductive element. A second electrically conductive element can be formed extending at least within the opening and electrically contacting the conductive pad and the first conductive element. A third semiconductor element can be positioned in a similar manner with respect to the second semiconductor element.Type: GrantFiled: September 16, 2010Date of Patent: April 1, 2014Assignee: Tessera, Inc.Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Piyush Savalia
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Publication number: 20140077383Abstract: A structure and method of making an offset-trench crackstop, which forms an air gap in a passivation layer that is adjacent to a passivated top metal layer of a metal crackstop in an integrated circuit (IC) die. The offset-trench crackstop may expose a portion of a topmost dielectric layer in the crackstop region, not expose a topmost patterned metal layer of the metal crackstop, and may be interposed between the metal crackstop and an active device region. Alternatively, the offset-trench crackstop may expose a portion of the topmost dielectric layer, which separates an outermost metal layer and an innermost metal layer of the metal crackstop, and does not expose any of the topmost patterned metal layer of the metal crackstop, where the innermost metal layer of the metal crackstop is interposed between the offset-trench crackstop in the crackstop region and the active device region of the IC die.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter
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Publication number: 20140077384Abstract: An approach for providing bit cells with triple patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process of a metal layer, a first structure that is a first one of a word line structure, a ground line structure, a power line structure, and a bit line structure; providing, via a second patterning process of the metal layer, a second structure that is different from the first structure and that is a second one of the word line structure, the ground line structure, the power line structure, and the bit line structure; and providing, via a third patterning process of the metal layer, a third structure that is different from the first structure and the second structure, and that is a third one of the word line structure, the ground line structure line, the power line structure, and the bit line structure.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Inventors: Juhan Kim, Jongwook Kye
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Patent number: 8669182Abstract: An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided.Type: GrantFiled: February 16, 2012Date of Patent: March 11, 2014Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Daniel C. Edelstein
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Publication number: 20140061924Abstract: An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a first metal line and a dielectric layer formed over the first metallization layer, wherein the dielectric layer comprises a metal structure having a bottom surface coplanr with a top surface of the first metal line.Type: ApplicationFiled: August 31, 2012Publication date: March 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yu Chen, Ku-Feng Yang, Tasi-Jung Wu, Lin-Chih Huang, Yuan-Hung Liu, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 8664113Abstract: A multilayer interconnect structure is formed by, providing a substrate having thereon a first dielectric for supporting a multi-layer interconnection having lower conductor MN, upper conductor MN+1, dielectric interlayer (DIL) and interconnecting via conductor VN+1/N. The lower conductor MN has a first upper surface located in a recess below a second upper surface of the first dielectric. The DIL is formed above the first and second surfaces. A cavity is etched through the DIL from a desired location of the upper conductor MN+1, exposing the first surface. The cavity is filled with a further electrical conductor to form the upper conductor MN+1 and the connecting via conductor VN+1/N making electrical contact with the first upper surface. A critical dimension between others of lower conductors MN and the via conductor VN+1/N is lengthened. Leakage current and electro-migration there-between are reduced.Type: GrantFiled: April 28, 2011Date of Patent: March 4, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventor: Ryoung-Han Kim
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Patent number: 8664766Abstract: An interconnect structure including a gouging feature at the bottom of one of the via openings. The structure includes an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein. The conductively filled via is in contact with an exposed surface of the at least one conductive feature of a first interconnect level by an anchoring area. The conductively filled via is separated from the second dielectric material by a first diffusion barrier layer, and the conductively filled line is separated from the second dielectric material by a second continuous diffusion barrier layer thereby the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line.Type: GrantFiled: April 27, 2009Date of Patent: March 4, 2014Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Terry A. Spooner, Oscar van der Straten
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Patent number: 8664761Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a plurality of stacked structures and a plurality of contact structures. Each of the stacked structures includes a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. Each of the contact structures is electrically connected to each of the stacked structures. The contact structure includes a first conductive pillar, a dielectric material layer, a metal silicide layer, and a second conductive pillar. The dielectric material layer surrounds the lateral surface of the first conductive pillar. The metal silicide layer is formed on an upper surface of the first conductive pillar. The second conductive pillar is formed on the metal silicide layer. The upper surfaces of the first conductive pillars are coplanar.Type: GrantFiled: December 21, 2012Date of Patent: March 4, 2014Assignee: Macronix International Co., Ltd.Inventors: Chih-Wei Hu, Teng-Hao Yeh
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Patent number: 8659159Abstract: According to one embodiment, an integrated circuit device includes a plurality of interconnects and a contact via. The plurality of interconnects are arranged parallel to each other. The contact via is connected to the each of the interconnects. A protrusion is formed at a portion of each of the interconnects connected to the contact via to protrude in a direction of the arrangement. A recess is formed at a portion of the each of the interconnects separated from the portion having the protrusion to recede in the direction. The protrusion formed on one interconnect of two mutually-adjacent interconnects among the plurality of interconnects is opposed to the recess formed in one other interconnect of the two mutually-adjacent interconnects. The portion having the recess is separated from portions on two sides thereof and is separated also from the portion having the protrusion.Type: GrantFiled: September 20, 2011Date of Patent: February 25, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Gaku Sudo
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Patent number: 8653648Abstract: A system and method for forming a TSV contact is presented. A preferred embodiment includes a TSV in contact with a portion of the uppermost metal layer of a semiconductor die. The interface between the TSV conductor and the contact pad is preferably characterized by a non-planar zigzag pattern that forms a grid pattern of contacts. Alternatively, the contacts may form a plurality of metal lines that make contact with the contact pad.Type: GrantFiled: October 3, 2008Date of Patent: February 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hua Chen, Chen-Shien Chen, Chen-Cheng Kuo, Wen-Wei Shen
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Patent number: 8648471Abstract: A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines in different cell array layers.Type: GrantFiled: April 24, 2012Date of Patent: February 11, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hideyuki Tabata, Eiji Ito, Hirofumi Inoue
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Patent number: 8648472Abstract: In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper portions of the first metal interconnect and the second metal interconnect are recessed to form recesses. A second insulating film filling the recesses is then formed above a substrate, and the upper portion of the second insulating film is planarized. Next, a hole and a trench are formed to extend halfway through the second insulating film, and ashing and polymer removal are performed. Subsequently to this, the hole and the trench are allowed to reach the first metal interconnect and the second metal interconnect.Type: GrantFiled: November 12, 2012Date of Patent: February 11, 2014Assignee: Panasonic CorporationInventor: Shusuke Isono
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Patent number: 8643083Abstract: Devices and systems for insulating integrated circuits from ultraviolet (“UV”) light are described. The device includes a conductive feature, a first and second UV blocking layer, a first and second insulating laver, and a conductive structure. The first insulating layer overlays the first UV blocking layer. A via opening extends through the first insulating layer and the first UV blocking layer. The second UV blocking layer overlays the first insulating laver. The second insulating layer overlays the second UV blocking layer. An interconnect trench is defined in the second insulating layer and second UV blocking layer. The conductive structure is electrically connected to the conductive feature and extends into the via opening and along the interconnect trench.Type: GrantFiled: May 7, 2012Date of Patent: February 4, 2014Assignee: Spansion LLCInventors: Bryon K. Hance, Brian D. White, William Brennan, Joseph W. Wiseman, Allen Evans
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Patent number: 8642467Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.Type: GrantFiled: January 11, 2012Date of Patent: February 4, 2014Assignee: Renesas Electronics CorporationInventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
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Patent number: 8643183Abstract: An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment. Concurrently or alternatively, interconnects are coated with barrier material in a simple and uncomplicated manner by means of the long-term heat treatment.Type: GrantFiled: October 30, 2006Date of Patent: February 4, 2014Assignee: Infineon Technologies AGInventors: Oliver Aubel, Wolfgang Hasse, Martina Hommel, Heinrich Koerner
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Publication number: 20140029181Abstract: Embodiments of the present disclosure are directed towards interlayer interconnects and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, one or more device layers disposed on the semiconductor substrate, and one or more interconnect layers disposed on the one or more device layers, the one or more interconnect layers including interconnect structures configured to route electrical signals to or from the one or more device layers, the interconnect structures comprising copper (Cu) and germanium (Ge). Other embodiments may be described and/or claimed.Type: ApplicationFiled: July 27, 2012Publication date: January 30, 2014Inventors: Florian Gstrein, Hui Jae Yoo, Jacob M. Faber, James S. Clarke
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Patent number: 8637982Abstract: A semiconductor fabrication technique cuts loops formed in a spacer pattern. The spacer pattern is a split loop pattern which generally includes a symmetric arrangement of one or more loops in each of four quadrants which are defines with respect to a reference point. The loops can be peaks or trenches. Each quadrant can include one loop, or multiple nested loops. Further, the space pattern includes a single cross, or multiple nested crosses, which extend between the loops. A cut out area is defined which extends outward from the reference point to closed ends of the loops, also encompassing a central portion of the cross. When a metal wiring layer pattern is formed using the spacer pattern with the cut out area, metal wiring is excluded from the cut out area. The loop ends in the metal wiring layer are broken and can be used as independent active lines.Type: GrantFiled: April 18, 2012Date of Patent: January 28, 2014Assignee: SanDisk Technologies Inc.Inventors: Kiyonori Ogisu, Yosuke Takahata
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Patent number: 8633594Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.Type: GrantFiled: July 13, 2012Date of Patent: January 21, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Kenichi Watanabe
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Patent number: 8633589Abstract: A portion of a conductive layer (310, 910) provides a capacitor electrode (310.0, 910.0). Dielectric trenches (410, 414, 510) are formed in the conductive layer to insulate the capacitor electrode from those portions of the conductive layer which are used for conductive paths passing through the electrode but insulated from the electrode. Capacitor dielectric (320) can be formed by anodizing tantalum while a nickel layer (314) protects an underlying copper (310) from the anodizing solution. This protection allows the tantalum layer to be made thin to obtain large capacitance. Chemical mechanical polishing of a layer (610) is made faster, and hence possibly less expensive, by first patterning the layer photolithographically to form, and/or increase in height, upward protrusions of this layer.Type: GrantFiled: October 2, 2007Date of Patent: January 21, 2014Assignee: Invensas CorporationInventors: Sergey Savastiouk, Valentin Kosenko, James J. Roman
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Patent number: 8633595Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.Type: GrantFiled: July 13, 2012Date of Patent: January 21, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Kenichi Watanabe
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Patent number: 8633520Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate; device isolation regions formed in the substrate; an impurity region formed in a region of the substrate between every two adjacent ones of the device isolation regions; a gate electrode formed on the substrate; first and second interlayer insulating films sequentially formed on the substrate; a metal interlayer insulating film formed on the second interlayer insulating film and comprising metal wiring layers; a first contact plug electrically connecting each of the metal wiring layers and the impurity region; and a second contact plug electrically connecting each of the metal wiring layers and the gate electrode, wherein the first contact plug is formed in the first and second interlayer insulating films, and the second contact plug is formed in the second interlayer insulating film.Type: GrantFiled: October 21, 2010Date of Patent: January 21, 2014Assignees: Samsung Electronics Co., Ltd., Infineon Technologies AG, International Business Machines CorporationInventors: Dong-Hee Yu, Bong-Seok Suh, Yoon-Hae Kim, O Sung Kwon, Oh-Jung Kwon
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Publication number: 20140015061Abstract: A memory device includes a storage unit formed using a substrate, a true bit line BL0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. The true bit line and the complementary bit line are adjacent to each other and are vertically stacked above the substrate.Type: ApplicationFiled: July 13, 2012Publication date: January 16, 2014Inventors: PERRY H. PELLEY, JAMES D. BURNETT
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Patent number: 8629561Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.Type: GrantFiled: July 3, 2012Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Maxime Darnon, Qinghuang Lin, Anthony D. Lisi, Satyanarayana V. Nitta
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Publication number: 20140008806Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.Type: ApplicationFiled: July 6, 2012Publication date: January 9, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
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Patent number: 8617981Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.Type: GrantFiled: April 12, 2013Date of Patent: December 31, 2013Assignee: Renesas Electronics CorporationInventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
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Patent number: 8618663Abstract: The present invention provides a method of fabricating an interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating. In general terms, a method is provided that includes providing at least one patternable low-k material on a surface of an inorganic antireflective coating that is located atop a substrate, said inorganic antireflective coating is vapor deposited and comprises atoms of M, C and H wherein M is at least one of Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La; forming at least one interconnect pattern within the at least one patternable low-k material; and curing the at least one patternable low-k material.Type: GrantFiled: September 20, 2007Date of Patent: December 31, 2013Assignee: International Business Machines CorporationInventors: Qinghuang Lin, Deborah A. Neumayer
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Patent number: 8618539Abstract: An interconnect sensor for detecting delamination due to coefficient of thermal expansion mismatch and/or mechanical stress. The sensor comprises a conductive path that includes a via disposed between two back end of line metal layers separated by a dielectric. The via is coupled between a first probe structure and a second probe structure and mechanically coupled to a stress inducing structure. The via is configured to alter the conductive path in response to mechanical stress caused by the stress inducing structure. The stress inducing structure can be a through silicon via or a solder ball. The dielectric material can be a low-k dielectric material. In another embodiment, a method of forming an interconnect sensor is provided for detecting delamination.Type: GrantFiled: November 5, 2009Date of Patent: December 31, 2013Assignee: QUALCOMM IncorporatedInventors: Brian Matthew Henderson, Shiqun Gu, Homyar C. Mogul, Mark M. Nakamoto, Arvind Chandrasekaran