Abstract: A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination.

Abstract: The present invention discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate, a local interconnect structure connected to the semiconductor substrate, and at least one via stack structure electrically connected to the local interconnect structure, wherein the at least one via stack structure comprises a via having an upper via and a lower via, the width of the upper via being greater than that of the lower via; a via spacer formed closely adjacent to the inner walls of the lower via; an insulation layer covering the surfaces of the via and the via spacer; a conductive plug formed within the space surrounded by the insulation layer, and electrically connected to the local interconnect structure. The present invention is applicable to manufacture of a via stack in the filed of manufacturing semiconductor.

Abstract: A wiring substrate includes an insulating layer, a wiring layer buried in the insulating layer, and a connection pad connected to the wiring layer via a via conductor provided in the insulating layer and in which at least a part is buried in an outer surface side of the insulating layer, wherein the connection pad includes a first metal layer (a first copper layer) arranged on the outer surface side, an intermediate metal layer (a nickel layer) arranged on a surface of an inner layer side of the first metal layer, and a second metal layer (a second copper layer) arranged on a surface of an inner layer side of the intermediate metal layer, and a hardness of the intermediate metal layer is higher than a hardness of the first metal layer and the second metal layer.

Abstract: A through silicon via (TSV) structure including a semiconductor substrate; a first inter-metal dielectric (IMD) layer on the semiconductor substrate; a cap layer overlying the IMD layer; a conductive layer extending through the cap layer, the first IMD layer and into the semiconductor substrate; a tungsten film capping a top surface of the conductive layer; a second IMD layer overlying the cap layer and covering the tungsten film; and an interconnect feature in the second IMD layer.

Abstract: A semiconductor memory device includes: a first n-type transistor; a first p-type transistor; a first wiring layer having a first interconnecting portion for connecting a drain of the first n-type transistor and a drain of the first p-type transistor; and a second wiring layer having a first conductive portion electrically connected to the first interconnecting portion.

Abstract: A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers.

Abstract: A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the first conductor pattern.

Abstract: A method for manufacturing a chip package is provided. The method including: holding a carrier including a plurality of dies; forming a separation between the plurality of dies by removing from the carrier one or more portions of the carrier between the plurality of dies; forming an encapsulation material in the removed one or more portions between the plurality of dies; separating the dies through the encapsulation material.

Abstract: An interconnect structure for use in an integrated circuit is provided. The interconnect structure includes a first low-K dielectric material. The first low-K material may be modified with a first group of carbon nanotubes (CNTs) and disposed on a metal line. The first low-K material is modified by dispersing the first group of CNTs in a solution, spinning the solution onto a silicon wafer and curing the solution to form the first low-K material modified with the first CNTs. The metal line includes a top layer and a bottom layer connected by a metal via. The interconnect structure also includes a second low-K dielectric material modified with a second group of CNTs and disposed on the bottom layer. Accordingly, embodiments the present disclosure could help to increase the mechanical strength of the low-K material or the entire interconnect structure.

Abstract: A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier layer is located within an opening that is located within a dielectric material and it is between a diffusion barrier layer and a conductive material which are also present within the opening. The redundant diffusion barrier includes a single layered or multilayered structure comprising Ru and a Co-containing material including pure Co or a Co alloy including at least one of N, B and P.

Abstract: A semiconductor device has a semiconductor die. An encapsulant is formed over the semiconductor die. A conductive micro via array is formed over the encapsulant outside a footprint of the semiconductor die. A first through-mold-hole having a step-through-hole structure is formed through the encapsulant to expose the conductive micro via array. In one embodiment, forming the conductive micro via array further includes forming an insulating layer over the encapsulant and the semiconductor die, forming a micro via array through the insulating layer outside the footprint of the semiconductor die, and forming a conductive layer over the insulating layer. In another embodiment, forming the conductive micro via array further includes forming a conductive ring.

Abstract: An integrated circuit package system includes a substrate, forming a resist layer having an elongated recess over the substrate, forming a via in the substrate below the elongated recess, and forming an elongated bump in the elongated recess over the via.

Abstract: A method for fabricating an integrated circuit (IC) chip includes providing a passivation layer over a circuit structure, an opening in the passivation layer exposing a pad of the circuit structure, next forming a first titanium-containing layer over the pad exposed by the opening, next performing an annealing process by heating the titanium-containing layer at a temperature of between 300 and 410° C. for a time of between 20 and 150 minutes in a nitrogen ambient with a nitrogen purity of great than 99%, next forming a second titanium-containing layer on the first titanium-containing layer, and then forming a metal layer on the second titanium-containing layer.

Abstract: A microelectronic assembly is provided in which first and second electrically conductive pads exposed at front surfaces of first and second microelectronic elements, respectively, are juxtaposed, each of the microelectronic elements embodying active semiconductor devices. An electrically conductive element may extend within a first opening extending from a rear surface of the first microelectronic element towards the front surface thereof, within a second opening extending from the first opening towards the front surface of the first microelectronic element, and within a third opening extending through at least one of the first and second pads to contact the first and second pads. Interior surfaces of the first and second openings may extend in first and second directions relative to the front surface of the first microelectronic element, respectively, to define a substantial angle.

Abstract: A single metal damascene structure including an insulating layer, a metal filling layer and a barrier layer is provided. The insulating layer has an opening therein, and the metal filling layer is positioned in the opening. The barrier layer is located between the filling metal layer and the insulating layer. The material of the barrier layer includes an alloy, and the ally includes a copper element and at least one another metal.

Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a wafer containing an interconnect structure. The interconnect structure includes a plurality of vias and interconnect lines. The semiconductor device includes a first conductive pad disposed over the interconnect structure. The first conductive pad is electrically coupled to the interconnect structure. The semiconductor device includes a plurality of second conductive pads disposed over the interconnect structure. The semiconductor device includes a passivation layer disposed over and at least partially sealing the first and second conductive pads. The semiconductor device includes a conductive terminal that is electrically coupled to the first conductive pad but is not electrically coupled to the second conductive pads.

Abstract: A nanopatterned surface is prepared by forming a block copolymer film on a miscut crystalline substrate, annealing the block copolymer film, then reconstructing the surface of the annealed block copolymer film. The method creates a well-ordered array of voids in the block copolymer film that is maintained over a large area. The nanopatterned block copolymer films can be used in a variety of different applications, including the fabrication of high density data storage media.

Abstract: A semiconductor device includes a substrate having a first surface and an opposite second surface. An electrode extends within the substrate towards the first surface and has a protruding portion extending from the first surface. A supporting portion extends from the first surface of the substrate to a sidewall of the protruding portion and supports the protruding portion.

Abstract: An array of functional cells includes a subset of cells powered by at least one supply rail. That supply rail is formed of first segments located on a first metallization level and second segments located on a second metallization level with at least one conductor element extending between the first and second segments to electrically connect successive segments of the supply rail.

Abstract: An integrated circuit structure comprises a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.

Abstract: Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.

Abstract: A semiconductor device includes: at least one semiconductor element having electrode terminals; a metal plate supporting the semiconductor element; and a wiring board covering the semiconductor element and including a plurality of insulating layers and wiring layers alternately stacked and external connection terminals on a surface, the wiring layers being electrically connected to each other by vias. The electrode terminals and the external connection terminals are electrically connected via at least one of the wiring layers and the vias. At least one of the electrode terminals, the is wiring layers, and the vias is electrically connected to the metal plate.

Abstract: This document discusses, among other things, example systems including integrated circuit contacts configured to reduce the likelihood of shorting to unrelated portions of overlying conductive material due to contact misalignment.

Abstract: A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Abstract: A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.

Abstract: An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.

Abstract: According to one embodiment, provided is a semiconductor device including a lower layer wiring, and an upper layer wiring that is drawn in the same direction as a direction in which the lower layer wiring is drawn. Intermediate wirings include at least a first intermediate wiring and a second intermediate wiring. Conductors include at least a plurality of first conductors connecting between the lower layer wiring and the first intermediate wiring, a plurality of second conductors connecting between the upper layer wiring and the second intermediate wiring, and a plurality of third conductors which connect between the first intermediate wiring and the second intermediate wiring, and are less in number than the first conductors or the second conductors on a drawn side of the lower layer wiring and the upper layer wiring.

Abstract: A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A guard ring is employed to enclose the metal-oxide-metal capacitor so as to prevent moisture from penetrating into the low k dielectric material.

Abstract: A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second patterns are coexistent within the plane of the semiconductor substrate, and the occupation ratio of the total of the first patterns and the second patterns within the plane of the semiconductor substrate, that is, the occupation ratio of the redistribution interconnects is 35 to 60%.

Abstract: A post passivation rerouting support structure comprises a relatively thin support layer above the passivation layer to support the RDL, and a relatively thick support layer for fine pitch interconnects extending from the RDL and terminating as contact structures at the surface of the thick support layer, for a next level packaging structure. The thick support layer is planarized before defining the contact structures. The thick support layer may be formed after the conducting posts have been formed, or the thick support layer is formed before forming the conducting posts in vias formed in the thick support layer. An encapsulating layer may be provided above the thick support layer, which top surface is planarized before defining the contact structures. The encapsulating layer and the further support layer may be the same layer.

Abstract: A method for forming a multi-level stack having a multi-level contact is provided. The method includes forming a multi-level stack comprising a specified number, n, of conductive layers and at least n?1 insulating layers. A via formation layer is formed over the stack. A first via is etched in the via formation layer at a first edge of the stack. A first multi-level contact is formed in the first via. For a particular embodiment, a second via may be etched in the via formation layer at a second edge of the stack and a second multi-level contact may be formed in the second via.

Abstract: A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.

Abstract: A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are more appropriate to be used for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.

Abstract: A multi-chip semiconductor apparatus includes a plurality of semiconductor chips electrically connected and stacked. Each of the semiconductor chips trims a voltage level used in the semiconductor chip in response to a chip select signal.

Abstract: A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A plurality of first micro-vias can be formed in the first insulating layer. A conductive layer is formed in the first micro-openings and over the first insulating layer. A second insulating layer is formed over the first insulating layer and conductive layer. A portion of the second insulating layer is removed to expose the conductive layer and form a plurality of second micro-openings in the second insulating layer over the conductive layer. The second micro-openings can be micro-vias, micro-via ring, or micro-via slots. Removing the portion of the second insulating layer leaves an island of the second insulating layer over the conductive layer. A bump is formed over the conductive layer. A third insulating layer is formed in the second micro-openings over the bump. The second micro-openings provide stress relief.

Abstract: Semiconductor packages are provided. The semiconductor package includes a first chip having a first inclined sidewall in an edge of the first chip; and a second chip having a second inclined sidewall in an edge of the second chip and the second chip being horizontally adjacent to the first chip such that the first and second inclined sidewalls are in substantial contact with each other.

Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.

Abstract: A semiconductor device including: a first mono-crystal layer and a second mono-crystal layer and at least one conductive layer in-between; where the at least one conductive layer includes a first conductive layer overlaying a second conductive layer overlying a third conductive layer, and where the second conductive layer having a predetermined second layer current carrying capacity greater than the current carrying capacity of the first conductive layer, and the second conductive layer current carrying capacity being greater than the current carrying capacity of the third conductive layer.

Abstract: The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.

Abstract: A semiconductor device includes a through electrode that penetrates through a silicon substrate, an isolation trench provided to penetrate through the silicon substrate to surround the through electrode, a first silicon film in contact with an inner surface of the isolation trench, a second silicon film in contact with an outer surface of the isolation trench, and an insulation film provided between the first and second silicon films.

Abstract: An electrical interconnect providing an interconnect between contacts on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a plurality of through holes extending from a first surface to a second surface. A resilient material is located in the through holes. The resilient material includes an opening extending from the first surface to the second surface. A plurality of discrete, free-flowing conductive nano-particles are located in the openings of the resilient material. The conductive particles are substantially free of non-conductive materials. A plurality of first contact members are located in the through holes adjacent the first surface and a plurality of second contact members are located in the through holes adjacent the second surface. The first and second contact members are electrically coupled to the nano-particles.

Abstract: A device with through-silicon via (TSV) and a method of forming the same includes the formation of an opening in a silicon substrate, the formation of a first insulation layer on the sidewalls and bottom of the opening, the formation of a second insulation layer on the sidewalls and bottom of the opening. A first interface between the first insulation layer and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm. A second interface between the second insulation layer and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm.

Abstract: A non-volatile memory device includes a lower molding layer, a horizontal interconnection line on the lower molding layer, an upper molding layer on the horizontal interconnection line, pillars extending vertically through the upper molding layer, the horizontal interconnection line, and the lower molding layer, and a buffer layer interposed between the pillars and the molding layers. The device also includes variable resistance material and a diode layer interposed between the pillars and the horizontal interconnection line.

Abstract: A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions.

Abstract: Presented are device structures and methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: A chip structure includes a semiconductor substrate, an interconnecting metallization structure, a passivation layer, a circuit layer and a bump. The interconnecting metallization structure is over the semiconductor substrate. The passivation layer is over the interconnecting metallization structure. The circuit layer is over the passivation layer. The bump is on the circuit layer, and the bump is unsuited for being processed using a reflow process.

Abstract: A method for manufacturing a semiconductor device is disclosed. A semiconductor substrate such as bare silicon is provided, and a dielectric layer is formed over the semiconductor substrate. An opening is provided within the dielectric layer by removing a portion of the dielectric layer. A conformal first conductive layer is formed over the dielectric layer and the opening. A conformal second conductive layer is formed over the first conductive layer. A conformal barrier layer is formed over the second conductive layer.

Abstract: A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO2 layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO2 layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.

Abstract: Methods of fabricating semiconductor devices that include interposers include the formation of conductive vias through a material layer on a recoverable substrate. A carrier substrate is bonded over the material layer, and the recoverable substrate is then separated from the material layer to recover the recoverable substrate. A detachable interface may be provided between the material layer and the recoverable substrate to facilitate the separation. Electrical contacts that communicate electrically with the conductive vias may be formed over the material layer on a side thereof opposite the carrier substrate. Semiconductor structures and devices are formed using such methods.

Abstract: Disclosed is a semiconductor device that is capable of preventing impurities such as moisture from being introduced into an active region at the time of dicing and at the time of bonding and that is capable of being easily miniaturized. The semiconductor device includes a cylindrical dummy wire having an opening for allowing a wire interconnecting a semiconductor element and an external connection terminal to pass therethrough, extending in an insulation film provided on a semiconductor layer having the semiconductor element to surround the semiconductor element, and disposed inside the external connection terminal.