Change Of State Resulting From Use Of External Beam, E.g., Laser Beam Or Ion Beam (epo) Patents (Class 257/E23.148)
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Patent number: 9679686Abstract: A process tunable resistor is fabricated by adjusting elements of the resistor during a fabrication process. The elements include legs, turns, and elements such as a parallel sub-legs, that are adjusted in the fabrication process to provide a specific user defined resistance value. The process tunable resistor provides for fixed contact points in order to support pre-existing or define circuit designs.Type: GrantFiled: December 23, 2011Date of Patent: June 13, 2017Assignee: Intel CorporationInventors: Scot E. Zickel, Tripti Nayak, Alexandra M. Kern
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Patent number: 9653558Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a source region, a drain region, a gate, and a dummy contact. The source region and the drain region are formed in the substrate. The gate is formed on the substrate and between the source region and the drain region. The dummy contact includes a plurality of dummy plugs formed on the substrate, wherein the dummy plugs have depths decreasing towards the drain region.Type: GrantFiled: June 15, 2015Date of Patent: May 16, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Yin Hsiao, Kai-Kuen Chang, Kun-Huang Yu
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Patent number: 8969752Abstract: The present invention provides a laser processing method comprising the steps of attaching a protective tape 25 to a front face 3 of a wafer 1a, irradiating a substrate 15 with laser light L while employing a rear face of the wafer 1a as a laser light entrance surface and locating a light-converging point P within the substrate 15 so as to form a molten processed region 13 due to multiphoton absorption, causing the molten processed region 13 to form a cutting start region 8 inside by a predetermined distance from the laser light entrance surface along a line 5 along which the object is intended to be cut in the wafer 1a, attaching an expandable tape 23 to the rear face 21 of the wafer 1a, and expanding the expandable tape 23 so as to separate a plurality of chip parts 24 produced upon cutting the wafer 1a from the cutting start region 8 acting as a start point from each other.Type: GrantFiled: September 11, 2003Date of Patent: March 3, 2015Assignee: Hamamatsu Photonics K.K.Inventors: Kenshi Fukumitsu, Fumitsugu Fukuyo, Naoki Uchiyama
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Patent number: 8889490Abstract: As for a memory element implemented in a semiconductor device typified by an RFID, it is an object of the present invention to reduce manufacturing steps and to provide a memory element and a memory circuit having the element with reduced cost. It is a feature of the present invention that a memory element sandwiched between electrodes has an organic compound, and an electrode connected to a semiconductor element controlling the memory element functions as an electrode of the memory element. In addition, an extremely thin semiconductor film formed on an insulated surface is used for the memory element; therefore cost can be reduced.Type: GrantFiled: July 2, 2010Date of Patent: November 18, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Yoshinobu Asami
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Patent number: 8816278Abstract: A method is provided for imaging a region of interest. The method includes defining a lamella within a microelectronic device, where the region of interest is in the lamella. The lamella has a first and second surface, and a first sacrificial layer contacts the first surface. The region of interest includes a material of interest, and an imaging technique capable of detecting the material of interest is selected. A support layer is formed on the second surface, where the support layer is transparent to the imaging technique. The first sacrificial layer is removed, and an image of the region of interest is produced.Type: GrantFiled: September 5, 2013Date of Patent: August 26, 2014Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Zhou Yongkai, Zhu Jie, Du An Yan
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Patent number: 8431467Abstract: An object to be processed is restrained from warping at the time of laser processing. A modified region M2 is formed within a wafer 11, and fractures a2, b2 extending in directions parallel to the thickness direction of the wafer 11 and tilted with respect to a plane including lines 5 are generated from the modified region M2. A modified region M3 is formed within the wafer 11, and a fracture a3 extending in a direction parallel to the thickness direction of the wafer 11 and tilted with respect to the plane including the lines 5 is generated from the modified region M3 so as to connect with the fracture b2. That is, the fractures a2, a3, b2 are generated so as to be connected together.Type: GrantFiled: August 19, 2011Date of Patent: April 30, 2013Assignee: Hamamatsu Photonics K.K.Inventor: Takeshi Sakamoto
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Patent number: 8298905Abstract: A method for forming a functional element includes a first step of forming an insulating layer composed of an insulator phase of a transition metal oxide serving as a metal-to-insulator transition material, the transition metal oxide being mainly composed of vanadium dioxide, and a second step of causing part of the insulating layer to transition to a metallic phase, in which the insulator phase differs from the metallic phase in terms of electrical resistivity and/or light transmittance.Type: GrantFiled: March 9, 2010Date of Patent: October 30, 2012Assignee: Sony CorporationInventor: Daisuke Ito
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Patent number: 8049299Abstract: An antifuse (40, 80, 90?) comprises, first (22?, 24?) and second (26?) conductive regions having spaced-apart curved portions (55, 56), with a first dielectric region (44) therebetween, forming in combination with the curved portions (55, 56) a curved breakdown region (47) adapted to switch from a substantially non-conductive initial state to a substantially conductive final state in response to a predetermined programming voltage. A sense voltage less than the programming voltage is used to determine the state of the antifuse as either OFF (high impedance) or ON (low impedance). A shallow trench isolation (STI) region (42) is desirably provided adjacent the breakdown region (47) to inhibit heat loss from the breakdown region (47) during programming. Lower programming voltages and currents are observed compared to antifuses (30) using substantially planar dielectric regions (32).Type: GrantFiled: February 25, 2009Date of Patent: November 1, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Won Gi Min, Geoffrey W. Perkins, Kyle D. Zukowski, Jiang-Kai Zuo
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Patent number: 7982285Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.Type: GrantFiled: January 8, 2008Date of Patent: July 19, 2011Assignee: International Business Machines CorporationInventors: Byeongju Park, Subramanian S. Iyer, Chandrasekharan Kothandaraman
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Patent number: 7911025Abstract: Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.Type: GrantFiled: May 27, 2008Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: Louis C. Hsu, Rajiv V. Joshi, Jack Allan Mandelman, Chih-Chao Yang
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Patent number: 7629234Abstract: A method is used in processing structures on or within a semiconductor substrate using N series of laser pulses to obtain a throughput benefit, wherein N?2. The structures are arranged in a plurality of substantially parallel rows extending in a generally lengthwise direction. The N series of laser pulses propagate along N respective beam axes until incident upon selected structures in N respective distinct rows. The method determines a joint velocity profile for simultaneously moving in the lengthwise direction the N laser beam axes substantially in unison relative to the semiconductor substrate so as to process structures in the N rows with the respective N series of laser pulses, whereby the joint velocity profile is such that the throughput benefit is achieved while ensuring that the joint velocity profile represents feasible velocities for each of the N series of laser pulses and for each of the respective N rows of structures processed with the N series of laser pulses.Type: GrantFiled: February 4, 2005Date of Patent: December 8, 2009Assignee: Electro Scientific Industries, Inc.Inventor: Kelly J. Bruland
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Patent number: 7550360Abstract: In a method of manufacturing a solid electrolytic capacitor, at first, an anodic oxide film is formed on the surface of an aluminum base. Then, a solid electrolyte layer is formed of a conductive polymer or the like on the anodic oxide film. Then, a cathode electrode portion including a silver paste layer is formed on the solid electrolyte layer. Then, a conductive paste is coated on the anodic oxide film on one side of the aluminum base and cured, thereby forming a metal silver layer. Then, a laser beam is irradiated from the opposite side of the aluminum base to weld together the aluminum base and the metal silver layer, thereby forming an anode electrode portion.Type: GrantFiled: June 18, 2007Date of Patent: June 23, 2009Assignee: NEC TOKIN CorporationInventors: Yuji Yoshida, Katsuhiro Yoshida
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Patent number: 7479670Abstract: The invention relates to an electronic component made primarily from organic materials with high resolution structuring, in particular to an organic field effect transistor (OFET) with a small source-drain distance, and to a production method thereof. The organic electronic component has depressions and/or modified regions in which the conductor tracks/electrodes, which can be metallic, for example, are arranged, and which have been produced by means of a laser during production.Type: GrantFiled: August 14, 2004Date of Patent: January 20, 2009Assignee: PolyIC GmbH & Co KGInventors: Walter Fix, Ronan Martin, Andreas Ullmann
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Publication number: 20080224261Abstract: Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor stricture Methods of making and programming the fuse/anti-fuse structures are also provided.Type: ApplicationFiled: May 27, 2008Publication date: September 18, 2008Applicant: International Business Machines CorporationInventors: Louis C. Hsu, Rajiv V. Joshi, Jack Allan Mandelman, Chih-Chao Yang
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Publication number: 20080224260Abstract: A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state.Type: ApplicationFiled: March 12, 2008Publication date: September 18, 2008Applicant: EASIC CORPORATIONInventors: Herman Schmit, Ronnie Vasishta, Adam Levinthal, Jonathan Park
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Publication number: 20080218772Abstract: A wafer handling robot, ion implanter system including a wafer handling robot and a related method are disclosed. An ion implanter system may include an ion implanting station including a load lock coupled thereto; a wafer handling robot located at least partially within the load lock, the wafer handling robot including an end effecter for handling at least one wafer, and a motor for moving the end effecter vertically; and a sensor positioned within the load lock to determine a vertical position of the end effecter.Type: ApplicationFiled: March 6, 2007Publication date: September 11, 2008Inventors: Brant S. Binns, Kevin Daniels, Robert A. Poltras
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Patent number: 7423286Abstract: The present invention is directed to methods for transferring pre-formed electronic devices, such as transistors, resistors, capacitors, diodes, semiconductors, inductors, conductors, and dielectrics, and segments of materials, such as magnetic materials and crystalline materials onto a variety of receiving substrates using energetic beam transfer methods. Also provided is a consumable intermediate comprising a transfer substrate and a transfer material coated thereon, wherein the transfer material may be comprised of pre-formed electronic devices or magnetic materials and crystalline materials that may be transferred to a variety of receiving substrates. Aspects of the present invention may also be used to form multi-device electronic components such as sensor devices, electro-optical devices, communications devices, transmit-receive modules, and phased arrays using the consumable intermediates and transfer methods described herein.Type: GrantFiled: September 7, 2004Date of Patent: September 9, 2008Assignee: SI2 Technologies, Inc.Inventors: Erik S. Handy, Joseph Michael Kunze, Peter T. Kazlas
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Publication number: 20080157271Abstract: A semiconductor device has a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a wiring formed in the insulating layer and an antifuse including first and second connecting portions coupled to the wiring. The anti fuse has a space provided between the first connecting portion and the second connecting portion and insulating the first connecting portion from the second connecting portion. The first connecting portion and the second connecting portion may be coupled by a conductive material disposed in the space.Type: ApplicationFiled: December 21, 2007Publication date: July 3, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kazumasa SUZUKI
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Patent number: 7145243Abstract: Formation of a mixed-material composition through diffusion using photo-thermal energy. The diffusion may be used to create electrically conductive traces. The diffusion may take place between material layers on one of a package substrate, semiconductor substrate, substrate for a printed circuit board (PCB), or other multi-layered substrate. The photo-thermal energy may be supplied by various devices, for example a YAG laser device, CO2 laser device, or other energy source.Type: GrantFiled: July 9, 2003Date of Patent: December 5, 2006Assignee: Intel CorporationInventors: Gary A. Brist, Gary B. Long, Daryl A. Sato
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Patent number: 6818966Abstract: A method and structure for controlling the surface properties in the dielectric layers in a thin film component can be provided for improving the trimming process of thin film element. A metal fill is configured with a uniform fill pattern beneath an array of thin film resistors, and can comprise a plurality of smaller features or peaks providing a finer fill pattern that improves the control of the topology of the dielectric layers. The fill pattern can be configured in various manners, such as fill patterns parallel to the thin film resistor, fill patterns perpendicular to the thin film resistor, or fill patterns comprising a checkerboard-like configuration.Type: GrantFiled: September 20, 2002Date of Patent: November 16, 2004Assignee: Texas Instruments IncorporatedInventors: Eric W. Beach, Walter B. Meinel, Eric L. Hoyt