Abstract: In the present disclosure, a semiconductor structure includes an Mx-1 layer including a first dielectric layer and first metal features, wherein the first metal features include a first set of first metal features in a first region and a second set of first metal features in a second region, wherein the first set has a first pattern density and the second set has a second pattern density being greater than the first pattern density. The structure further includes a Vx layer disposed over the Mx-1 layer, the Vx layer including first vias contacting the first set of the first metal features. The structure further includes an Mx layer disposed over the Vx layer, the Mx layer including a fuse element, wherein the fuse element has a first thickness in the first region less than a second thickness in the second region.

Abstract: A semiconductor device and a method of manufacturing a semiconductor are provided. In an embodiment, a metallic layer may be formed over a semiconductor substrate. An anti-reflective layer may be formed over the metallic layer. A passivation layer may be formed over the anti-reflective layer. An opening may be formed in the passivation layer to expose the anti-reflective layer.

Abstract: A semiconductor structure includes first and second transistors each having a source terminal, a drain terminal, and a gate terminal. The semiconductor structure further includes a program line; a first metal plate over the first and the second transistors; a first insulator over the first metal plate; a second metal plate over the first insulator; a second insulator over the second metal plate; and a third metal plate over the second insulator. The first metal plate, the first insulator, and the second metal plate form a first anti-fuse element. The second metal plate, the second insulator, and the third metal plate form a second anti-fuse element. The source terminal of the first transistor is electrically connected to the first metal plate. The source terminal of the second transistor is electrically connected to the third metal plate. The program line is electrically connected to the second metal plate.

Abstract: An interconnect structure, along with methods of forming such, are described. In some embodiments, the structure includes a first dielectric layer disposed over one or more devices, a first conductive feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first conductive feature, and a second conductive feature disposed in the second dielectric layer. The second conductive feature is electrically connected to the first conductive feature. The structure further includes a heat dissipation layer disposed between the first and second dielectric layers, and the heat dissipation layer partially surrounds the second conductive feature and is electrically isolated from the first and second conductive features.

Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided, in which the substrate is provided with a peripheral area and an array area; an insulation layer is formed on the substrate; a first mask layer with a first mask pattern is formed on the insulation layer; the insulation layer is etched by taking the first mask layer as a mask, to form a contact hole in the array area; a first electrode layer is formed; a second mask layer with a second mask pattern is formed, in which the second mask layer is arranged on the first electrode layer; and the first electrode layer and the first mask layer are etched by taking the second mask layer as a mask until the insulation layer in the array area is exposed, in which a remaining portion of the first electrode layer forms a lower electrode layer.

Abstract: The present disclosure relates to calibrating scanner devices for positioning laser beams in a processing field, and includes, e.g.: arranging a retroreflector in the processing field of the scanner device, the processing field being formed in a processing chamber for irradiating powder layers; detecting laser radiation reflected back into the scanner device when the laser beam passes over the retroreflector; determining an actual position of the laser beam in the processing field using the detected laser radiation; and calibrating the scanner device by correcting a laser beam target position specified for the scanner device in the processing field using the determined actual position of the laser beam in the processing field.

Abstract: The embodiments relate to a semiconductor structure and a fabrication method thereof. The fabrication method includes: providing a wafer, in the wafer there being provided with a scribe line, in the scribe line there being provided with a test pad, a first test structure, and a second test structure; the second test structure being positioned below the first test structure, and a transverse pitch between the second test structure and the first test structure being at least equal to a width of the test pad; forming a protective layer on the wafer, the protective layer at least covering the scribe line; and performing exposure and development on the protective layer, such that a thickness of the protective layer remained above the first test structure is greater than that of the protective layer remained above the second test structure.

Abstract: Disclosed are an integrated circuit device and a formation method thereof. The formation method of an integrated circuit device comprises the following steps: providing a substrate, wherein a first plug and a second plug are disposed inside the substrate; forming a first covering layer covering the substrate; forming, in the first region, a first opening exposing the first plug; forming a first conductive layer in the first opening; forming an isolation layer covering the first conductive layer and the first covering layer; forming, in the first region, a contact hole exposing the first conductive layer and a trench located above the contact hole and connecting with the contact hole, and forming, in the second region, a second opening exposing the second plug; and forming a conductive connection layer in the contact hole, forming a second conductive layer in the trench, and forming a fuse wire in the second opening.

Abstract: Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.

Abstract: A method of making a semiconductor device includes operations directed toward electrically connecting a component to a first fuse, wherein the first fuse is on a first conductive level a first distance from the component; identifying a conductive element for omission between the first fuse and a second fuse; and electrically connecting the component to the second fuse, wherein the second fuse is on a second conductive level a second distance from the component, the second distance is greater than the first distance, and the electrically connecting the component to the second fuse comprises electrically connecting the component to the second fuse without forming the identified conductive element.

Abstract: A laser-beam power-modulation system includes an acousto-optic modulator (AOM) to receive a laser beam and separate the laser beam into a primary beam and a plurality of diffracted beams based on an input signal. The power of the primary beam depends on the input signal. The system also includes a slit to transmit the primary beam and dump the plurality of diffracted beams, a controller to generate a control signal based at least in part on feedback indicative of the power of the primary beam or the power of a beam generated using the primary beam, and a driver to generate the input signal based at least in part on the control signal.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a conductive feature in a first dielectric layer. The semiconductor device structure also includes an etching stop layer over the first dielectric layer and a second dielectric layer over the etching stop layer. The semiconductor device structure further includes a conductive via in the etching stop layer and the second dielectric layer. In addition, the semiconductor device structure includes a conductive line over the conductive via. The semiconductor device structure also includes a first barrier liner covering the bottom surface of the conductive line. The semiconductor device structure further includes a second barrier liner surrounding sidewalls of the conductive line and the conductive via. The conductive line and the conductive via are confined in the first barrier liner and the second barrier liner.

Abstract: A test system and test techniques for accurate high-current parametric testing of semiconductor devices. In operation, the test system supplies a current to the semiconductor device and measures a voltage on the device. The testing system may use the measured voltage to compute an ON resistance for the high-current semiconductor device. In one technique, multiple force needles contact a pad in positions that provide equi-resistant paths to one or more sense needles contacting the same pad. In another technique, current flow through the force needles is regulated such that voltage at the pad of the device under test is representative of the ON resistance of the device and independent of contact resistance of the force needle. Another technique entails generating an alarm indication when the contact resistance of a force needle exceeds a threshold.

Abstract: A semiconductor device includes a first dielectric layer formed on a second dielectric layer and planar contacts formed in the second dielectric layer. The planar contacts are spaced apart to form a gap therebetween. The first dielectric layer includes a thermally conductive dielectric layer and is formed on lateral sides of the planar contacts and in the gap. A resistive element is formed between the planar contacts over the gap and in contact with at least the thermally conductive dielectric layer in the gap.

Abstract: A semiconductor device includes a first dielectric layer formed from a thermally conductive dielectric material. Contacts are formed in the first dielectric layer, the planar contacts being spaced apart to form a gap therebetween. The thermally conductive dielectric material of the first dielectric layer is formed on lateral sides of the planar contacts and in the gap. A resistive element is formed laterally across the gap between the planar contacts and in direct contact with at least the thermally conductive dielectric material in the gap.

Abstract: An EOS event detection circuit coupled to a power supply via a supply voltage rail and comprising a plurality of sub-circuits coupled to the supply voltage rail, each sub-circuit comprising a first transistor, a Zener diode coupled between the supply voltage rail and a first terminal of the first transistor, and a fusible element coupled between a second terminal of the first transistor and the supply voltage rail, wherein the first transistor is configured to cause the fusible element to open when an EOS event occurring on the supply voltage rail exceeds a reverse breakdown voltage of the Zener diode, and wherein the Zener diode in each sub-circuit has a different reverse breakdown voltage.

Abstract: A semiconductor device includes a first dielectric layer formed on a second dielectric layer and planar contacts formed in the second dielectric layer. The planar contacts are spaced apart to form a gap therebetween. The first dielectric layer includes a thermally conductive dielectric layer and is formed on lateral sides of the planar contacts and in the gap. A resistive element is formed between the planar contacts over the gap and in contact with at least the thermally conductive dielectric layer in the gap.

Abstract: A semiconductor device includes a first dielectric layer formed on a second dielectric layer and planar contacts formed in the second dielectric layer. The planar contacts are spaced apart to form a gap therebetween. The first dielectric layer includes a thermally conductive dielectric layer and is formed on lateral sides of the planar contacts and in the gap. A resistive element is formed between the planar contacts over the gap and in contact with at least the thermally conductive dielectric layer in the gap.

Abstract: A semiconductor device includes: an electric fuse circuit including first electric fuses used as data bits and second electric fuses used as polarity bits; and a write circuit configured to selectively pass a current through the first electric fuses and the second electric fuses and thereby write data in the electric fuse circuit. The write circuit is configured to perform a first process when number of write bits included in write data is larger than a value obtained by dividing total number of bits in the write data by 2. The first process includes writing of inverted write data in a plurality of first electric fuses, and including writing of inversion data in one of the second electric fuses. The plurality of first electric fuses are part of the first electric fuses. The inverted write data is inverted data of the write data. The inversion data represents inversion.

Abstract: The present invention provides a laser processing method comprising the steps of attaching a protective tape 25 to a front face 3 of a wafer 1a, irradiating a substrate 15 with laser light L while employing a rear face of the wafer 1a as a laser light entrance surface and locating a light-converging point P within the substrate 15 so as to form a molten processed region 13 due to multiphoton absorption, causing the molten processed region 13 to form a cutting start region 8 inside by a predetermined distance from the laser light entrance surface along a line 5 along which the object is intended to be cut in the wafer 1a, attaching an expandable tape 23 to the rear face 21 of the wafer 1a, and expanding the expandable tape 23 so as to separate a plurality of chip parts 24 produced upon cutting the wafer 1a from the cutting start region 8 acting as a start point from each other.

Abstract: A structure and design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Abstract: The present invention generally relates to an optical system that is able to reliably deliver a uniform amount of energy across an anneal region contained on a surface of a substrate. The optical system is adapted to deliver, or project, a uniform amount of energy having a desired two-dimensional shape on a desired region on the surface of the substrate. An energy source for the optical system is typically a plurality of lasers, which are combined to form the energy field.

Abstract: A fuse part of a semiconductor device includes an insulation layer over a substrate, and a fuse over the insulation layer, wherein the fuse includes a plurality of blowing pads for irradiating a laser beam and the plurality of blowing pads have laser coordinates different from one another.

Abstract: A semiconductor device includes a fuse configured to be programmed in response to a laser, a protective layer formed under the fuse and overlapping with a portion of the fuse, and a heat emission portion coupled with the protective layer.

Abstract: A metal electrically programmable fuse (“eFuse”) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip width, at both ends of the metal strip. The strip width can be a lithographic minimum dimension, and the ratio of the length of the metal strip to the strip width is greater than 5 to localize heating around the center of the metal strip during programming. Localization of heating reduces required power for programming the metal eFuse. Further, a gradual temperature gradient is formed during the programming within a portion of the metal strip that is longer than the Blech length so that electromigration of metal gradually occurs reliably at the center portion of the metal strip. Metal line portions are provides at the same level as the metal eFuse to physically block debris generated during programming.

Abstract: A semiconductor device includes an upper interconnect, a lower interconnect, insulating layers interposed between the upper interconnect and the lower interconnect, a connecting portion that is formed in the insulating layers and connects the upper interconnect and the lower interconnect, and an element that is placed in one of the insulating layers and has a conductive layer connected to the connecting portion. The connecting portion is formed over the lower interconnect and the end portions of the conductive layer of the element, and is in contact with the upper face of the lower interconnect and the upper faces and side faces of the end portions of the conductive layer of the element.

Abstract: The semiconductor device includes: a substrate; an electric fuse that includes a lower-layer wiring formed on the substrate, a first via provided on the lower-layer wiring and connected to the lower-layer wiring, and an upper-layer wiring provided on the first via and connected to the first via, a flowing-out portion of a conductive material constituting the electric fuse being formed in a cut-off state of the electric fuse; and a heat diffusion portion that includes a heat diffusion wiring that is formed in the same layer as one of the upper-layer wiring and the lower-layer wiring and is placed on a side of the one of the upper-layer wiring and the lower-layer wiring, the heat diffusion portion being electrically connected to the one of the upper-layer wiring and the lower-layer wiring.

Abstract: The invention relates to a method for producing metallic interconnect lines on the surface of a substrate comprising: an etching step for defining trenches within said substrate; a step for filling said trenches using electrodeposition of a metal exhibiting a crystalline lattice, further comprising the production of a so-called metal invasion layer, on top of said trenches filled with grains of metal so as to define said interconnect lines, characterized in that it also comprises the following steps: determination of a first direction (D1) of orientation of grains along a trench and of a second direction (D2) of orientation of grains in a direction perpendicular to a trench; determination of a third direction (D3) of ion channelling in the crystalline lattice of said metal; determination of at least one direction of orientation (Di1, Di2, Di3) of an ion implantation beam in said metal invasion layer, by performing the scalar products: of a first vector relative to said first direction (D1, <110>) an

Abstract: A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Abstract: The present invention relates to a fuse for a semiconductor device, and discloses the technique capable of preventing fuse damage, which might occur during a fuse blowing step, with reducing area of the fuse occupying the semiconductor device. The present invention includes a common source region, wherein a plurality of fuses are radially arranged about the common source region, and a fuse box wall is formed outside the fuses.

Abstract: A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Abstract: According to one exemplary embodiment, a method for monitoring structural integrity of at least one fuse in semiconductor wafer, which includes at least one electrical monitoring structure, includes forming a monitoring window in a dielectric layer overlying the at least one electrical monitoring structure, where the monitoring window and a fuse window overlying the at least one fuse are, in one embodiment, formed in a same etch process. The method further includes performing at least one electrical measurement on the at least one electrical monitoring structure, wherein the at least one electrical measurement is utilized to monitor the structural integrity of the at least one fuse. A change in the at least one electrical measurement is utilized to indicate a change in the structural integrity of the at least one fuse. The at least one electrical monitoring structure can include, for example, a metal serpentine line and one or more metal combs.

Abstract: Disclosed herein is a fuse of a semiconductor memory device and a repair process for the same. The fuse includes a lower conductive film of a multilayer interconnection formed on a lower structure of a semiconductor substrate, an upper conductive film of the multilayer interconnection spaced apart upward from the lower conductive film to define a predetermined vertical space therebetween, and a contact electrode, which vertically connects the upper and lower conductive films to each other and forms a fuse body. The lower conductive film includes a form not coinciding with that of the upper conductive film. With such a configuration, the device can achieve a stable minimization in the length of the fuse and the distance between adjacent fuses in consideration of a laser beam irradiation region for the high integration of the semiconductor memory device. In this way, the device performs the repair process of cutting the contact electrode and/or upper conductive film using a laser beam.

Abstract: A method and system for locally processing a predetermined microstructure formed on a substrate without causing undesirable changes in electrical or physical characteristics of the substrate or other structures formed on the substrate are provided. The method includes providing information based on a model of laser pulse interactions with the predetermined microstructure, the substrate and the other structures. At least one characteristic of at least one pulse is determined based on the information. A pulsed laser beam is generated including the at least one pulse. The method further includes irradiating the at least one pulse having the at least one determined characteristic into a spot on the predetermined microstructure. The at least one determined characteristic and other characteristics of the at least one pulse are sufficient to locally process the predetermined microstructure without causing the undesirable changes.

Abstract: A fuse of a semiconductor device includes a fuse pattern separated by a blowing region formed on an interlayer insulating film, and a recess formed by removing a portion of the upper portion of a plurality of contacts disposed in the lower portion of the blowing region. After the fuse pattern is blown, the fuse pattern moves in the reliable environment, thereby preventing the electric short to improve yield of the semiconductor device.

Abstract: A semiconductor integrated circuit device has: a layer insulating film formed on a semiconductor substrate; a fuse portion which is configured by an uppermost metal wiring layer that is formed on the layer insulating film; an inorganic insulating protective film which is formed on the metal wiring layer and the layer insulating film; and an organic insulating protective film which is formed on the inorganic insulating protective film. An opening is formed in the organic insulating protective film so that the inorganic insulating protective on the fuse portion is exposed. According to this configuration, it is not required to etch away the layer insulating film in order to form an opening above the fuse portion. Therefore, the time period required for forming the opening can be shortened and the whole production time period can be shortened.

Abstract: A semiconductor device includes plural fuse elements which can be disconnected by irradiating a laser beam, and attenuation members which are located between the plural fuse elements as viewed two-dimensionally and can attenuate the laser beam. Each attenuation member includes plural columnar bodies. With this arrangement, the attenuation members including plural columnar units absorb the laser beam leaked out from a fuse element to be disconnected to a semiconductor substrate side. The laser beam is also scattered by Fresnel diffraction. Therefore, the columnar body can efficiently attenuate the laser beam, without generating a crack in the insulation film by absorbing excessive energy.

Abstract: A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure.

Abstract: A semiconductor device having a semiconductor substrate, an insulating layer, a fuse, a diffusion layer and a resistor. The semiconductor substrate has a first conductivity type. The insulating layer is selectively formed on the surface of the semiconductor substrate. The fuse is formed on the insulating layer. The diffusion layer has a second conductivity type. The diffusion layer is formed on the surface of the semiconductor substrate and electrically connected to the fuse. The first resistor is electrically connected to the fuse.

Abstract: An integrated component includes a semiconductor substrate; at least one interconnect applied on the semiconductor substrate; an insulating layer applied on the at least one interconnect; and at least one opening through the insulating layer which interrupts the at least one interconnect into a first section and a second section.

Abstract: A semiconductor device has a plurality of fuse element portions each of which including a first fuse interconnect having a fuse to be portion, a second fuse interconnect connected to an internal circuit, a first impurity diffusion layer for electrically connecting the first fuse interconnect and the second fuse interconnect, and a second impurity diffusion layers. The first fuse interconnect, the second fuse interconnect, and the first impurity diffusion layer of each of the plurality of fuse element portions are arranged approximately parallel to one another at a predetermined pitch distance.

Abstract: Provided is a three-dimensional semiconductor device. The three-dimensional semiconductor device includes a body in which a plurality of semiconductor chips or packages are stacked, a protective substrate configured to protect an outer layer chip or package of the body and configured to transmit a laser beam, and a fuse pattern portion having a pattern of a fuse function formed to cut off an electrical connection of a defective chip or package by the laser beam penetrating the protective substrate when at least one of the chips or packages is defective.

Abstract: A method is used in processing structures on or within a semiconductor substrate using N series of laser pulses to obtain a throughput benefit, wherein N?2. The structures are arranged in a plurality of substantially parallel rows extending in a generally lengthwise direction. The N series of laser pulses propagate along N respective beam axes until incident upon selected structures in N respective distinct rows. The method determines a joint velocity profile for simultaneously moving in the lengthwise direction the N laser beam axes substantially in unison relative to the semiconductor substrate so as to process structures in the N rows with the respective N series of laser pulses, whereby the joint velocity profile is such that the throughput benefit is achieved while ensuring that the joint velocity profile represents feasible velocities for each of the N series of laser pulses and for each of the respective N rows of structures processed with the N series of laser pulses.

Abstract: A semiconductor device of the present invention comprises: a substrate; a plurality of wiring layers formed over the substrate; a fuse formed in an uppermost one of the plurality of wiring layers; a first insulating film made up of a single film and formed on the uppermost wiring layer such that the first insulating film is in contact with a surface of the fuse; and a second insulating film formed on the first insulating film; wherein the second insulating film has an opening therein formed above a fuse region of the uppermost wiring layer such that only the first insulating film exists above the fuse region, the fuse region including the fuse and being irradiated with a laser beam when the fuse is blown.

Abstract: The present invention relates to a laser fuse structure for high power applications. Specifically, the laser fuse structure of the present invention comprises first and second conductive supporting elements (12a, 12b), at least one conductive fusible link (14), first and second connection elements (20a, 20b), and first and second metal lines (22a, 22b). The conductive supporting elements (12a, 12b), the conductive fusible link (14), and the metal lines (22a, 22b) are located at a first metal level (3), while the connect elements (20a, 20b) are located at a second, different metal level (4) and are connected to the conductive supporting elements (12a, 12b) and the metal lines (22a, 22b) by conductive via stacks (18a, 18b, 23a, 23b) that extend between the first and second metal levels (3, 4).

Abstract: An integrated circuit device is provided including an integrated circuit substrate having a fuse region. A window layer is provided on the integrated circuit substrate that defines a fuse region. The window layer is positioned at an upper portion of the integrated circuit device and recessed beneath a surface of the integrated circuit device. A buffer pattern is provided between the integrated circuit substrate and the window layer and a fuse pattern is provided between the buffer pattern and the window layer. Methods of forming integrated circuit devices are also described.

Abstract: This invention pertains to a color coatings blender apparatus to be used for color composition customization for the application of color coatings on 2D and 3D surfaces. The apparatus is comprised of a main body and interchangeable inserts all with central blender chambers and primary and secondary ports, and interchangeable spindles; the configurations of which are governed by coating technical characteristics. This invention integrates gradient specific programmable computer digital processes to function as internal editors, manipulate information and present the operator with multiple options and production overrides. This invention will make data analysis more interactive by utilizing existing external software applications as editors and expanding the process of visual communications for multiple purposes. While the blender apparatus, complete with external selectable appurtenances, can be used manually, it can also be combined with a programmable computer for producing physical gradient layers.

Abstract: A method for producing an integrated circuit including a fuse element, a fuse-memory element or a resistor element is disclosed. In one embodiment, at least one metallization layer is applied onto a substrate. A hard mask is applied onto the at least one metallization layer. The at least one metallization layer is wet chemically etched by using the hard mask and the fuse element. The fuse-memory element or the resistor element is formed in a region in which the at least one metallization layer has been etched.

Abstract: The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to an e-fuse device including an opening, a first via and a second via in an interlayer dielectric, wherein the opening, the first via and the second via are connected to an interconnect below the interlayer dielectric; a dielectric layer that encloses the first via and the second via; and a metal layer over the dielectric layer, wherein the metal layer fills the opening with a metal, and wherein the first via and the second via are substantially empty to allow for electromigration of the interconnect during re-programming of the e-fuse device.

Abstract: A laser fuse structure for a semiconductor device, the laser fuse structure having an array of laser fuses wherein one or more of the fuses in the array have a tortuous fuse line extending between first and second connectors that connect the fuse to an underlying circuit area.