Change Of State Resulting From Use Of External Beam, E.g., Laser Beam Or Ion Beam (epo) Patents (Class 257/E23.15)
  • Patent number: 10373908
    Abstract: A semiconductor device includes a first dielectric layer formed on a second dielectric layer and planar contacts formed in the second dielectric layer. The planar contacts are spaced apart to form a gap therebetween. The first dielectric layer includes a thermally conductive dielectric layer and is formed on lateral sides of the planar contacts and in the gap. A resistive element is formed between the planar contacts over the gap and in contact with at least the thermally conductive dielectric layer in the gap.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Kangguo Cheng, Zhengwen Li, Fei Liu
  • Patent number: 10224277
    Abstract: A semiconductor device includes a first dielectric layer formed from a thermally conductive dielectric material. Contacts are formed in the first dielectric layer, the planar contacts being spaced apart to form a gap therebetween. The thermally conductive dielectric material of the first dielectric layer is formed on lateral sides of the planar contacts and in the gap. A resistive element is formed laterally across the gap between the planar contacts and in direct contact with at least the thermally conductive dielectric material in the gap.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Kangguo Cheng, Zhengwen Li, Fei Liu
  • Patent number: 10116129
    Abstract: An EOS event detection circuit coupled to a power supply via a supply voltage rail and comprising a plurality of sub-circuits coupled to the supply voltage rail, each sub-circuit comprising a first transistor, a Zener diode coupled between the supply voltage rail and a first terminal of the first transistor, and a fusible element coupled between a second terminal of the first transistor and the supply voltage rail, wherein the first transistor is configured to cause the fusible element to open when an EOS event occurring on the supply voltage rail exceeds a reverse breakdown voltage of the Zener diode, and wherein the Zener diode in each sub-circuit has a different reverse breakdown voltage.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: October 30, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: William K. Laird, Joseph J. Crowfoot
  • Patent number: 9941202
    Abstract: A semiconductor device includes a first dielectric layer formed on a second dielectric layer and planar contacts formed in the second dielectric layer. The planar contacts are spaced apart to form a gap therebetween. The first dielectric layer includes a thermally conductive dielectric layer and is formed on lateral sides of the planar contacts and in the gap. A resistive element is formed between the planar contacts over the gap and in contact with at least the thermally conductive dielectric layer in the gap.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Kangguo Cheng, Zhengwen Li, Fei Liu
  • Patent number: 9620432
    Abstract: A semiconductor device includes a first dielectric layer formed on a second dielectric layer and planar contacts formed in the second dielectric layer. The planar contacts are spaced apart to form a gap therebetween. The first dielectric layer includes a thermally conductive dielectric layer and is formed on lateral sides of the planar contacts and in the gap. A resistive element is formed between the planar contacts over the gap and in contact with at least the thermally conductive dielectric layer in the gap.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: April 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Cao, Kangguo Cheng, Zhengwen Li, Fei Liu
  • Patent number: 9576676
    Abstract: A semiconductor device includes: an electric fuse circuit including first electric fuses used as data bits and second electric fuses used as polarity bits; and a write circuit configured to selectively pass a current through the first electric fuses and the second electric fuses and thereby write data in the electric fuse circuit. The write circuit is configured to perform a first process when number of write bits included in write data is larger than a value obtained by dividing total number of bits in the write data by 2. The first process includes writing of inverted write data in a plurality of first electric fuses, and including writing of inversion data in one of the second electric fuses. The plurality of first electric fuses are part of the first electric fuses. The inverted write data is inverted data of the write data. The inversion data represents inversion.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: February 21, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Yasuo Kanda
  • Patent number: 8969752
    Abstract: The present invention provides a laser processing method comprising the steps of attaching a protective tape 25 to a front face 3 of a wafer 1a, irradiating a substrate 15 with laser light L while employing a rear face of the wafer 1a as a laser light entrance surface and locating a light-converging point P within the substrate 15 so as to form a molten processed region 13 due to multiphoton absorption, causing the molten processed region 13 to form a cutting start region 8 inside by a predetermined distance from the laser light entrance surface along a line 5 along which the object is intended to be cut in the wafer 1a, attaching an expandable tape 23 to the rear face 21 of the wafer 1a, and expanding the expandable tape 23 so as to separate a plurality of chip parts 24 produced upon cutting the wafer 1a from the cutting start region 8 acting as a start point from each other.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: March 3, 2015
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Kenshi Fukumitsu, Fumitsugu Fukuyo, Naoki Uchiyama
  • Patent number: 8692375
    Abstract: A structure and design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, William R. Tonti, Chih-Chao Yang
  • Patent number: 8569187
    Abstract: The present invention generally relates to an optical system that is able to reliably deliver a uniform amount of energy across an anneal region contained on a surface of a substrate. The optical system is adapted to deliver, or project, a uniform amount of energy having a desired two-dimensional shape on a desired region on the surface of the substrate. An energy source for the optical system is typically a plurality of lasers, which are combined to form the energy field.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: October 29, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Stephen Moffatt, Douglas E. Holmgren, Samuel C. Howells, Edric Tong, Bruce E. Adams, Jiping Li, Aaron Muir Hunter
  • Patent number: 8552427
    Abstract: A fuse part of a semiconductor device includes an insulation layer over a substrate, and a fuse over the insulation layer, wherein the fuse includes a plurality of blowing pads for irradiating a laser beam and the plurality of blowing pads have laser coordinates different from one another.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: October 8, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Yun Nam
  • Publication number: 20130113071
    Abstract: A semiconductor device includes a fuse configured to be programmed in response to a laser, a protective layer formed under the fuse and overlapping with a portion of the fuse, and a heat emission portion coupled with the protective layer.
    Type: Application
    Filed: September 14, 2012
    Publication date: May 9, 2013
    Inventor: Min-Yung LEE
  • Patent number: 8421186
    Abstract: A metal electrically programmable fuse (“eFuse”) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip width, at both ends of the metal strip. The strip width can be a lithographic minimum dimension, and the ratio of the length of the metal strip to the strip width is greater than 5 to localize heating around the center of the metal strip during programming. Localization of heating reduces required power for programming the metal eFuse. Further, a gradual temperature gradient is formed during the programming within a portion of the metal strip that is longer than the Blech length so that electromigration of metal gradually occurs reliably at the center portion of the metal strip. Metal line portions are provides at the same level as the metal eFuse to physically block debris generated during programming.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: April 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Baozhen Li, Chunyan E. Tian, Chih-Chao Yang
  • Patent number: 8357991
    Abstract: A semiconductor device includes an upper interconnect, a lower interconnect, insulating layers interposed between the upper interconnect and the lower interconnect, a connecting portion that is formed in the insulating layers and connects the upper interconnect and the lower interconnect, and an element that is placed in one of the insulating layers and has a conductive layer connected to the connecting portion. The connecting portion is formed over the lower interconnect and the end portions of the conductive layer of the element, and is in contact with the upper face of the lower interconnect and the upper faces and side faces of the end portions of the conductive layer of the element.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: January 22, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Daisuke Oshida, Hiroyuki Kunishima, Norio Okada
  • Patent number: 8354731
    Abstract: The semiconductor device includes: a substrate; an electric fuse that includes a lower-layer wiring formed on the substrate, a first via provided on the lower-layer wiring and connected to the lower-layer wiring, and an upper-layer wiring provided on the first via and connected to the first via, a flowing-out portion of a conductive material constituting the electric fuse being formed in a cut-off state of the electric fuse; and a heat diffusion portion that includes a heat diffusion wiring that is formed in the same layer as one of the upper-layer wiring and the lower-layer wiring and is placed on a side of the one of the upper-layer wiring and the lower-layer wiring, the heat diffusion portion being electrically connected to the one of the upper-layer wiring and the lower-layer wiring.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: January 15, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiromichi Takaoka, Yoshitaka Kubota, Hiroshi Tsuda
  • Patent number: 8334206
    Abstract: The invention relates to a method for producing metallic interconnect lines on the surface of a substrate comprising: an etching step for defining trenches within said substrate; a step for filling said trenches using electrodeposition of a metal exhibiting a crystalline lattice, further comprising the production of a so-called metal invasion layer, on top of said trenches filled with grains of metal so as to define said interconnect lines, characterized in that it also comprises the following steps: determination of a first direction (D1) of orientation of grains along a trench and of a second direction (D2) of orientation of grains in a direction perpendicular to a trench; determination of a third direction (D3) of ion channelling in the crystalline lattice of said metal; determination of at least one direction of orientation (Di1, Di2, Di3) of an ion implantation beam in said metal invasion layer, by performing the scalar products: of a first vector relative to said first direction (D1, <110>) an
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: December 18, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Vincent Carreau
  • Publication number: 20120261794
    Abstract: A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 18, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis L. HSU, William R. TONTI, Chih-Chao YANG
  • Patent number: 8274135
    Abstract: The present invention relates to a fuse for a semiconductor device, and discloses the technique capable of preventing fuse damage, which might occur during a fuse blowing step, with reducing area of the fuse occupying the semiconductor device. The present invention includes a common source region, wherein a plurality of fuses are radially arranged about the common source region, and a fuse box wall is formed outside the fuses.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: September 25, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Heon Kim
  • Patent number: 8232649
    Abstract: A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, William R. Tonti, Chih-Chao Yang
  • Patent number: 8106476
    Abstract: According to one exemplary embodiment, a method for monitoring structural integrity of at least one fuse in semiconductor wafer, which includes at least one electrical monitoring structure, includes forming a monitoring window in a dielectric layer overlying the at least one electrical monitoring structure, where the monitoring window and a fuse window overlying the at least one fuse are, in one embodiment, formed in a same etch process. The method further includes performing at least one electrical measurement on the at least one electrical monitoring structure, wherein the at least one electrical measurement is utilized to monitor the structural integrity of the at least one fuse. A change in the at least one electrical measurement is utilized to indicate a change in the structural integrity of the at least one fuse. The at least one electrical monitoring structure can include, for example, a metal serpentine line and one or more metal combs.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: January 31, 2012
    Assignee: Broadcom Corporation
    Inventors: Robert I. Wu, Robert Lutze, Jung Kuan Wang, Voon Yean Ten, Liming Tsau
  • Patent number: 7977164
    Abstract: Disclosed herein is a fuse of a semiconductor memory device and a repair process for the same. The fuse includes a lower conductive film of a multilayer interconnection formed on a lower structure of a semiconductor substrate, an upper conductive film of the multilayer interconnection spaced apart upward from the lower conductive film to define a predetermined vertical space therebetween, and a contact electrode, which vertically connects the upper and lower conductive films to each other and forms a fuse body. The lower conductive film includes a form not coinciding with that of the upper conductive film. With such a configuration, the device can achieve a stable minimization in the length of the fuse and the distance between adjacent fuses in consideration of a laser beam irradiation region for the high integration of the semiconductor memory device. In this way, the device performs the repair process of cutting the contact electrode and/or upper conductive film using a laser beam.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: July 12, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun Kwon An
  • Patent number: 7955906
    Abstract: A method and system for locally processing a predetermined microstructure formed on a substrate without causing undesirable changes in electrical or physical characteristics of the substrate or other structures formed on the substrate are provided. The method includes providing information based on a model of laser pulse interactions with the predetermined microstructure, the substrate and the other structures. At least one characteristic of at least one pulse is determined based on the information. A pulsed laser beam is generated including the at least one pulse. The method further includes irradiating the at least one pulse having the at least one determined characteristic into a spot on the predetermined microstructure. The at least one determined characteristic and other characteristics of the at least one pulse are sufficient to locally process the predetermined microstructure without causing the undesirable changes.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: June 7, 2011
    Assignee: GSI Group Corporation
    Inventors: James J. Cordingley, Jonathan S. Ehrman, David M. Filgas, Shepard D. Johnson, Joohan Lee, Donald V. Smart, Donald J. Svetkoff
  • Publication number: 20110108946
    Abstract: A fuse of a semiconductor device includes a fuse pattern separated by a blowing region formed on an interlayer insulating film, and a recess formed by removing a portion of the upper portion of a plurality of contacts disposed in the lower portion of the blowing region. After the fuse pattern is blown, the fuse pattern moves in the reliable environment, thereby preventing the electric short to improve yield of the semiconductor device.
    Type: Application
    Filed: June 25, 2010
    Publication date: May 12, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventor: Jin Won PARK
  • Patent number: 7872327
    Abstract: A semiconductor integrated circuit device has: a layer insulating film formed on a semiconductor substrate; a fuse portion which is configured by an uppermost metal wiring layer that is formed on the layer insulating film; an inorganic insulating protective film which is formed on the metal wiring layer and the layer insulating film; and an organic insulating protective film which is formed on the inorganic insulating protective film. An opening is formed in the organic insulating protective film so that the inorganic insulating protective on the fuse portion is exposed. According to this configuration, it is not required to etch away the layer insulating film in order to form an opening above the fuse portion. Therefore, the time period required for forming the opening can be shortened and the whole production time period can be shortened.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: January 18, 2011
    Assignee: Panasonic Corporation
    Inventor: Katsuhiko Tsuura
  • Patent number: 7868417
    Abstract: A semiconductor device includes plural fuse elements which can be disconnected by irradiating a laser beam, and attenuation members which are located between the plural fuse elements as viewed two-dimensionally and can attenuate the laser beam. Each attenuation member includes plural columnar bodies. With this arrangement, the attenuation members including plural columnar units absorb the laser beam leaked out from a fuse element to be disconnected to a semiconductor substrate side. The laser beam is also scattered by Fresnel diffraction. Therefore, the columnar body can efficiently attenuate the laser beam, without generating a crack in the insulation film by absorbing excessive energy.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: January 11, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Sumio Ogawa
  • Patent number: 7820493
    Abstract: A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: October 26, 2010
    Assignee: Marvell International Ltd.
    Inventors: Chuan-Cheng Cheng, Shuhua Yu, Roawen Chen, Albert Wu
  • Patent number: 7816761
    Abstract: A semiconductor device having a semiconductor substrate, an insulating layer, a fuse, a diffusion layer and a resistor. The semiconductor substrate has a first conductivity type. The insulating layer is selectively formed on the surface of the semiconductor substrate. The fuse is formed on the insulating layer. The diffusion layer has a second conductivity type. The diffusion layer is formed on the surface of the semiconductor substrate and electrically connected to the fuse. The first resistor is electrically connected to the fuse.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: October 19, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Noboru Egawa, Yasuhiro Fukuda
  • Patent number: 7799583
    Abstract: An integrated component includes a semiconductor substrate; at least one interconnect applied on the semiconductor substrate; an insulating layer applied on the at least one interconnect; and at least one opening through the insulating layer which interrupts the at least one interconnect into a first section and a second section.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: September 21, 2010
    Assignee: Infineon Technologies AG
    Inventors: Günther Ruhl, Markus Hammer, Regina Kainzbauer
  • Patent number: 7791111
    Abstract: A semiconductor device has a plurality of fuse element portions each of which including a first fuse interconnect having a fuse to be portion, a second fuse interconnect connected to an internal circuit, a first impurity diffusion layer for electrically connecting the first fuse interconnect and the second fuse interconnect, and a second impurity diffusion layers. The first fuse interconnect, the second fuse interconnect, and the first impurity diffusion layer of each of the plurality of fuse element portions are arranged approximately parallel to one another at a predetermined pitch distance.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: September 7, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Kazumasa Kuroyanagi, Shoji Koyama
  • Publication number: 20100193903
    Abstract: Provided is a three-dimensional semiconductor device. The three-dimensional semiconductor device includes a body in which a plurality of semiconductor chips or packages are stacked, a protective substrate configured to protect an outer layer chip or package of the body and configured to transmit a laser beam, and a fuse pattern portion having a pattern of a fuse function formed to cut off an electrical connection of a defective chip or package by the laser beam penetrating the protective substrate when at least one of the chips or packages is defective.
    Type: Application
    Filed: July 30, 2008
    Publication date: August 5, 2010
    Applicant: EPWORKS CO., LTD.
    Inventor: Gu-Sung Kim
  • Publication number: 20100133651
    Abstract: A method is used in processing structures on or within a semiconductor substrate using N series of laser pulses to obtain a throughput benefit, wherein N?2. The structures are arranged in a plurality of substantially parallel rows extending in a generally lengthwise direction. The N series of laser pulses propagate along N respective beam axes until incident upon selected structures in N respective distinct rows. The method determines a joint velocity profile for simultaneously moving in the lengthwise direction the N laser beam axes substantially in unison relative to the semiconductor substrate so as to process structures in the N rows with the respective N series of laser pulses, whereby the joint velocity profile is such that the throughput benefit is achieved while ensuring that the joint velocity profile represents feasible velocities for each of the N series of laser pulses and for each of the respective N rows of structures processed with the N series of laser pulses.
    Type: Application
    Filed: December 2, 2009
    Publication date: June 3, 2010
    Applicant: Electro Scientific Industries, Inc.
    Inventor: Kelly J. Bruland
  • Patent number: 7728406
    Abstract: A semiconductor device of the present invention comprises: a substrate; a plurality of wiring layers formed over the substrate; a fuse formed in an uppermost one of the plurality of wiring layers; a first insulating film made up of a single film and formed on the uppermost wiring layer such that the first insulating film is in contact with a surface of the fuse; and a second insulating film formed on the first insulating film; wherein the second insulating film has an opening therein formed above a fuse region of the uppermost wiring layer such that only the first insulating film exists above the fuse region, the fuse region including the fuse and being irradiated with a laser beam when the fuse is blown.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: June 1, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yasuhiro Ido, Takeshi Iwamoto
  • Patent number: 7701035
    Abstract: The present invention relates to a laser fuse structure for high power applications. Specifically, the laser fuse structure of the present invention comprises first and second conductive supporting elements (12a, 12b), at least one conductive fusible link (14), first and second connection elements (20a, 20b), and first and second metal lines (22a, 22b). The conductive supporting elements (12a, 12b), the conductive fusible link (14), and the metal lines (22a, 22b) are located at a first metal level (3), while the connect elements (20a, 20b) are located at a second, different metal level (4) and are connected to the conductive supporting elements (12a, 12b) and the metal lines (22a, 22b) by conductive via stacks (18a, 18b, 23a, 23b) that extend between the first and second metal levels (3, 4).
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: April 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Stephen E. Greco, Erik L. Hedberg, Dae-Young Jung, Paul S. McLaughlin, Christopher D. Muzzy, Norman J. Rohrer, Jean E. Wynne
  • Patent number: 7696602
    Abstract: An integrated circuit device is provided including an integrated circuit substrate having a fuse region. A window layer is provided on the integrated circuit substrate that defines a fuse region. The window layer is positioned at an upper portion of the integrated circuit device and recessed beneath a surface of the integrated circuit device. A buffer pattern is provided between the integrated circuit substrate and the window layer and a fuse pattern is provided between the buffer pattern and the window layer. Methods of forming integrated circuit devices are also described.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: April 13, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyun-Chul Kim
  • Publication number: 20100084737
    Abstract: This invention pertains to a color coatings blender apparatus to be used for color composition customization for the application of color coatings on 2D and 3D surfaces. The apparatus is comprised of a main body and interchangeable inserts all with central blender chambers and primary and secondary ports, and interchangeable spindles; the configurations of which are governed by coating technical characteristics. This invention integrates gradient specific programmable computer digital processes to function as internal editors, manipulate information and present the operator with multiple options and production overrides. This invention will make data analysis more interactive by utilizing existing external software applications as editors and expanding the process of visual communications for multiple purposes. While the blender apparatus, complete with external selectable appurtenances, can be used manually, it can also be combined with a programmable computer for producing physical gradient layers.
    Type: Application
    Filed: January 17, 2007
    Publication date: April 8, 2010
    Inventors: Alain Lacourse, Mathieu Ducharme, Hugo St-Jean, Yves Gagnon, Yvon Savaria, Michel Meunier
  • Patent number: 7682958
    Abstract: A method for producing an integrated circuit including a fuse element, a fuse-memory element or a resistor element is disclosed. In one embodiment, at least one metallization layer is applied onto a substrate. A hard mask is applied onto the at least one metallization layer. The at least one metallization layer is wet chemically etched by using the hard mask and the fuse element. The fuse-memory element or the resistor element is formed in a region in which the at least one metallization layer has been etched.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: March 23, 2010
    Assignee: Infineon Technologies AG
    Inventors: Georg Seidemann, Reinhard Goellner
  • Patent number: 7671444
    Abstract: The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to an e-fuse device including an opening, a first via and a second via in an interlayer dielectric, wherein the opening, the first via and the second via are connected to an interconnect below the interlayer dielectric; a dielectric layer that encloses the first via and the second via; and a metal layer over the dielectric layer, wherein the metal layer fills the opening with a metal, and wherein the first via and the second via are substantially empty to allow for electromigration of the interconnect during re-programming of the e-fuse device.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: March 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ping-Chuan Wang, Wai-Kin Li
  • Patent number: 7667289
    Abstract: A laser fuse structure for a semiconductor device, the laser fuse structure having an array of laser fuses wherein one or more of the fuses in the array have a tortuous fuse line extending between first and second connectors that connect the fuse to an underlying circuit area.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: February 23, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hong Lin, Kang-Cheng Lin
  • Publication number: 20100032798
    Abstract: The semiconductor device includes: a substrate; an electric fuse that includes a lower-layer wiring formed on the substrate, a first via provided on the lower-layer wiring and connected to the lower-layer wiring, and an upper-layer wiring provided on the first via and connected to the first via, a flowing-out portion of a conductive material constituting the electric fuse being formed in a cut-off state of the electric fuse; and a heat diffusion portion that includes a heat diffusion wiring that is formed in the same layer as one of the upper-layer wiring and the lower-layer wiring and is placed on a side of the one of the upper-layer wiring and the lower-layer wiring, the heat diffusion portion being electrically connected to the one of the upper-layer wiring and the lower-layer wiring.
    Type: Application
    Filed: August 3, 2009
    Publication date: February 11, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Hiromichi Takaoka, Yoshitaka Kubota, Hiroshi Tsuda
  • Patent number: 7659601
    Abstract: A semiconductor device having a moisture-proof dam and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating layer provided on a substrate having a fuse region. A fuse guard dam is provided on the interlayer insulating layer to surround the fuse region. A cover insulating layer is provided on the interlayer insulating layer to cover the fuse guard dam and have a fuse window exposing a middle part of the fuse region, and at least two upper extension dams are provided in the cover insulating layer to sequentially surround the fuse region and be connected to the fuse guard dam.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: February 9, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Suk Park, Won-Chul Lee
  • Patent number: 7633136
    Abstract: A semiconductor device includes an interlayer insulating film on a substrate. A runner part includes a plurality of runner lines spaced apart from each other by a regular interval under the interlayer insulating film. A fuse cut part includes a plurality of fuse lines spaced apart from each other by a wider interval than the interval between the runner lines. A via in the interlayer insulating film connects a fuse line and a runner line to each other.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: December 15, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Man-Jong Yu
  • Patent number: 7629234
    Abstract: A method is used in processing structures on or within a semiconductor substrate using N series of laser pulses to obtain a throughput benefit, wherein N?2. The structures are arranged in a plurality of substantially parallel rows extending in a generally lengthwise direction. The N series of laser pulses propagate along N respective beam axes until incident upon selected structures in N respective distinct rows. The method determines a joint velocity profile for simultaneously moving in the lengthwise direction the N laser beam axes substantially in unison relative to the semiconductor substrate so as to process structures in the N rows with the respective N series of laser pulses, whereby the joint velocity profile is such that the throughput benefit is achieved while ensuring that the joint velocity profile represents feasible velocities for each of the N series of laser pulses and for each of the respective N rows of structures processed with the N series of laser pulses.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: December 8, 2009
    Assignee: Electro Scientific Industries, Inc.
    Inventor: Kelly J. Bruland
  • Patent number: 7608910
    Abstract: A semiconductor device and methods for protecting a semiconductor device. In an example, the semiconductor device may include a semiconductor substrate including at least one electrostatic discharge (ESD) protection device, at least one metal interconnection line connected to the at least one ESD protection device through a conductive plug and a passivation layer disposed on less than all of the metal interconnection line. In an example method, a semiconductor device may be protected by diverting at least a portion of an electron build-up from an accumulation point to one or more protective circuits along one or more conductive paths, the electron build-up, without the diverting, sufficient to cause an ESD at the accumulation point. In another example, a semiconductor device may be protected by exposing one or more conductive lines to a fuse opening to avoid an ESD by diverting an electron build-up at the fuse opening to one or more ESD protection devices.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: October 27, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyung-Lae Eun
  • Patent number: 7605444
    Abstract: Provided are a fuse box that simultaneously prevents damage caused by laser blowing and cross talk between the fuses and a method of manufacturing the same. In a fuse box having an open region in which fuses are opened by laser blowing and a bundle region in which fuse opens do not occur, a capping layer, adjacent to the open region, having a metal layer and an insulation layer covers the outermost fuses in the bundle region, thereby reducing the influence of laser blowing of fuses in the bundle region, and preventing capacitive coupling caused by the formation of a parasitic capacitor between fuse lines and an insulation layer therebetween. Accordingly, cross talk due to the capacitive coupling can be prevented, thereby enhancing the reliability of a fuse circuit. Lower fuses can be disposed in a lower layer in the bundle region, thereby forming a two-layered fuse box.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: October 20, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-kyu Bang, Kun-gu Lee, Jeong-kyu Kim
  • Publication number: 20090236688
    Abstract: A semiconductor device includes a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern, and a second insulating layer formed on the first insulating layer and covering the fuse pattern.
    Type: Application
    Filed: June 4, 2009
    Publication date: September 24, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tai-Heui CHO, Kun-Gu LEE
  • Patent number: 7557455
    Abstract: A bond pad structure has a first conductive layer and an anti-reflective coating layer disposed on the first conductive layer. The first conductive layer includes first and second portions (which could be formed by etching). Part of the first portion is exposed within a bond pad opening, and the second portion is electrically connected to an integrated circuit. The anti-reflective coating layer also includes first and second portions (which could be formed by etching). The first portion may be located near the bond pad opening, and the second portion may be located farther away from the bond pad opening. A second conductive layer electrically connects the first and second portions of the first conductive layer. In this way, the first portion of the anti-reflective coating layer may undergo oxidation without leading to oxidation of the second portion of the anti-reflective coating layer.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: July 7, 2009
    Assignee: National Semiconductor Corporation
    Inventor: Thomas Bold
  • Patent number: 7550360
    Abstract: In a method of manufacturing a solid electrolytic capacitor, at first, an anodic oxide film is formed on the surface of an aluminum base. Then, a solid electrolyte layer is formed of a conductive polymer or the like on the anodic oxide film. Then, a cathode electrode portion including a silver paste layer is formed on the solid electrolyte layer. Then, a conductive paste is coated on the anodic oxide film on one side of the aluminum base and cured, thereby forming a metal silver layer. Then, a laser beam is irradiated from the opposite side of the aluminum base to weld together the aluminum base and the metal silver layer, thereby forming an anode electrode portion.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: June 23, 2009
    Assignee: NEC TOKIN Corporation
    Inventors: Yuji Yoshida, Katsuhiro Yoshida
  • Patent number: 7538410
    Abstract: The present invention provides a fuse structure. The fuse structure comprises a substrate, a plurality of conductive layers, a plurality of dielectric layers and a plurality of conductive plugs. The novel fuse structure includes a plurality of fuse units, and a new layout of the fuse units to increase the pitch between the fuse units, preventing the fuse structure from failing when misalignment of the laser beam and thermal scattering of the laser beam damage the second layer of the fuse structure in the laser blow process, thus increasing reliability and yield.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: May 26, 2009
    Assignee: Nanya Technology Corporation
    Inventor: Wu-Der Yang
  • Publication number: 20090079028
    Abstract: A semiconductor device has a fuse, an internal circuit and a protection capacitor. The fuse has a first terminal connected to be applied to a fixed voltage and a second terminal. The internal circuit includes a transistor. The transistor has a threshold voltage and a gate. The protection capacitor is connected between the second terminal of the fuse and the gate of the transistor. The protection capacitor supplies the threshold voltage to the transistor where the fuse supplies the fixed voltage to the protection capacitor.
    Type: Application
    Filed: November 10, 2008
    Publication date: March 26, 2009
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Yasuhiro Fukuda
  • Patent number: 7492032
    Abstract: A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: February 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-Kyu Bang, Kun-Gu Lee, Kyoung-Suk Lyu, Jeong-Ho Bang, Kyeong-Seon Shin, Ho-Jeong Choi, Seung-Gyoo Choi
  • Publication number: 20090014829
    Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.
    Type: Application
    Filed: September 12, 2008
    Publication date: January 15, 2009
    Inventors: Min-Sung Kang, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin