Comprising Fuses, I.e., Connections Having Their State Changed From Conductive To Nonconductive (epo) Patents (Class 257/E23.149)
  • Patent number: 11133228
    Abstract: A semiconductor integrated circuit includes: a semiconductor monocrystalline region; an insulating film provided on a main surface of the semiconductor monocrystalline region; a conductive layer having a rectangular shape provided on the insulating film and including at least a polycrystalline layer of p-type; electric-field relaxing layers having a lower specific resistivity than the conductive layer and each including a polycrystalline layer of n-type so as to be arranged on both sides of the conductive layer in a direction perpendicular to a current-flowing direction; a high-potential-side electrode in ohmic contact with the conductive layer at one end of the conductive layer in the current-flowing direction; and a low-potential-side electrode in ohmic contact with the conductive layer and the respective electric-field relaxing layers at another end of the conductive layer opposed to the one end in the current-flowing direction, and having a lower potential than the high-potential-side electrode.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: September 28, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hideaki Katakura
  • Patent number: 11093164
    Abstract: A memory component includes multiple fuses, a memory array having a multiple blocks, and control logic operatively coupled with the memory array and the plurality of fuses. The control logic is to receive an erase command associated with the memory array and attempt to erase, in response to receipt of the erase command, a block of the multiple blocks from the memory array. The control logic is further to detect a failure to completely erase the block. The control logic is further to receive a blow fuse command in response to the failure to completely erase the block. The control logic is to blow a fuse, of the multiple fuses, which is coupled with the block, to make the block of the multiple blocks inaccessible to the control logic.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Daniel J. Hubbard, Marc S. Hamilton, Kevin R. Brandt, William Akin
  • Patent number: 11036581
    Abstract: An apparatus includes a non-volatile storage circuit that includes a primary copy of a data value in a first storage location and a redundant copy of the data value in a second, different storage location. The data value includes one or more bits. The apparatus further includes an error detection circuit configured to retrieve contents of the first and second storage locations in response to a request for the data value. The error detection circuit is further configured to perform an error correction operation on the retrieved contents of the first and second storage locations to generate a data output responsive to the request, and to perform an error detection operation to generate an error signal that indicates whether the retrieved contents of the first and second storage locations are different.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: June 15, 2021
    Assignee: Apple Inc.
    Inventors: Wei Chen, Sanjay Pant
  • Patent number: 10985050
    Abstract: The present disclosure relates to the technical field of semiconductors, and in particular to a semiconductor chip, a semiconductor wafer and a method for manufacturing a semiconductor wafer. The semiconductor chip comprises: a substrate, devices provided on a side of the substrate, via holes running through the substrate, conductive material filled in the via holes and contacted with the devices, and a backside metal layer provided on the other side of the substrate away from the devices, the backside metal layer coming into contact with the conductive material so as to be electrically connected to the devices via the conductive material. The semiconductor chip, the semiconductor wafer and the method for manufacturing a semiconductor wafer of the present disclosure reduce the ground resistance and improve the heat dissipation of devices with via holes structure during the operation.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: April 20, 2021
    Assignee: Dynax Semiconductor, Inc.
    Inventors: Naiqian Zhang, Pan Pan
  • Patent number: 10861665
    Abstract: A micro-fuse assembly includes a substrate, a number of thin-film micro-fuses on the substrate, and a topping wafer configured to sealingly engage to at least one of the substrate or the thin-film micro-fuses to define a cavity therebetween. The cavity is configured to encapsulate the thin-film micro-fuses within an inert environment sealed within the cavity. A method of encapsulating a micro-fuse assembly within an inert environment using a topping wafer is also disclosed.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: December 8, 2020
    Assignee: Rosemount Aerospace Inc.
    Inventors: Roger Alan Backman, David P. Potasek
  • Patent number: 10283303
    Abstract: Provided is a semiconductor integrated circuit device including a fuse circuit whose area and cost are minimized by a simple circuit configuration. The fuse circuit includes a first fuse and a second fuse having substantially the same shape and different sheet resistances, which are connected in series between terminals with different potentials. In a state in which none of the fuses is cut, a potential of an output terminal is fixed to a potential of one of the terminals.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: May 7, 2019
    Assignee: ABLIC INC.
    Inventor: Minoru Ariyama
  • Patent number: 10177089
    Abstract: An advanced e-Fuse structure is described. An e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a large grained copper structure and the fuse element is comprised of a fine grained copper structure.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 10121740
    Abstract: A structure of an e-Fuse device in a semiconductor device is described. The e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a large grained copper layer and an aspect ratio reducing layer, and the fuse element is comprised of a fine grained copper structure.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 10083908
    Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: September 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, James J. Demarest, Christopher J. Penny, Christopher J. Waskiewicz
  • Patent number: 10032716
    Abstract: In one aspect of the invention, a method for fabricating an e-Fuse device is described. A trench structure is provided. The trench structure includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions. The trench is provided in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The trench is filled with copper. An annealing step converts the copper to create a large grained copper structure in the anode and cathode regions and a fine grained copper structure in the fuse element. Another aspect of the invention is an e-Fuse device which includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 9929104
    Abstract: A semiconductor device includes a substrate including at least two semiconductor chip regions and a scribe lane region disposed between the semiconductor chip regions. The semiconductor device additionally includes a first optical measurement pattern disposed on the substrate. The semiconductor device further includes a second optical measurement pattern disposed on an upper layer of the first optical measurement pattern, the second optical measurement pattern being spaced apart from the first optical measurement pattern. The semiconductor device additionally includes a three-dimensional (3D) shielding structure surrounding the first optical measurement pattern and including an electrically conductive material.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: March 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Sik Park, Yi-Gwon Kim, Yong-Kug Bae, Sung-Won Choi, Hee-Ho Ku, Ga-Hyun Yang
  • Patent number: 9666527
    Abstract: A fuse includes a semiconductor layer having a dielectric material formed thereon. An epitaxially grown material is formed in a trench within the dielectric material. The epitaxially grown material includes a peak region. A fuse metal is formed over the peak region and extends along sidewalls of the trench and over the dielectric material outside the trench. Contacts are formed outside the trench connecting to fuse metal over the dielectric material.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: May 30, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong He, Juntao Li, Junli Wang, Chih-Chao Yang
  • Patent number: 9029981
    Abstract: A semiconductor device comprises an active region including a core circuit forming region and a buffer forming region, and a fuse element forming region arranged on a corner of the active region and to be able to be electrically fused. It is possible to arrange the fuse element without forming the fuse in the core circuit forming region by arranging the fuse element forming region at the corner of the active region.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroyuki Furukawa
  • Patent number: 9024410
    Abstract: A semiconductor device includes a first insulating film formed above a semiconductor substrate, a fuse formed above the first insulating film, a second insulating film formed above the first insulating film and the fuse and including an opening reaching the fuse, and a third insulating film formed above the second insulating film and in the opening.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: May 5, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Shigetoshi Takeda
  • Patent number: 9024411
    Abstract: A three-dimensionally (3d) confined conductor advantageously used as an electronic fuse and self-aligned methods of forming the same. By non-conformal deposition of a dielectric film over raised structures, a 3d confined tube, which may be sub-lithographic, is formed between the raised structures. Etching holes which intersect the 3d confined region and subsequent metal deposition fills the 3d confined region and forms contacts. When the raised structures are gates, the fuse element may be located at the middle of the line (i.e. in pre-metal dielectric). Other methods for creating the structure are also described.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: May 5, 2015
    Assignee: International Business Machines Corporation
    Inventors: Junjun Li, Yan Zun Li, Chengwen Pei, Pinping Sun
  • Patent number: 8963284
    Abstract: A semiconductor device includes: an e-fuse gate, a floating pattern between the e-fuse gate and an e-fuse active portion, a blocking dielectric pattern between the floating pattern and the e-fuse gate, and an e-fuse dielectric layer between the floating pattern and the e-fuse active portion. The floating pattern includes a first portion between the e-fuse gate and the e-fuse active portion and a pair of second portions extended upward along both sidewalls of the e-fuse gate from both edges of the first portion.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Deok-Kee Kim
  • Patent number: 8957482
    Abstract: In various embodiments, the fuse is formed from silicide and on top of a fin of a fin structure. Because the fuse is formed on top of a fin, its width takes the width of the fin, which is very thin. Depending on implementations, the fuse is also formed using planar technology and includes a thin width. Because the width of the fuse is relatively thin, a predetermined current can reliably cause the fuse to be opened. Further, the fuse can be used with a transistor to form a memory cell used in memory arrays, and the transistor utilizes FinFET technology.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: February 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Lung Hsueh, Tao Wen Chung, Po-Yao Ke, Shine Chung
  • Patent number: 8952487
    Abstract: An electronic circuit arrangement in accordance with some embodiments has a substrate, the substrate including: a plurality of metallization layers located one above the other; a single fuse-link via coupled between a first metallization layer and a second metallization layer of the plurality of metallization layers, wherein the single fuse-link via is in the form of an electrical fuse link preferentially programmable by applying a sufficiently large current to melt or degenerate the fuse link; a plurality of through-contact vias coupled in parallel between a third metallization layer and a fourth metallization layer of the plurality of metallization layers, wherein the through-contact vias form a through-contact between the third and fourth metallization layers; and electrical circuit components, arranged in a circuit layer, which are electrically coupled to one another by means of the single fuse-link via and by means of the plurality of through-contact vias.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: February 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Andreas Rusch, Klaus Schruefer
  • Patent number: 8952486
    Abstract: An improved electrical-fuse (e-fuse) device including a dielectric layer having a first top surface, two conductive features embedded in the dielectric layer and a fuse element. Each conductive feature has a second top surface and a metal cap directly on the second top surface. Each metal cap has a third top surface that is above the first top surface of the dielectric layer. The fuse element is on the third top surface of each metal cap and on the first top surface of the dielectric layer. A method of forming the e-fuse device is also provided.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Stephen M. Gates, Baozhen Li, Dan Edelstein
  • Patent number: 8937365
    Abstract: In a semiconductor integrated circuit device including fuse elements for performing laser trimming processing, a dummy fuse formed of a first polycrystalline Si film is formed between the fuse elements formed of a second polycrystalline Si film, and a nitride film is formed on the dummy fuse. In this manner, the step difference of an interlayer film caused by the presence and absence of the fuse element formed of the polycrystalline Si film is eliminated, to thereby prevent SOG films having moisture-absorption characteristics on an inner surface of a fuse opening region and on an internal element side from connecting to each other.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: January 20, 2015
    Assignee: Seiko Instruments Inc.
    Inventor: Yukimasa Minami
  • Patent number: 8896089
    Abstract: Interposers for semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, an interposer includes a substrate, a contact pad disposed on the substrate, and a first through-via in the substrate coupled to the contact pad. A first fuse is coupled to the first through-via. A second through-via in the substrate is coupled to the contact pad, and a second fuse is coupled to the second through-via.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Wei Chiu, Tzu-Yu Wang, Wei-Cheng Wu, Chun-Yi Liu, Hsien-Pin Hu, Shang-Yun Hou
  • Patent number: 8890260
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry Hak-Lay Chuang, Kong-Beng Thei, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu, Bao-Ru Young
  • Patent number: 8872306
    Abstract: Provided are electrical connection structures and methods of fabricating the same. The structures may include a substrate including a bonding pad region provided with a bonding pad and a fuse region provided with a fuse, an insulating layer provided on the substrate and including a bonding pad opening exposing the bonding pad and a fuse opening exposing the fuse region, a connection terminal provided in the bonding pad region and electrically connected to the bonding pad, and a protection layer provided on the insulating layer including a first protection layer provided within the bonding pad region and a second protection layer in the fuse opening.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: October 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeonggi Jin, Jeong-woo Park, Ju-il Choi
  • Patent number: 8866257
    Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kaushik Chanda, Lynne M. Gignac, Wai-Kin Ll, Ping-Chaun Wang
  • Patent number: 8865592
    Abstract: A preferred embodiment includes a method of manufacturing a fuse element that includes forming a polysilicon layer over a semiconductor structure, doping the polysilicon layer with carbon or nitrogen, depositing a metal over the polysilicon layer; and annealing the metal and polysilicon layer to form a silicide in an upper portion of the polysilicon layer.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies AG
    Inventors: Jiang Yan, Henning Haffner, Frank Huebinger, SunOo Kim, Richard Lindsay, Klaus Schruefer
  • Patent number: 8860175
    Abstract: A fuse of a semiconductor device and a method for forming the same are disclosed. The fuse includes a first metal line formed over a semiconductor substrate, a second metal line spaced apart from the first metal line, and a contact fuses formed of a metal contact coupled to the first metal line and the second metal line. Upper parts of the contact fuses overlap with each other, and lower parts are spaced apart from each other. Since the fuse is formed of a metal contact, fuse oxidation and fuse movement can be prevented. A conventional metal-contact fabrication process can be used, so that mass production of semiconductor devices is possible. In addition, the fuse region is reduced in size, reducing production costs.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: October 14, 2014
    Assignee: SK hynix Inc.
    Inventor: Chi Hwan Jang
  • Patent number: 8853799
    Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: October 7, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Alan J. O'Donnell, Santiago Iriarte, Mark J. Murphy, Colin G. Lyden, Gary Casey, Eoin Edward English
  • Patent number: 8848443
    Abstract: A semiconductor memory device includes at least one first semiconductor chip including a plurality of memory cells and a second semiconductor chip including a fuse circuit configured to repair defective cells among the memory cells of the at least one first semiconductor chip.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: September 30, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Saeng-Hwan Kim
  • Patent number: 8847350
    Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a metal-via fuse. The metal-via fuse and a programming transistor form a one-time programmable (OTP) memory cell. The metal-via fuse has a high resistance and can be programmed with a low programming voltage, which expands the programming window.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Chieh Lin, Kuoyuan (Peter) Hsu, Wei-Li Liao, Yun-Han Chen, Chen-Ming Hung
  • Patent number: 8841208
    Abstract: An electronic fuse structure including a first Mx metal comprising a conductive cap, an Mx+1 metal located above the Mx metal, wherein the Mx+1 metal does not comprise a conductive cap, and a via, wherein the via electrically connects the Mx metal to the Mx+1 metal in a vertical orientation.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Junjing Bao, Elbert Emin Huang, Yan Zun Li, Dan Moy
  • Patent number: 8836077
    Abstract: A semiconductor device according to an embodiment of the present invention includes fuse patterns spaced apart from each other by a predetermined distance over a first interlayer insulation film; a second interlayer insulation film disposed between the fuse patterns over the first interlayer insulation film; and a capping film pattern formed over the fuse patterns and the second interlayer insulation films, the capping film pattern including a slot exposing the second interlayer insulation film.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: September 16, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jeong Youl Kim, Ki Soo Choi
  • Patent number: 8829645
    Abstract: An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Deok-Kee Kim, Ahmet S Ozcan, Haining S Yang
  • Patent number: 8809142
    Abstract: An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Deok-Kee Kim, Ahmet S. Ozcan, Haining S. Yang
  • Patent number: 8809997
    Abstract: An e-fuse structure includes a first doped region and a second doped region formed in a substrate. The first doped region has a first conductivity type and the second doped region has a second conductivity type different from the first conductivity type. The first and second doped regions contact each other. A conductive pattern is disposed on the first and second doped regions and contacts the first and second doped regions. A first contact plug is disposed on the conductive pattern in an area corresponding to the first doped region, and a second contact plug is disposed on the conductive pattern in an area corresponding to the second doped region.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongsang Cho, Intaek Ku, Donghoon Kim, Ikhwan Kim, Choulhwan Oh
  • Patent number: 8767434
    Abstract: An e-fuse array circuit includes: an e-fuse transistor of a vertical gate type configured to have a gate for receiving a voltage of a program gate line and have one between a drain terminal and a source terminal floating; and a selection transistor of a buried gate type configured to have a gate for receiving a voltage of a word line gate line and electrically connect/disconnect the other one between the drain terminal and the source terminal with a bit line.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: July 1, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sungju Son, Youncheul Kim, Sungho Kim, Dongue Ko
  • Patent number: 8749020
    Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metal fuse in the dielectric layer; a dummy pattern adjacent the metal fuse; and a metal line in the dielectric layer, wherein a thickness of the metal fuse is substantially less than a thickness of the metal line.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: June 10, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Shin-Puu Jeng, Shih-Hsun Hsu
  • Patent number: 8742465
    Abstract: A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: June 3, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Takehiro Ueda
  • Patent number: 8735242
    Abstract: A method of forming a semiconductor device includes forming a field-effect transistor (FET), and forming a fuse which includes a graphene layer and is electrically connected to the FET.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventor: Wenjuan Zhu
  • Patent number: 8729663
    Abstract: On a silicon substrate 120 of a semiconductor device, a field oxide film 101 is provided. On the field oxide film 101, two fuses 104 are provided. Directly below the fuses 104 in the silicon substrate 120, an n-type well 102 is provided. Besides the n-type well 102, a p-type well 103 is provided in such a manner as to surround a region directly under the fuses 104 in the silicon substrate 120. A cover insulating film 108 is provided over the silicon substrate 120 and the field oxide film 101. A seal ring composed of a contact 106 and an interconnection 107 is embedded in the cover insulating film 108 so as to surround the fuses 104.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: May 20, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kiyotaka Miwa, Nayuta Kariya
  • Patent number: 8723290
    Abstract: The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: May 13, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-suk Shin, Andrew-Tae Kim, Hong-jae Shin
  • Patent number: 8724365
    Abstract: A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: May 13, 2014
    Assignee: International Business Machines Corporation
    Inventors: William R. Tonti, Wayne S. Berry, John A. Fifield, William H. Guthrie, Richard S. Kontra
  • Patent number: 8716831
    Abstract: An eFuse structure having a first metal layer serving as a fuse with a gate including an undoped polysilicon (poly), a second metal layer and a high-K dielectric layer all formed on a silicon substrate with a Shallow Trench Isolation formation, and a process of fabricating same are provided. The eFuse structure enables use of low amounts of current to blow a fuse thus allowing the use of a smaller MOSFET.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: May 6, 2014
    Assignee: Broadcom Corporation
    Inventors: Xiangdong Chen, Wei Xia
  • Patent number: 8716071
    Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kaushik Chanda, Lynne M. Gignac, Wai-Kin Li, Ping-Chuan Wang
  • Patent number: 8704228
    Abstract: An anti-fuse device includes a gate electrode on a semiconductor substrate, a gate insulating layer between the semiconductor substrate and the gate electrode, junction regions in the semiconductor substrate adjacent the gate electrode, and at least one anti-breakdown material layer between the junction regions, the gate insulating layer being between the gate electrode and the anti-breakdown material layer.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: April 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-song Ahn, Satoru Yamada, Young-jin Choi
  • Patent number: 8704333
    Abstract: Embodiments of a system with first means for forming a chamber adjacent to a component formed on a substrate and a single orifice between the chamber and a first surface of the first means that is opposite a second surface of the first means adjacent to the substrate and second means for enclosing the chamber on at least a portion of the first surface that encompasses the single orifice are disclosed.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: April 22, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Andrew Phillips, Jeremy H. Donaldson, Julie J. Cox, Mark H. MacKenzie, Christopher A. Leonard
  • Patent number: 8698275
    Abstract: An electronic circuit arrangement has a substrate which has at least one metallization layer. At least one electrical interconnect and/or at least one via are formed in the metallization layer such that the electrical interconnect and the via are in the form of an electrical fuse link. In addition, the substrate has electrical circuit components which are arranged in the circuit layer. The circuit components are electrically coupled to one another by means of the electrical interconnect and by means of a plurality of vias.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: April 15, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Andreas Rusch, Klaus Schrüfer
  • Patent number: 8692375
    Abstract: A structure and design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, William R. Tonti, Chih-Chao Yang
  • Patent number: 8686536
    Abstract: An embodiment is a fuse structure. In accordance with an embodiment, a fuse structure comprises an anode, a cathode, a fuse link interposed between the anode and the cathode, and cathode connectors coupled to the cathode. The cathode connectors are each equivalent to or larger than about two times a minimum feature size of a contact that couples to an active device.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shien-Yang Wu, Wei-Chan Kung
  • Publication number: 20140077334
    Abstract: An electronic fuse and method for forming the same. Embodiments of the invention include e-fuses having a first metallization level including a metal structure, a second metallization level above the first metallization level, a metal via in the second metallization level, an interface region where the metal via meets the first metallization level, and a damaged region at the interface region. Embodiments further include a method including providing a first metallization level including a metal structure, forming a capping layer on the first metallization level, forming an opening in the capping layer that exposes a portion of the metal structure; forming above the capping layer an adhesion layer contacting the metal structure, forming an insulating layer above the adhesion layer, etching the insulating layer and the adhesion layer to form a recess exposing the metal structure, and filling the fuse via recess to form a fuse via.
    Type: Application
    Filed: September 20, 2012
    Publication date: March 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jinjing Bao, Griselda Bonilla, Samuel S. Choi, Daniel C. Edelstein, Ronald G. Filippi, Naftali Eliahu Lustig, Andrew H. Simon
  • Publication number: 20140061851
    Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a metal-via fuse. The metal-via fuse and a programming transistor form a one-time programmable (OTP) memory cell. The metal-via fuse has a high resistance and can be programmed with a low programming voltage, which expands the programming window.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sung-Chieh LIN, Kuoyuan (Peter) HSU, Wei-Li LIAO, Yun-Han CHEN, Chen-Ming HUNG