Abstract: A method for manufacturing a semiconductor device includes: forming a trimming element inside or over a semiconductor substrate; forming an insulating film on the trimming element; forming, on the insulating film, a first wiring layer connected to one end of the trimming element via a first contact region penetrating the insulating film; forming, on the insulating film, a second wiring layer connected to another end of the trimming element via a second contact region penetrating the insulating film; trimming the trimming element; and examining an insulated state between the semiconductor substrate and either the first wiring layer or the second wiring layer after the trimming.

Abstract: Provided is a semiconductor device and corresponding method of fabricating the same. The semiconductor device comprises a plurality of bottom lines. One or more top vias are arranged on top of the plurality of bottom lines. One or more electronic fuses (eFuses) are also arranged on top of the plurality of bottom lines. Each eFuse of the one or more eFuses is a via having a smaller critical dimension that the one or more top vias. A plurality of top lines are arranged on top of the one or more top vias and the one or more eFuses.

Abstract: An anti-fuse unit includes: an anti-fuse device; a first selection transistor electrically connected with the anti-fuse device; and a second selection transistor electrically connected with the first selection transistor. Each of the anti-fuse device, the first selection transistor and the second selection transistor is provided with a gate oxide layer and a gate conductive layer, the gate oxide layer of the anti-fuse device, the gate oxide layer of the first selection transistor and the gate oxide layer of the second selection transistor have a same thickness, and the gate conductive layer of the anti-fuse device, the gate conductive layer of the first selection transistor and the gate conductive layer of the second selection transistor have a same thickness.

Abstract: Various fuse structures are disclosed herein that exhibit improved performance, such as reduced electro-migration. An exemplary fuse structure includes an anode, a cathode, and a fuse link extending between the anode and the cathode. A plurality of anode contacts are coupled to the anode, and a plurality of cathode contacts are coupled to the cathode. The plurality of cathode contacts are arranged symmetrically with respect to a centerline of the fuse link.

Abstract: A fuse structure includes first and second transistors where each of the first and the second transistors has a source terminal, a drain terminal, and a gate terminal; a first source/drain contact disposed on the source terminal of the first transistor; a second source/drain contact disposed on the drain terminal of the second transistor; an insulator disposed laterally between the first and the second source/drain contacts; a source/drain contact via disposed on the first source/drain contact; and a program line connected to the source/drain contact via, wherein a width of the insulator is configured such that a programming potential applied across the source/drain contact via and the drain terminal of the second transistor causes the insulator to break down.

Abstract: A device may include a substrate, and an interlevel dielectric arranged over the substrate. The interlevel dielectric may include a first interlevel dielectric layer in an interconnect level i, the first interlevel dielectric layer having a first interconnect and a second interconnect therein. A nitride block insulator may be arranged over the first interlevel dielectric layer and over the first interconnect and the second interconnect. An opening may be arranged in the nitride block insulator, the opening extending through the nitride block insulator to expose a surface of the first interconnect in the first interlevel dielectric layer. A contact plug may be arranged in the opening of the nitride block insulator. The contact plug at least lines the opening and prevents out-diffusion of conductive material from the first interconnect. A thin film of a passive component may be arranged over the nitride block insulator and over the contact plug.

Abstract: Provided are an electrical interconnection structure, an electronic apparatus and manufacturing methods therefor, which can provide a reliable electrical interconnection structure between the MEMS apparatus and an external circuit while sealing and encapsulating the MEMS device. The electrical interconnection structure includes: a bonding metal; a first dielectric layer and a second dielectric layer. The first dielectric layer includes a first through hole penetrating the first dielectric layer and exposing the bonding metal. The first through hole is filled with a first conductive material electrically connected to the bonding metal. The second dielectric layer includes a second through hole. An orthographic projection of second conductive material in the second through hole covers an orthographic projection of first conductive material in the first through hole onto the plane of the base.

Abstract: An integrated circuit includes a transistor that has an collector region, a base region laterally surrounded by the collector region, and an emitter region laterally surrounded by the base region. A silicide layer on the emitter region is laterally spaced apart from the base region by an unsilicided ring. The emitter region is laterally spaced apart from a base contact region that may be covered by a dielectric layer such as a gate oxide layer.

Abstract: A method for cutting off at least one portion, in particular a wafer, from a solid body is contemplated. The method includes: modifying the crystal lattice of the solid body by means of a modifier, wherein a number of modifications are produced to form a nonplanar, in particular convex, detachment region in the interior of the solid body, wherein the modifications are produced in accordance with predetermined parameters, wherein the predetermined parameters describe a relationship between a deformation of the portion and a defined further treatment of the portion, detaching the portion from the solid body.

Abstract: A metal fuse structure may be provided. The metal fuse structure may comprise a first fuse element and a second fuse element. The second fuse element may be adjacent to the first fuse element for a length L. The second fuse element may be spaced apart from first fuse element by a width W.

Abstract: A memory device is disclosed. The memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines, each of the word lines coupled to a corresponding row of the memory cells; a plurality of bit lines, each of the bit lines coupled to a corresponding column of the memory cells; and a plurality of second word lines, each of the second word lines coupled to a corresponding column of the memory cells.

Abstract: The present disclosure provides a semiconductor device with a fuse structure and an anti-fuse structure and a method for forming the semiconductor device. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a first electrode disposed over the first dielectric layer. The semiconductor device also includes a fuse link disposed over the first electrode, and a second electrode disposed over the fuse link. The semiconductor device further includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode. The first electrode, the fuse link, and the second electrode form a fuse structure, and the first electrode, the third electrode, and a portion of the second dielectric layer between the first electrode and the third electrode form an anti-fuse structure.

Abstract: The present disclosure provides a semiconductor device with a copper-manganese liner and a method for preparing the semiconductor device. The semiconductor device includes a first well region and a second well region disposed in a semiconductor substrate. The semiconductor device also includes a first dielectric layer disposed over the semiconductor substrate and covering the first well region and the second well region, and a gate structure disposed over the first dielectric layer and between the first well region and the second well region. The semiconductor device further includes a conductive structure disposed over and separated from the first well region by a portion of the first dielectric layer. The conductive feature includes a barrier layer and a conductive plug disposed over the barrier layer, and the barrier layer is made of copper-manganese (CuMn). The first well region, the conductive structure and the portion of the first dielectric layer form an anti-fuse structure.

Abstract: A display panel and a method for manufacturing a display panel that includes a front side and a back side, the display panel including a substrate having a plurality of electrical components provided on a front side of the substrate and integrated circuits connected to the plurality of electrical components, the integrated circuits being embedded in the substrate. A plurality of edge contacts is also provided along edges of the substrate, where the plurality of edge contacts is electrically connected with the integrated circuits. An electrically conductive layer covers at least a part of the front side of the substrate and surrounds the plurality of electrical components, where the electrically conductive layer does not physically contact the embedded integrated circuits and provides electromagnetic interference (EMI) shielding to different components of the display panel.

Abstract: The present disclosure provides a semiconductor device with a fuse structure and an anti-fuse structure and a method for forming the semiconductor device. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a first electrode disposed over the first dielectric layer. The semiconductor device also includes a fuse link disposed over the first electrode, and a second electrode disposed over the fuse link. The semiconductor device further includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode. The first electrode, the fuse link, and the second electrode form a fuse structure, and the first electrode, the third electrode, and a portion of the second dielectric layer between the first electrode and the third electrode form an anti-fuse structure.

Abstract: An electrically programmable fuse structure and a semiconductor device are disclosed. The electrically programmable fuse structure comprises a cathode, a fuse link and an anode, the fuse link connecting the cathode to the anode, the cathode connected to the fuse link at a junction, wherein the cathode comprises a plurality of conductive branches arranged to form a converging side and a diverging side, and the converging side of the cathode is connected to the junction so as to be connected to the fuse link.

Abstract: In the present disclosure, a semiconductor structure includes an Mx-1 layer including a first dielectric layer and first metal features, wherein the first metal features include a first set of first metal features in a first region and a second set of first metal features in a second region, wherein the first set has a first pattern density and the second set has a second pattern density being greater than the first pattern density. The structure further includes a Vx layer disposed over the Mx-1 layer, the Vx layer including first vias contacting the first set of the first metal features. The structure further includes an Mx layer disposed over the Vx layer, the Mx layer including a fuse element, wherein the fuse element has a first thickness in the first region less than a second thickness in the second region.

Abstract: The present disclosure provides a one-time programmable capacitive fuse bit, including an upper plate, the upper plate includes a plurality of fuses arranged side by side and spaced by an internal from each other, middle portions of two adjacent fuses are connected to each other; a connecting portion connected to the fuse is disposed above two ends and the middle portion of each of the plurality of fuses; the fuse bit further includes a lower plate corresponding to the two ends and the middle portion of the fuse, the lower plate is disposed below the fuse; the lower plate corresponding to the middle portion of the fuse is opposite to the connecting portion corresponding to the middle portion of the fuse; a hollow portion is disposed between the lower plate corresponding to the middle portion of the fuse and the lower plate corresponding to both ends of the fuse.

Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.

Abstract: A semiconductor integrated circuit includes: a semiconductor monocrystalline region; an insulating film provided on a main surface of the semiconductor monocrystalline region; a conductive layer having a rectangular shape provided on the insulating film and including at least a polycrystalline layer of p-type; electric-field relaxing layers having a lower specific resistivity than the conductive layer and each including a polycrystalline layer of n-type so as to be arranged on both sides of the conductive layer in a direction perpendicular to a current-flowing direction; a high-potential-side electrode in ohmic contact with the conductive layer at one end of the conductive layer in the current-flowing direction; and a low-potential-side electrode in ohmic contact with the conductive layer and the respective electric-field relaxing layers at another end of the conductive layer opposed to the one end in the current-flowing direction, and having a lower potential than the high-potential-side electrode.

Abstract: A memory component includes multiple fuses, a memory array having a multiple blocks, and control logic operatively coupled with the memory array and the plurality of fuses. The control logic is to receive an erase command associated with the memory array and attempt to erase, in response to receipt of the erase command, a block of the multiple blocks from the memory array. The control logic is further to detect a failure to completely erase the block. The control logic is further to receive a blow fuse command in response to the failure to completely erase the block. The control logic is to blow a fuse, of the multiple fuses, which is coupled with the block, to make the block of the multiple blocks inaccessible to the control logic.

Abstract: An apparatus includes a non-volatile storage circuit that includes a primary copy of a data value in a first storage location and a redundant copy of the data value in a second, different storage location. The data value includes one or more bits. The apparatus further includes an error detection circuit configured to retrieve contents of the first and second storage locations in response to a request for the data value. The error detection circuit is further configured to perform an error correction operation on the retrieved contents of the first and second storage locations to generate a data output responsive to the request, and to perform an error detection operation to generate an error signal that indicates whether the retrieved contents of the first and second storage locations are different.

Abstract: The present disclosure relates to the technical field of semiconductors, and in particular to a semiconductor chip, a semiconductor wafer and a method for manufacturing a semiconductor wafer. The semiconductor chip comprises: a substrate, devices provided on a side of the substrate, via holes running through the substrate, conductive material filled in the via holes and contacted with the devices, and a backside metal layer provided on the other side of the substrate away from the devices, the backside metal layer coming into contact with the conductive material so as to be electrically connected to the devices via the conductive material. The semiconductor chip, the semiconductor wafer and the method for manufacturing a semiconductor wafer of the present disclosure reduce the ground resistance and improve the heat dissipation of devices with via holes structure during the operation.

Abstract: A micro-fuse assembly includes a substrate, a number of thin-film micro-fuses on the substrate, and a topping wafer configured to sealingly engage to at least one of the substrate or the thin-film micro-fuses to define a cavity therebetween. The cavity is configured to encapsulate the thin-film micro-fuses within an inert environment sealed within the cavity. A method of encapsulating a micro-fuse assembly within an inert environment using a topping wafer is also disclosed.

Abstract: Provided is a semiconductor integrated circuit device including a fuse circuit whose area and cost are minimized by a simple circuit configuration. The fuse circuit includes a first fuse and a second fuse having substantially the same shape and different sheet resistances, which are connected in series between terminals with different potentials. In a state in which none of the fuses is cut, a potential of an output terminal is fixed to a potential of one of the terminals.

Abstract: An advanced e-Fuse structure is described. An e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a large grained copper structure and the fuse element is comprised of a fine grained copper structure.

Abstract: A structure of an e-Fuse device in a semiconductor device is described. The e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a large grained copper layer and an aspect ratio reducing layer, and the fuse element is comprised of a fine grained copper structure.

Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.

Abstract: In one aspect of the invention, a method for fabricating an e-Fuse device is described. A trench structure is provided. The trench structure includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions. The trench is provided in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The trench is filled with copper. An annealing step converts the copper to create a large grained copper structure in the anode and cathode regions and a fine grained copper structure in the fuse element. Another aspect of the invention is an e-Fuse device which includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions.

Abstract: A semiconductor device includes a substrate including at least two semiconductor chip regions and a scribe lane region disposed between the semiconductor chip regions. The semiconductor device additionally includes a first optical measurement pattern disposed on the substrate. The semiconductor device further includes a second optical measurement pattern disposed on an upper layer of the first optical measurement pattern, the second optical measurement pattern being spaced apart from the first optical measurement pattern. The semiconductor device additionally includes a three-dimensional (3D) shielding structure surrounding the first optical measurement pattern and including an electrically conductive material.

Abstract: A fuse includes a semiconductor layer having a dielectric material formed thereon. An epitaxially grown material is formed in a trench within the dielectric material. The epitaxially grown material includes a peak region. A fuse metal is formed over the peak region and extends along sidewalls of the trench and over the dielectric material outside the trench. Contacts are formed outside the trench connecting to fuse metal over the dielectric material.

Abstract: A semiconductor device comprises an active region including a core circuit forming region and a buffer forming region, and a fuse element forming region arranged on a corner of the active region and to be able to be electrically fused. It is possible to arrange the fuse element without forming the fuse in the core circuit forming region by arranging the fuse element forming region at the corner of the active region.

Abstract: A three-dimensionally (3d) confined conductor advantageously used as an electronic fuse and self-aligned methods of forming the same. By non-conformal deposition of a dielectric film over raised structures, a 3d confined tube, which may be sub-lithographic, is formed between the raised structures. Etching holes which intersect the 3d confined region and subsequent metal deposition fills the 3d confined region and forms contacts. When the raised structures are gates, the fuse element may be located at the middle of the line (i.e. in pre-metal dielectric). Other methods for creating the structure are also described.

Abstract: A semiconductor device includes a first insulating film formed above a semiconductor substrate, a fuse formed above the first insulating film, a second insulating film formed above the first insulating film and the fuse and including an opening reaching the fuse, and a third insulating film formed above the second insulating film and in the opening.

Abstract: A semiconductor device includes: an e-fuse gate, a floating pattern between the e-fuse gate and an e-fuse active portion, a blocking dielectric pattern between the floating pattern and the e-fuse gate, and an e-fuse dielectric layer between the floating pattern and the e-fuse active portion. The floating pattern includes a first portion between the e-fuse gate and the e-fuse active portion and a pair of second portions extended upward along both sidewalls of the e-fuse gate from both edges of the first portion.

Abstract: In various embodiments, the fuse is formed from silicide and on top of a fin of a fin structure. Because the fuse is formed on top of a fin, its width takes the width of the fin, which is very thin. Depending on implementations, the fuse is also formed using planar technology and includes a thin width. Because the width of the fuse is relatively thin, a predetermined current can reliably cause the fuse to be opened. Further, the fuse can be used with a transistor to form a memory cell used in memory arrays, and the transistor utilizes FinFET technology.

Abstract: An electronic circuit arrangement in accordance with some embodiments has a substrate, the substrate including: a plurality of metallization layers located one above the other; a single fuse-link via coupled between a first metallization layer and a second metallization layer of the plurality of metallization layers, wherein the single fuse-link via is in the form of an electrical fuse link preferentially programmable by applying a sufficiently large current to melt or degenerate the fuse link; a plurality of through-contact vias coupled in parallel between a third metallization layer and a fourth metallization layer of the plurality of metallization layers, wherein the through-contact vias form a through-contact between the third and fourth metallization layers; and electrical circuit components, arranged in a circuit layer, which are electrically coupled to one another by means of the single fuse-link via and by means of the plurality of through-contact vias.

Abstract: An improved electrical-fuse (e-fuse) device including a dielectric layer having a first top surface, two conductive features embedded in the dielectric layer and a fuse element. Each conductive feature has a second top surface and a metal cap directly on the second top surface. Each metal cap has a third top surface that is above the first top surface of the dielectric layer. The fuse element is on the third top surface of each metal cap and on the first top surface of the dielectric layer. A method of forming the e-fuse device is also provided.

Abstract: In a semiconductor integrated circuit device including fuse elements for performing laser trimming processing, a dummy fuse formed of a first polycrystalline Si film is formed between the fuse elements formed of a second polycrystalline Si film, and a nitride film is formed on the dummy fuse. In this manner, the step difference of an interlayer film caused by the presence and absence of the fuse element formed of the polycrystalline Si film is eliminated, to thereby prevent SOG films having moisture-absorption characteristics on an inner surface of a fuse opening region and on an internal element side from connecting to each other.

Abstract: Interposers for semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, an interposer includes a substrate, a contact pad disposed on the substrate, and a first through-via in the substrate coupled to the contact pad. A first fuse is coupled to the first through-via. A second through-via in the substrate is coupled to the contact pad, and a second fuse is coupled to the second through-via.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: Provided are electrical connection structures and methods of fabricating the same. The structures may include a substrate including a bonding pad region provided with a bonding pad and a fuse region provided with a fuse, an insulating layer provided on the substrate and including a bonding pad opening exposing the bonding pad and a fuse opening exposing the fuse region, a connection terminal provided in the bonding pad region and electrically connected to the bonding pad, and a protection layer provided on the insulating layer including a first protection layer provided within the bonding pad region and a second protection layer in the fuse opening.

Abstract: A preferred embodiment includes a method of manufacturing a fuse element that includes forming a polysilicon layer over a semiconductor structure, doping the polysilicon layer with carbon or nitrogen, depositing a metal over the polysilicon layer; and annealing the metal and polysilicon layer to form a silicide in an upper portion of the polysilicon layer.

Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

Abstract: A fuse of a semiconductor device and a method for forming the same are disclosed. The fuse includes a first metal line formed over a semiconductor substrate, a second metal line spaced apart from the first metal line, and a contact fuses formed of a metal contact coupled to the first metal line and the second metal line. Upper parts of the contact fuses overlap with each other, and lower parts are spaced apart from each other. Since the fuse is formed of a metal contact, fuse oxidation and fuse movement can be prevented. A conventional metal-contact fabrication process can be used, so that mass production of semiconductor devices is possible. In addition, the fuse region is reduced in size, reducing production costs.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: A semiconductor memory device includes at least one first semiconductor chip including a plurality of memory cells and a second semiconductor chip including a fuse circuit configured to repair defective cells among the memory cells of the at least one first semiconductor chip.

Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a metal-via fuse. The metal-via fuse and a programming transistor form a one-time programmable (OTP) memory cell. The metal-via fuse has a high resistance and can be programmed with a low programming voltage, which expands the programming window.

Abstract: An electronic fuse structure including a first Mx metal comprising a conductive cap, an Mx+1 metal located above the Mx metal, wherein the Mx+1 metal does not comprise a conductive cap, and a via, wherein the via electrically connects the Mx metal to the Mx+1 metal in a vertical orientation.

Abstract: A semiconductor device according to an embodiment of the present invention includes fuse patterns spaced apart from each other by a predetermined distance over a first interlayer insulation film; a second interlayer insulation film disposed between the fuse patterns over the first interlayer insulation film; and a capping film pattern formed over the fuse patterns and the second interlayer insulation films, the capping film pattern including a slot exposing the second interlayer insulation film.