Abstract: Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

Abstract: A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels.

Abstract: A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The central region of the second surface can be disposed between the first and second axes. The terminals can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic elements.

Abstract: A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The second surface can have a central region disposed between the first and second axes. Each microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. The terminals can be configured to carry all of the address signals transferred to the microelectronic package.

Abstract: A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.

Abstract: A semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. According to the present invention, even if a mechanical stress or a thermal stress is applied to an interconnection, a crack does not occur in the interconnection or the interconnection is not disconnected. Therefore, a reliability of the semiconductor package is improved.

Abstract: Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.

Abstract: In a semiconductor device, a lower multi-layered interconnect structure, an intermediate via-level insulating interlayer, and an upper multi-layered interconnect structure are stacked in this order in a region overlapped with a bonding pad in a plan view; upper interconnects and vias of the upper multi-layered interconnect structure are formed so as to be connected to the bonding pad in the pad placement region; the intermediate via-level insulating interlayer has no electro-conductive material layer, which connect the interconnects or vias in the upper multi-layered interconnect structure with interconnects or vias in the lower multi-layered interconnect structure, formed therein; and the ratio of area occupied by the vias in the via-level insulating interlayers contained in the lower multi-layered interconnect structure is smaller than the ratio of area occupied by the vias in the via-level insulating interlayers contained in the upper multi-layered interconnect structure.

Abstract: An integrated circuit arrangement includes a substrate with a multiplicity of integrated semiconductor components arranged therein, the substrate having a wiring interconnect near to the substrate, a middle wiring interconnect and a wiring interconnect remote from the substrate, which are arranged in this order at increasing distance from the substrate.

Abstract: A multi-path transistor includes an active region including a channel region and an impurity region. A gate is dielectrically separated from the channel region. A signal line is dielectrically separated from the impurity region. A conductive shield is disposed between, and dielectrically separated from, the signal line and the channel region. In some multi-path transistors, the channel region includes an extension-channel region under the conductive shield and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being in the extension-channel region to conduct substantially independent of a voltage on the signal line. In other multi-path transistors, the conductive shield is operably coupled to the impurity region and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being under the conductive shield to conduct substantially independent of a voltage on the signal line.

Abstract: A semiconductor memory device includes a cell array layer including a first and a second wiring, which cross each other; a third wiring formed on a first wiring layer below the cell array layer; a fourth wiring formed on a second wiring layer above the cell array layer; and a contact extending in a stacking direction for connecting the third and the fourth wiring, wherein the device further comprises a redundant wiring layer being formed between the first and the second wiring layer, the redundant wiring layer being formed with a redundant wiring having a portion extending in the same direction as at least one of the third and the fourth wiring, and the third and the redundant wiring, and the fourth and the redundant wiring being connected by a plurality of contacts arranged along the portion extending in the same direction as the third or the fourth wiring.

Abstract: A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.

Abstract: A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines indifferent cell array layers.

Abstract: A technology is provided for a packaging board adapted to mount a device capable of improving handleability and securing connection reliability. The packaging board includes: a pad electrode formed on a substrate; an insulating layer covering the substrate, having an opening at least in part in an area over the pad electrode; and a joint layer formed on the pad electrode inside the opening. The surface of the joint layer is lower than the top lip of the opening.

Abstract: A microelectronic unit includes a microelectronic element, e.g., an integrated circuit chip, having a semiconductor region of monocrystalline form. The semiconductor region has a front surface extending in a first direction, an active circuit element adjacent the front surface, a rear surface remote from the front surface, and a conductive via which extends towards the rear surface. The conductive via can be insulated from the semiconductor region by an inorganic dielectric layer. An opening can extend from the rear surface partially through a thickness of the semiconductor region, with the opening and the conductive via having respective widths in the first direction. The width of the opening may be greater than the width of the conductive via where the opening meets the conductive via.

Abstract: A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced.

Abstract: The invention provides a connection structure including: a first electro-conductive film that is formed on a substrate; an insulation film that is formed on the first electro-conductive film, an end surface of the insulation film facing in a direction in which an end surface of the first electro-conductive film faces; and a second electro-conductive film that extends from the upper surface of the insulation film to reach the end surface of the first electro-conductive film across the end surface of the insulation film, the second electro-conductive film being electrically connected to the first electro-conductive film via the end surface of the first electro-conductive film.

Abstract: An integrated circuit includes a substrate; a sealing element spanning a periphery of the substrate that forms a protective boundary for the substrate; a plurality of copper lines spanning the substrate in at least two distinct layers contained within the protective boundary; a first conducting element disposed outside the sealing element; and one or more second conducting elements connecting at least two of the copper lines and that spans the sealing element; wherein the conducting elements are substantially non-oxidizing metals that are resistant to oxidization and that connect the copper line to the first conducting element.

Abstract: A semiconductor device comprises an electrical contact designed to reduce a contact resistance. The electrical contact has a size that varies according to a length of a region where the contact is to be formed.

Abstract: An electronic component comprises a plurality of layers at least two of which comprise predominantly organic functional materials with improved through-plating through certain of the layers. The through-plating is formed in one embodiment by a disruption element on a first lower layer which results in a void in the subsequently applied layers, which void is filled with a material which may be conductive to form the through plating. In a second embodiment, the through plating is formed on the first lower layer prior to the subsequent application of the other layers, in the form of a free-standing truncated frusto-conical raised portion, and forms a disruption or non-welting element for the subsequently applied other layers, formed on the first lower layer and which are engaged with and surround the through plating after their application.

Abstract: A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower interconnections, wherein widths of the trenches are greater than widths of the via holes, and metal interconnections formed by burying metal thin films in the via holes and the trenches. Depths of the trenches are adjusted differently from each other depending on required resistances of the metal interconnections.

Abstract: An integrated circuit includes a contact structure with a buried first and a protruding second portion. The buried first portion is arranged in a cavity formed in a semiconductor structure and is in direct contact with the semiconductor structure. The protruding second portion is arranged above the main surface of the semiconductor structure and in direct contact with a conductive structure that is spaced apart from or separated from the main surface of the semiconductor structure. An insulator structure is arranged below and in direct contact with the contact structure.

Abstract: A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels.

Abstract: An integrated circuit contact system is provided including forming a contact plug in a dielectric and forming a first barrier layer in a trench in the dielectric and on the contact plug. Further, the system includes removing a portion of the first barrier layer from the bottom of the first barrier layer and depositing the portion of the first barrier layer on the sidewall of the first barrier layer, and forming a second barrier layer over the first barrier layer and filling a corner area of the trench.

Abstract: In order to improve the manufacturing yield of a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and attached to each other, the opening shape of each of conductive grooves (4A) formed in each chip (C2) obtained from a wafer (W2) is rectangular, and the number of the conductive grooves (4A) whose long-sides are directed in a Y direction and the number of the conductive grooves (4A) whose long-sides are directed in an X direction perpendicular to the Y direction are made to be approximately equal to each other number in the entire wafer (W2), whereby the film stress upon embedding of a conductive film into the interior of the conductive grooves is reduced, and generation of exfoliation and micro-cracks in the conductive film or warpage and cracks of the wafer (W2) are prevented.

Abstract: An electronic circuit with repetitive patterns formed by shadow mask vapor deposition includes a repetitive pattern of electronic circuit elements formed on a substrate. Each electronic circuit element includes the following elements in the desired order of deposition: a first semiconductor segment, a second semiconductor segment, a first metal segment, a second metal segment, a third metal segment, a fourth metal segment, a fifth metal segment, a sixth metal segment, a first insulator segment, a second insulator segment, a third insulator segment, a seventh metal segment, an eighth metal segment, a ninth metal segment and a tenth metal segment. All of the above segments may be deposited via a shadow mask deposition process. The electronic circuit element may be an element of an array of like electronic circuit elements.

Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed.

Abstract: In a semiconductor device according to an aspect of the invention, a direction in which a fourth metal interconnection layer located on a semiconductor layer is extended is orthogonal to a direction in which third interconnection layers ML30 and ML37 located on the fourth interconnection layer are extended. Thus, even in a case where a stress is applied from outside to bonding pads BP1 and BP2 located above, the stress is wholly dispersed by the third interconnection layers and the fourth interconnection layer which are laminated to intersect with each other, and stress concentration on a particular point can be relieved to restrain deterioration in semiconductor device strength to a minimum. Accordingly, it is possible to provide the semiconductor device having a structure in which productivity of the semiconductor device can be improved while the stress concentration applied from outside on the particular point of the bonding pad is relieved.

Abstract: With embodiments disclosed herein, the distribution of gated power is done using on-die layers without having to come back out and use package layers.

Abstract: There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions. In a semiconductor device wherein plural pads on a semiconductor element which are connected to function terminals on an external package are arranged in two lines along the periphery of the semiconductor element, an arrangement order of the plural pads on the semiconductor element is different from an arrangement order of the function terminals on the external package.

Abstract: A semiconductor die package is disclosed. The semiconductor die package comprises a leadframe structure with a die attach pad including a die attach surface, a folded edge structure and an opposite surface opposite to the die attach surface. A plurality of leads extending laterally away from the die attach pad. A semiconductor die comprising a first surface and a second surface is attached to the semiconductor die, and a molding material is around at least a portion of the leadframe structure and at least a portion of the semiconductor die. The opposite surface is exposed through the molding material and terminal ends of the leads do not extend past lateral edges of the molding material.

Abstract: An integrated circuit 78 is formed of multiple layers of circuits 14, 16 superimposed to produce stacks of circuit blocks 2, 4. Stack control circuitry 18, 20 is associated with the input and output signals from the circuit blocks to direct these to/from the currently active circuit block(s) as appropriate. The superimposed circuit blocks 2, 4 provide redundancy for each other, both for manufacturing defect resistance and for operational redundancy, such as providing multiple modular redundancy in safety critical environments.

Abstract: An integrated circuit includes: a substrate; and a bond pad array on the substrate. The bond pad array includes: a row of inner bond pads, each inner bond pad positioned with respect to a plurality of inner pad openings; a plurality of first inner metal layers respectively coupled to the inner bond pads for transmitting signals between the inner pads and an internal circuit, where at least one first inner metal layer has a width less than a width of a corresponding inner bond pad; a row of outer bond pads, staggered with respect to the row of inner bond pads; and a plurality of first outer metal layers respectively coupled to the outer bond pads for transmitting signals between the outer pads and the internal circuit, where at least one inner bond pad overlaps adjacent first outer metal layers.

Abstract: A first wire having sidewalls of an integrated circuit is tapered from the proximal end to the distal end to reduce width from the first width to the second width. A second wire, spaced apart from the first wire, the second wire has sidewalls. The first wire and the second wire are each horizontally disposed along side each other forming a part of a sidewall capacitor between facing sidewalls. The sidewall capacitor capacitance is progressively reduced responsive to the first wire taper.

Abstract: A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate through an insulation layer made of silicon oxide, silicon nitride or the like, a supporting plate bonded to a top surface of the semiconductor substrate to cover the pad electrode and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein an aperture of the via hole at a portion close to the pad electrode is larger than an aperture of the via hole at a portion close to the back surface of the semiconductor substrate.

Abstract: One or more embodiments of the present invention relate to structures obtained by methods (a) for growing a film by an intermixing growth process, or (b) by depositing a film, which film includes chalcogenides of copper and/or silver (but excluding oxides), such as, for example, copper sulfide (CuSX and/or Cu2SX, where 0.7?X?1.3; and X=1.0 for stoichiometric compounds).

Abstract: A semiconductor device comprising a plurality of first wirings provided in a predetermined layer on a substrate with being lined up, and formed to extend longer or contract shorter from one side toward the other side along a direction in which the first wirings are lined up, adjacent one-end portions of the first wirings being arranged in positions displaced from one another in a direction crossing at right angles the direction in which the first wirings are lined up.

Abstract: An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structures levels and elongated interconnects.

Abstract: An electronic device can include conductive regions. A void can extend between different portions of an insulating layer. Different openings can intersect the void. A liner layer can substantially block the void, substantially preventing subsequently forming an electrical leakage path along the void. In one aspect, a stressor layer can be deposited over the conductive regions prior to forming the insulating layer. The liner layer can be formed over the stressor layer within the different openings through the insulating layer. In another aspect, an etch-stop layer can be formed over a silicide layer prior to forming the insulating layer. After removing a portion of the liner layer, a portion of the etch-stop layer can be removed to expose the silicide layer within the different openings. In yet another aspect, a nitride layer can lie between a substrate and the insulating layer and include a section of the openings.

Abstract: A printed circuit board includes at least two conductive traces, each having a first portion and a second portion. The printed circuit board also includes a cross-over section that includes two electrically conductive portions, each connecting electrically to the first and second portions of a corresponding one of the conductive traces, such that the conductive traces in their first portions lie on opposite sides of each other as they do in their second portions.

Abstract: A semiconductor die includes a plurality of drivers and a plurality of bonding pads. Each driver is formed by a plurality of interconnected modules and has an associated bonding pad to which at least one of the modules of the driver is electrically connected. The modules of some of the drivers are positioned outside of the associated bonding pad toward a periphery of the die. The bonding pads may be arranged, for example, in a double- or triple-staggered pattern around the periphery of the die.

Abstract: An integrated circuit package comprises an integrated circuit die comprising N adjacent pads, where N is an integer greater than three. A substrate comprises a first pair of traces including first and second traces and a second pair of traces including third and fourth traces. The first, second, third and fourth traces include first ends spaced from the integrated circuit die and second ends adjacent to the integrated circuit die. The first and second pairs of traces carry differential signals. The third trace of the second pair of traces has a first polarity and the fourth trace of the second pair of traces has a second polarity. The third trace is located on one side of the fourth trace at the first end and is located on an opposite side of the fourth trace at the second end. N connections independently connect the second ends to N pads.

Abstract: An improved semiconductor device interconnect structure comprising a dielectric layer recessed with respect to the conductive interconnect features. This structure and method reduces embedded metallic residues from CMP scratches and metal cap applications and provides improved mechanical integrity at the capping layer/liner/dielectric interface.

Abstract: The present invention provides a quilt packaging system for microchip, a method for making such a quilt packaging system, microchips that may be used in a such a quilt packaging system, and methods for making such microchips.

Abstract: A semiconductor process is taught for performing electroless plating of copper overlying at least a portion of a layer comprising cobalt, nickel, or both cobalt and nickel. The cobalt and/or nickel comprising layer may be formed using electroless plating. For some embodiments, a tin layer is then formed overlying the copper. The tin layer may be formed using immersion plating or electroless plating. A micropad may comprise the cobalt and/or nickel comprising layer and the copper layer. In some embodiments, the micropad may also comprise the tin layer. In one embodiment, the micropad may be compressed at an elevated temperature to form a copper tin intermetallic compound which provides an interconnect between a plurality of semiconductor devices.

Abstract: A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower interconnections, wherein widths of the trenches are greater than widths of the via holes, and metal interconnections formed by burying metal thin films in the via holes and the trenches. Depths of the trenches are adjusted differently from each other depending on required resistances of the metal interconnections.

Abstract: A chip structure including a substrate, at least one chip bonding pad, a passivation layer, at least one compliant bump, and at least one redistribution conductive trace is provided. The substrate has an active surface whereon the chip bonding pad is disposed. The passivation layer is disposed on the active surface and exposes the chip bonding pad. The compliant bump has a top surface and a side surface. At least part of the compliant bump is disposed on the passivation layer. One end of the redistribution conductive trace is electrically connected to the chip bonding pad and the other end thereof covers part of the side surface and at least part of the top surface of the compliant bump. Therefore, the chip bonding pad of the chip structure can be electrically connected to the corresponding electrical contact of the carrier through the compliant bump and the redistribution conductive trace.

Abstract: An electronic device can include conductive regions. A void can extend between different portions of an insulating layer. Different openings can intersect the void. A liner layer can substantially block the void, substantially preventing subsequently forming an electrical leakage path along the void. In one aspect, a stressor layer can be deposited over the conductive regions prior to forming the insulating layer. The liner layer can be formed over the stressor layer within the different openings through the insulating layer. In another aspect, an etch-stop layer can be formed over a silicide layer prior to forming the insulating layer. After removing a portion of the liner layer, a portion of the etch-stop layer can be removed to expose the silicide layer within the different openings. In yet another aspect, a nitride layer can lie between a substrate and the insulating layer and include a section of the openings.

Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a dielectric layer; a chemical mechanical polish (CMP) stop layer on the dielectric layer; a conductive wiring in the dielectric layer; and a metal cap over the conductive wiring.

Abstract: An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with respective ones of the N plane-like metal layers, where M is an integer greater than one, wherein the first plane-like metal layer and the N plane-like metal layers are located in separate planes. A first drain region has a generally rectangular shape. First, second, third and fourth source regions have a generally rectangular shape and that are arranged adjacent to sides of the first drain region. The first drain region and the first, second, third and fourth source regions communicate with at least two of the N plane-like metal layers. A first gate region is arranged between the first, second, third and fourth source regions and the first drain region. First, second, third and fourth substrate contact regions are arranged adjacent to corners of the first drain region.