Geometry Or Layout Of Interconnection Structure (epo) Patents (Class 257/E23.151)
  • Patent number: 10256275
    Abstract: An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the source/drain regions of one of the select transistors. The local second vertical line is in conductive connection with the other source/drain region of the one select transistor. Individual memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between. Other aspects and implementations, including methods, are disclosed.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: April 9, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Zengtao T. Liu
  • Patent number: 9762269
    Abstract: An RF communications device may include a circuit board having a dielectric layer and conductive traces, one of the conductive traces defining a transmission line. The RF communications device may also include an RF transmitter carried by the circuit board and coupled to the transmission line, and RF switching circuits, each RF switching circuit including a substrate having a tapered proximal end coupled to the transmission line, and a distal end extending outwardly on the convex side of the transmission line. Each RF switching circuit may include a series diode, and a shunt diode coupled to the series diode, the series diode extending from the tapered proximal end and across an interior of the substrate.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: September 12, 2017
    Assignee: HARRIS CORPORATION
    Inventors: John McIntyre, Kevin Dell, Christopher David Mackey, John Paul Shoots
  • Patent number: 9762309
    Abstract: This invention aims to present a smart and dynamic power amplifier module that features both power combining and power sharing capabilities. The proposed flexible power amplifier (PA) module consists of a pre-processor, N PAs, and a post-processor. The pre-processor is an M-to-N wavefront (WF) multiplexer (muxer), while the post processor is a N-to-M WF de-multiplexer (demuxer), where N?M?2. Multiple independent signals can be concurrently amplified by a proposed multi-channel PA module with a fixed total power output, while individual signal channel outputs feature different power intensities with no signal couplings among the individual signals. In addition to basic configurations, some modules can be configured to feature both functions of parallel power amplifiers and also as M-to-M switches. Other programmable features include configurations of power combining and power redistribution functions with a prescribed amplitude and phase distributions, as well as high power PA with a linearizer.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: September 12, 2017
    Assignee: Spatial Digital Systems, Inc.
    Inventor: Donald C. D. Chang
  • Patent number: 9711480
    Abstract: A packaged integrated circuit for operating reliably at elevated temperatures is provided. The packaged integrated circuit includes a modified extracted die, which includes one or more extended bond pads, a package comprising a base and a lid, and a plurality of new bond wires. The modified extracted die is placed into a cavity of the base. After the modified extracted die is placed into the cavity, the plurality of new bond wires are bonded between the one or more extended bond pads of the modified extracted die and package leads of the package base or downbonds. After bonding the plurality of new bond wires, the lid is sealed to the base.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: July 18, 2017
    Assignee: Global Circuit Innovations Incorporated
    Inventor: Erick Merle Spory
  • Patent number: 9697320
    Abstract: Circuits and methods for a system on a chip having non-uniform channel spacings is provided. In an example, a chip is provided that includes a first functional block having a rectilinear shape, the first processing unit having on a side a plurality of channel spacings. A first channel spacing of the plurality of channel spacings is positioned in contact with the side and a second functional block. A second channel spacing of the plurality of channel spacings is positioned in contact with the side and the second functional block. The width of the second channel spacing is non-uniform with the width of the first channel spacing.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: July 4, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Sreedhar Gudala, Kumar Gopal Rao, Francis Page, Pak Kin Wong, Sunil Kumar
  • Patent number: 9270228
    Abstract: A technique for implementing an clock tree distribution network having a clock buffer and a plurality of LC tanks that each take into \consideration local capacitance distributions and conductor resistances. An AC-based sizing formulation is applied to the buffer and to the LC tanks so as to reduce the total buffer area. The technique is iterative and can be fully automated while also reducing clock distribution power consumption.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: February 23, 2016
    Assignee: The Regents of the University of California
    Inventor: Matthew Guthaus
  • Patent number: 9024431
    Abstract: A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 8975735
    Abstract: A redistribution board includes a first conductive layer including a redistribution structure for low voltage signals, a second conductive layer including a redistribution structure for high voltage signals, and a non-conductive layer. The second conductive layer is spaced apart from the first conductive layer by the non-conductive layer. The redistribution board further includes a conductive connector extending from a mounting surface of the redistribution board to the second conductive layer. The conductive connector is surrounded by a low voltage trace of the first conductive layer.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Höglauer
  • Patent number: 8958229
    Abstract: A nonvolatile memory device includes multiple variable resistive elements formed on a substrate; multiple bit lines formed on the variable resistive elements, extended in a first direction, and separated from each other by a first pitch; multiple circuit word lines formed on the multiple bit lines, extended in a second direction, and separated from each other by a second pitch; and multiple circuit word lines formed on the multiple bit lines, extended in the first direction, and separated from each other by a third pitch, wherein the third pitch of the multiple circuit word lines is larger than the first pitch of the multiple bit lines.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: February 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyun Park, Jae-Hee Oh, Sung-Won Kim
  • Patent number: 8952538
    Abstract: A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 10, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hirohisa Matsuki
  • Patent number: 8946905
    Abstract: An integrated circuit (IC) having a concentric arrangement of stacked vias is disclosed. The IC includes first and second pluralities of signal lines on first and second metal layers, respectively. The second metal layer is arranged between the first metal layer and a silicon layer. The IC also includes a via structure implemented in a predefined area, and connects each of the first and second pluralities of signal lines to circuitry in the silicon layer through respective first and second pluralities of vias. Each via of the first and second pluralities has a center point that extends along a vertical axis from its respective metal layer to the silicon layer. Centers of each of the second plurality of vias are closer to a perimeter of the predefined area than respective centers of any of the first plurality of vias.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: February 3, 2015
    Assignee: Oracle International Corporation
    Inventor: Robert P. Masleid
  • Patent number: 8928151
    Abstract: A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: January 6, 2015
    Assignee: Intel Corporation
    Inventors: Mihir K. Roy, Islam Salama, Yonggang Li
  • Patent number: 8907458
    Abstract: Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shom Ponoth, David V. Horak, Takeshi Nogami, Chih-Chao Yang
  • Patent number: 8878365
    Abstract: A semiconductor device, including: a semiconductor layer; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width; an interlayer dielectric formed above the first conductive layer and the second conductive layer; and an electrode pad formed above the interlayer dielectric. A connection section at which the first conductive layer and the second conductive layer are connected is disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad; and a reinforcing section is provided at the connection section.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: November 4, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki
  • Patent number: 8872303
    Abstract: A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wu-Te Weng, Ji-Shyang Nieh
  • Patent number: 8860225
    Abstract: Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: October 14, 2014
    Assignee: Infineon Technologies AG
    Inventors: Philipp Riess, Erdem Kaltalioglu, Hermann Wendt
  • Patent number: 8853793
    Abstract: A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes of the PMOS and NMOS transistors are formed by conductive features which extend in only a first parallel direction. The first and second p-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second p-type diffusion regions. The first and second n-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second n-type diffusion regions.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: October 7, 2014
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Jim Mali, Carole Lambert
  • Patent number: 8841774
    Abstract: A first wiring (1) has a bending portion (2), a first wiring region (1a) extending from the bending portion (2) in the X direction, and a second wiring region (1b) extending from the bending portion (2) in the Y direction. A via (3) is formed under the wiring (1). The via (3) is formed so as not to overlap with a region of the bending portion (2) in the first wiring region (1a). The length of the via (3) in the X direction (x) is longer than the length thereof in the Y direction (y) and both ends of the via (3) in the Y direction overlap with both ends of the first wiring region (1a) in the Y direction.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: September 23, 2014
    Assignee: Panasonic Corporation
    Inventors: Miwa Ichiryu, Hiroyuki Uehara, Hidetoshi Nishimura
  • Patent number: 8836135
    Abstract: A semiconductor device including: a semiconductor substrate; a plurality of interconnect layers disposed at different heights from the semiconductor substrate, each interconnect layer including an interconnection formed therein; and a via formed in a columnar shape extending in the stack direction of the interconnect layers, the via electrically connecting the interconnections of the different interconnect layers, the interconnections including an intermediate interconnection in contact with the via in the intermediate portion thereof, and the intermediate interconnection including a first type intermediate interconnection passing through the via in a direction perpendicular to the stack direction and in contact with the via on the top surface, bottom surface, and both side surfaces thereof.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirokazu Kikuchi
  • Patent number: 8829681
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: September 9, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8823173
    Abstract: A semiconductor device includes first and second wirings formed in a first wiring layer and extending parallel to an X direction, third and fourth wirings formed in a third wiring layer and extending parallel to a Y direction; fifth and sixth wirings formed in a second wiring layer positioned between the first and second wiring layers, a first contact conductor that connects the first wiring to the third wiring; and a second contact conductor that connects the second wiring to the fourth wiring. The first and second contact conductors are arranged in the X direction. Because the first and second contact conductors that connect wiring layers that are two or more layers apart are arranged in one direction, a prohibited area that is formed in the second wiring layer can be made narrower.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: September 2, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Koji Yasumori, Hisayuki Nagamine
  • Patent number: 8810036
    Abstract: In a semiconductor device, parallel first and second conductive lines having a unit width extend from a memory cell region into a connection region. A trim region in the connection region includes pads respectively connected to the first and second conductive lines but are separated by a width much greater than the unit width.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Min, Ki-Jeong Kim, Kyoung-Sub Shin, Dong-Hyun Kim
  • Patent number: 8796868
    Abstract: Apparatuses and methods for an improved semiconductor layout are described herein. Embodiments of the present invention provide a microelectronic device including a microelectronic die and one or more redistribution paths formed thereon for electrically interconnecting at least one bond pad with an exposed portion of the redistribution path. The redistribution paths, bond pads, and exposed portions may be configured to result in the device having a width narrowed by at least the width of the bond pads due to their absence on at least one edge.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: August 5, 2014
    Assignee: Marvell International Ltd.
    Inventors: Thomas Ngo, Shiann-Ming Liou
  • Patent number: 8791448
    Abstract: Semiconductor memory devices having strapping contacts are provided, the devices include cell regions and strapping regions between adjacent cell regions in a first direction. Active patterns, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines, extending in the second direction, intersect the active patterns and first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-in Kim, Jae-hee Oh, Jun-hyok Kong, Sung-ho Eun, Yong-tae Oh
  • Patent number: 8791569
    Abstract: A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each of which has a rectangular shape extending in a first direction. A second wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a second copper wiring layer adjacent to the first copper wiring layer, each of which has a rectangular shape extending in a second direction orthogonal to the first direction. The region occupied by the first wiring pattern and that occupied by the second wiring pattern are arranged such that they at least overlap. The first wiring pattern and the second wiring pattern are electrically connected so as to have the same electric potential.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: July 29, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Jun Maede
  • Patent number: 8779597
    Abstract: An apparatus includes a semiconductor chip with a base support structure having a surface and an opposed surface. At least one device structure extends from the surface of the base support structure. A first conductive region is coupled to the base support structure. At least a portion of the first conductive region extends below the opposed surface.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: July 15, 2014
    Inventor: Sang-Yun Lee
  • Patent number: 8772838
    Abstract: A semiconductor layout structure includes multiple active blocks which are disposed on a substrate, parallel with one another and extending along a first direction, multiple first shallow trench isolations which are disposed on a substrate, parallel with one another and respectively disposed on the multiple active blocks, and multiple second shallow trench isolations which are disposed on a substrate, cutting through multiple active blocks and extending along a second direction. The first direction has an angle about 1 degree to about 53 degrees to the second direction.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 8, 2014
    Assignee: Inotera Memories, Inc.
    Inventors: Tzung-Han Lee, Chung-Yuan Lee
  • Patent number: 8759983
    Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on the connecting member, the wiring including a first region and a second region, the first region contacting with a portion of an upper surface of the connecting member, and the second region located on the first region and having a width greater than that of the first region; and a second insulating film formed on the first insulating film so as to contact with at least a portion of the first region of the wiring and with a bottom surface of the second region.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Akihiro Kajita, Kazuyuki Higashi
  • Patent number: 8735995
    Abstract: A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 27, 2014
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Jim Mali, Carole Lambert
  • Patent number: 8737443
    Abstract: A nitride semiconductor laser device is provided herein that is reduced in capacitance to have a better response. The nitride semiconductor laser device includes: an active layer; an upper cladding layer which is stacked above the active layer; a low dielectric constant insulating film which is stacked above the upper cladding layer; and a pad electrode which is stacked above the low dielectric constant insulating film.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: May 27, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kentaro Tani, Yoshihiko Tani, Toshiyuki Kawakami
  • Patent number: 8716770
    Abstract: A solid-state imaging apparatus comprises: a plurality of photoelectric conversion elements for converting light into an electric charge, including a first photoelectric conversion element; a first semiconductor region from which the electric charge is transferred from a first photoelectric conversion element; an amplifying MOS transistor including a gate electrode connected to the first semiconductor region to amplify the potential of the first semiconductor region; an insulating film; a metal wiring layer above the insulating film; a local interconnect of a first conductor, formed in the insulating film, for connecting the gate electrode of the amplifying MOS transistor to the first semiconductor region not through the metal wiring layer; a second semiconductor region, different from the first semiconductor region; and a second conductor for connecting the second semiconductor region to at least a part of the metal wiring layer.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: May 6, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takashi Okagawa
  • Patent number: 8710660
    Abstract: A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tien-I Bao
  • Patent number: 8704355
    Abstract: A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: April 22, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Masaya Kawano
  • Patent number: 8698204
    Abstract: In one embodiment, a semiconductor memory device includes a substrate, and device regions in the substrate to extend in a first direction. The device further includes select gates on the substrate to extend in a second direction, and a contact region provided between the select gates and including contact plugs on the respective device regions. The contact region includes partial regions, in each of which N contact plugs are disposed on N successive device regions to be arranged on a straight line being non-parallel to the first and second directions, where N is an integer of 2 or more. The contact region includes the partial regions of at least two types whose values of N are different. Further, each of the contact plugs has a planar shape of an ellipse, and is arranged so that a major axis of the ellipse is tilted with respect to the first direction.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: April 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kutsukake, Yoshiko Kato
  • Publication number: 20140097541
    Abstract: Substantially simultaneous plasma etching of polysilicon and oxide layers in multilayer lines in semiconductors allows for enhanced critical dimensions and aspect ratios of the multilayer lines. Increasing multilayer line aspect ratios may be possible, allowing for increased efficiency, greater storage capacity, and smaller critical dimensions in semiconductor technologies.
    Type: Application
    Filed: October 10, 2012
    Publication date: April 10, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Lo Yueh LIN
  • Patent number: 8692380
    Abstract: A method of manufacture of an integrated circuit system includes: forming reticle data; detecting a sub-geometry, a singularity, or a combination thereof in the reticle data; applying a unit cell, a patch cell, or a combination thereof for removing the sub-geometry, the singularity, or the combination thereof from the reticle data; and fabricating an integrated circuit from the reticle data.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: April 8, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Soon Yoeng Tan, Huey Ming Chong, Byoung-Il Choi, Soo Muay Goh
  • Patent number: 8686486
    Abstract: It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Toshihiko Saito
  • Patent number: 8674501
    Abstract: A semiconductor integrated circuit device includes plural circuit units each having plural logic circuits; and plural power terminals supplying power source from outside to the semiconductor integrated circuit device, in which the plural circuit units each having plural logic circuits have common packaging design with each other, and lengths in a vertical direction and a lateral direction of the circuit units each having plural logic circuits are equal to an even multiple of a distance between the power terminals adjacent to each other.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: March 18, 2014
    Assignee: Fujitsu Limited
    Inventor: Yasuhide Sosogi
  • Patent number: 8674460
    Abstract: In accordance with the disclosure, a MEMS substrate is provided that includes: a central planar portion configured to support a MEMS device; and a first electrical pad coplanar with the central planar portion, the first pad being connected to the central planar portion through a first flexure, wherein the first flexure is configured to substantially mechanically isolate the first electrical pad from the central planar portion.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: March 18, 2014
    Assignee: DigitalOptics Corporation MEMS
    Inventors: Roman C. Gutierrez, Robert J. Calvet
  • Patent number: 8674512
    Abstract: Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Randal W. Chance, William T. Rericha
  • Patent number: 8669555
    Abstract: Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.
    Type: Grant
    Filed: November 23, 2012
    Date of Patent: March 11, 2014
    Assignee: Panasonic Corporation
    Inventors: Masao Takahashi, Koji Takemura, Toshihiko Sakashita, Tadaaki Mimura
  • Patent number: 8648471
    Abstract: A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines in different cell array layers.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: February 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Tabata, Eiji Ito, Hirofumi Inoue
  • Patent number: 8633520
    Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate; device isolation regions formed in the substrate; an impurity region formed in a region of the substrate between every two adjacent ones of the device isolation regions; a gate electrode formed on the substrate; first and second interlayer insulating films sequentially formed on the substrate; a metal interlayer insulating film formed on the second interlayer insulating film and comprising metal wiring layers; a first contact plug electrically connecting each of the metal wiring layers and the impurity region; and a second contact plug electrically connecting each of the metal wiring layers and the gate electrode, wherein the first contact plug is formed in the first and second interlayer insulating films, and the second contact plug is formed in the second interlayer insulating film.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: January 21, 2014
    Assignees: Samsung Electronics Co., Ltd., Infineon Technologies AG, International Business Machines Corporation
    Inventors: Dong-Hee Yu, Bong-Seok Suh, Yoon-Hae Kim, O Sung Kwon, Oh-Jung Kwon
  • Patent number: 8633544
    Abstract: A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: January 21, 2014
    Assignee: Halo LSI, Inc.
    Inventors: Kimihiro Satoh, Tomoko Ogura, Ki-Tae Park, Nori Ogura, Yoshitaka Baba
  • Patent number: 8624395
    Abstract: An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Conal E. Murray, Ping-Chuan Wang, Chih-Chao Yang
  • Patent number: 8623700
    Abstract: The present invention provides a quilt packaging system for microchip, a method for making such a quilt packaging system, microchips that may be used in a such a quilt packaging system, and methods for making such microchips.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: January 7, 2014
    Assignee: University of Notre Dame du Lac
    Inventors: Gary H. Bernstein, Patrick Fay, Wolfgang Porod, Qing Liu
  • Patent number: 8618608
    Abstract: A lateral silicon controlled rectifier structure includes a P-type substrate; an N-well region in the P-type substrate; a first P+ doped region in the N-well region and being connected to an anode; a P-well region in the P-type substrate and bordering upon the N-well region; a first N+ doped region formed in the P-well region and separated from the first P+ doped region by a spacing distance, the first N+ doped region being connected to a cathode; and a gate structure overlying a portion of the P-type substrate between the first P+ doped region and the first N+ doped region.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: December 31, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Ta-Cheng Lin, Te-Chang Wu
  • Patent number: 8618678
    Abstract: A chip structure and a chip package structure are disclosed herein. The chip structure includes a chip and a bump. The chip includes at least one pad. The bump is disposed on a bounding region of the pad. The shape of the bump is triangular pillar or trapezoidal pillar. A surface area of connection between the bump and the pad is less than or equal to the bounding region. Therefore, the material usage and the cost of the bump can be reduced. In addition, such shape of the bump has directional characteristic so that it is easy to perform the chip testing via the identifiable pads, and perform the package process of bonding the chip to a circuit board or any carriers.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: December 31, 2013
    Assignee: Himax Technologies Limited
    Inventor: Chiu-Shun Lin
  • Patent number: 8618580
    Abstract: An integrated circuit chip includes a semiconductor substrate, a first circuit in or coupled to the semiconductor substrate, a second circuit device in or coupled the semiconductor substrate, a dielectric structure coupled the semiconductor substrate, a first interconnecting structure in the dielectric structure, a first pad connected to the first node of the voltage regulator through the first interconnecting structure, a second interconnecting structure in the dielectric structure, a second pad connected to the first node of the analog circuit through the second interconnecting structure, a passivation layer coupled the dielectric structure, wherein multiple openings in the passivation layer exposes the first and second pads, and a third interconnecting structure coupled the passivation layer and coupled the first and second pads.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: December 31, 2013
    Assignee: Megit Acquisition Corp.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee, Chien-Kang Chou
  • Publication number: 20130341796
    Abstract: A semiconductor device has external, exposed electrical contacts at an device active face and a semiconductor die, which has internal, electrical contacts at a die active face. The exposed contacts are offset from the internal contacts laterally of the device active face. A redistribution layer includes a layer of insulating material and redistribution interconnectors within the insulating material, the interconnectors connecting with the exposed contacts. A set of conductors connect the internal contacts and the interconnectors. The conductors have oblong, tear drop shaped cross-sections extending laterally of the die active face beyond the respective internal contacts, and contact the interconnectors at positions spaced further apart than the internal contacts. The redistribution layer may be prefabricated using less costly manufacturing techniques such as lamination.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 26, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Navas Khan Oratti Kalandar, Chee Seng Foong, Norazham Mohd Sukemi, Kesvakumar V.C. Muniandy