Containing Conductive Organic Materials Or Pastes, E.g., Conductive Adhesives, Inks (epo) Patents (Class 257/E23.166)
  • Patent number: 8847349
    Abstract: An integrated circuit (IC) package including an IC die and a conductive ink printed circuit layer electrically connected to the IC die.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 30, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Matthew David Romig, Lance Cole Wright, Leslie Edward Stark, Frank Stepniak, Screenivasan K. Koduri
  • Patent number: 8828787
    Abstract: Processes for making a thin film solar cell on a substrate by providing a substrate coated with an electrical contact layer, depositing an ink onto the contact layer of the substrate, wherein the ink contains an alkali ion source compound suspended or dissolved in a carrier along with photovoltaic absorber precursor compounds, and heating the substrate. The alkali ion source compound can be MalkMB(ER)4 or Malk(ER). The processes can be used for CIS or CIGS.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: September 9, 2014
    Assignee: Precursor Energetics, Inc.
    Inventors: Kyle L. Fujdala, Zhongliang Zhu, David Padowitz, Paul R. Markoff Johnson, Wayne A. Chomitz, Matthew C. Kuchta
  • Patent number: 8816512
    Abstract: Disclosed is a light emitting device module including a package body, a first lead frame and a second lead frame provided on the package body, a light emitting device electrically connected to the first lead frame and the second lead frame, a first pad and a second pad respectively formed on the lower surfaces of the first lead frame and the second lead frame, and a third pad formed on the lower surface of the package body, wherein at least one of the first pad, the second pad and the third pad includes a plurality of sub-pads.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: August 26, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Eui Geun Jun
  • Patent number: 8710662
    Abstract: A light-reflective anisotropic conductive paste is used as an anisotropic conductive paste when a light-emitting device is produced by flip-chip mounting a light-emitting element such as a light-emitting diode element (LED) on a wiring board. The light-reflective anisotropic conductive paste includes light-reflective insulating particles, in order to improve light emission efficiency without providing, in the LED, a light-reflecting layer that causes an increase in manufacturing cost. With the light-reflective anisotropic conductive paste, a reduction in bonding strength of the light-emitting element to the wiring board in a high-temperature environment can be suppressed, and a reduction in conduction reliability after a TCT can also be suppressed. In the light-reflective anisotropic conductive paste, conductive particles and the light-reflective insulating particles are dispersed in a thermosetting resin composition.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: April 29, 2014
    Assignee: Sony Corporation & Information Device Corporation
    Inventors: Hideaki Umakoshi, Hidetsugu Namiki, Akira Ishigami, Masaharu Aoki, Shiyuki Kanisawa, Yoshihisa Shinya
  • Patent number: 8697485
    Abstract: Printed electronic device comprising a substrate onto at least one surface of which has been applied a layer of an electrically conductive ink comprising functionalized graphene sheets and at least one binder. A method of preparing printed electronic devices is further disclosed.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: April 15, 2014
    Assignees: Vorbeck Materials Corporation, The Trustees of Princeton University
    Inventors: John M. Crain, John S. Lettow, Ilhan A. Aksay, Sibel A. Korkut, Katherine S. Chiang, Chuan-Hua Chen, Robert K. Prud'Homme
  • Patent number: 8674521
    Abstract: A semiconductor device package is provided. The semiconductor device package includes a package body; a plurality of electrodes including a first electrode on the package body; a paste member on the first electrode and including inorganic fillers and metal powder; and a semiconductor device die-bonded on the paste member, wherein a die-bonding region of the first electrode includes a paste groove having a predetermined depth and the paste member is formed in the paste groove.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: March 18, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Choong Youl Kim
  • Patent number: 8384231
    Abstract: In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer.
    Type: Grant
    Filed: January 18, 2010
    Date of Patent: February 26, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, Michael J. Seddon
  • Patent number: 8203218
    Abstract: A semiconductor device package is provided. The semiconductor device package includes a package body, a plurality of electrodes, a paste member, and a semiconductor device. The electrodes includes a first electrode disposed on the package body. The paste member is disposed on the first electrode and includes at least one of an inorganic filler and metal powder. The semiconductor device is die-bonded on the paste member.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: June 19, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventor: Choong Youl Kim
  • Patent number: 8193643
    Abstract: According to an aspect of the present invention, there is provided a semiconductor device, including a semiconductor chip including a semiconductor element, a first electrode of the semiconductor chip being configured on a first surface of the semiconductor element, a second electrode of the semiconductor element being configured on a second surface opposed to the first surface of the semiconductor chip, an encapsulating material encapsulating the semiconductor chip, a first hole and a second hole being configured in the encapsulating material, a portion of the first electrode and a portion of the second electrode being exposed, a first conductive material being connected to the first surface of the semiconductor chip via the first hole, a second conductive material being connected to the second surface of the semiconductor chip via the second hole, and a plating film covering five surfaces of the first conductive material other than one surface contacting with the encapsulating material and five surfaces of
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: June 5, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Tojo, Tomoyuki Kitani, Tomohiro Iguchi, Takahiro Aizawa, Hideo Nishiuchi, Masako Fukumitsu
  • Patent number: 7625814
    Abstract: A method of filling a conductive material in a three dimensional integration feature formed on a surface of a wafer is disclosed. The feature is optionally lined with dielectric and/or adhesion/barrier layers and then filled with a liquid mixture containing conductive precursor, such as a solution with dissolved ruthenium precursor or a dispersion or suspension with conductive particles (e.g., gold, silver, copper), and the substrate is rotated while the mixture is on its surface. Then, the liquid carrier is dried from the feature, leaving a conductive layer in the feature. These two steps are optionally repeated until the feature is filled up with the conductor. Then, the conductor is annealed in the feature, thereby forming a dense conductive plug in the feature.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: December 1, 2009
    Assignee: ASM Nutool, Inc.
    Inventors: Ismail Emesh, Chantal J. Arena, Bulent M. Basol
  • Patent number: 7554196
    Abstract: A plastic package and to a semiconductor component including such a plastic package, as well as to a method for its production is disclosed. In one embodiment, the plastic package includes plastic outer faces, which include lower outer contact faces on a lower side of the plastic package and upper outer contact faces on an upper side, which are connected together via outer conductor tracks. The conductor tracks include conduction paths which are formed on exposed conducting deposits in the plastic package.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: June 30, 2009
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Bachmaier, Michael Bauer, Robert-Christian Hagen
  • Patent number: 7485561
    Abstract: A method of filling a conductive material in a three dimensional integration structure feature formed on a surface of a wafer is disclosed. The feature is filled with a dispersion containing a plurality of conductive particles and a solvent. Then, the solvent is removed from the feature, leaving the plurality of conductive particles in the feature. These two steps are repeated until the feature is filled up with the conductive particles. Then, the conductive particles are annealed in the feature, thereby forming a dense conductive plug in the feature.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: February 3, 2009
    Assignee: ASM NuTool, Inc.
    Inventor: Bulent M. Basol
  • Patent number: 7456504
    Abstract: Improved methods and apparatus are provided for the handling and testing of semiconductor devices. One embodiment comprises a die carrier for one or more semiconductor dice having very fine pitch electrical I/O (input/output) elements. The semiconductor dice are temporarily attached to the die carrier in singulated form to enable testing the dice with conventional contact technology. The die carrier may include a flex circuit base substrate and a rigid support frame. Further embodiments comprise materials and methods for attaching the semiconductor dice to the die carrier and for providing a temporary electrical connection with the semiconductor dice during testing. Exemplary materials for providing the temporary electrical connection may comprise a conductive film or tape, a conductive or conductor-filled epoxy, resin or RTV adhesive-based materials, a water-soluble material impregnated with a conductive filler or non-reflowed solder paste.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: November 25, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Steven L. Hamren, Daniel P. Cram
  • Patent number: 7384862
    Abstract: It is an object of the present invention to alleviate unevenness due to an opening for making a contact with the lower layer even when the opening has a large diameter (1 ?m or more). Thus, it is a further object of the invention to reduce defects caused by the unevenness due to the contact hole. It is a feature of the invention to form a wiring by filling the contact hole with conductive fine particles. The conductive fine particles can be easily dispersed into a wiring material by using conductive fine particles having high wettability with the wiring material, thereby making a contact. Thus, planarization of a contact hole can be achieved without performing a reflow process. Further, more planarity can be obtained by performing a reflow process in addition, and the reliability is improved accordingly.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: June 10, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7321133
    Abstract: Regio-regular polythiophenes used in diodes which are not light emitting or photovoltaic. High quality, processable thin film polymer films can be made. The thin film can have a thickness of about 50 nm to about one micron, and the conductive thin film can be applied by spin casting, drop casting, screening, ink-jetting, transfer or roll coating. The polythiophenes can be homopolymers or copolymers. The regio-regular poly(3-substitutedthiophene) can be derivatized so that the 3-substituent is an alkyl, aryl, or alkyl/aryl moiety with a heteroatom substitution in either the ?- or beta-position of the 3-substituent.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: January 22, 2008
    Assignee: Plextronics, Inc.
    Inventors: Shawn P. Williams, Troy D. Hammond, Darin W. Laird
  • Patent number: 7282779
    Abstract: A device includes banks formed on a substrate, a conducting film formed by droplet ejection onto a predetermined pattern formation region in a groove between the banks, and a second conductive film formed by droplet ejection disposed outside the pattern formation region and electrically separated from the conductive film.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: October 16, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Hironori Hasei
  • Publication number: 20070048897
    Abstract: A method and apparatus for depositing conductive paste in openings of a circuitized substrate such as a multilayered printed circuit board to produce effective conductive thru-holes capable of being electrically coupled to selected conductive layers of the substrate. The invention comprises using vacuum to draw from the underside of the substrate while substantially simultaneously applying the paste onto the substrate's opposing surface. One example of means for accomplishing such paste application is a squeegee, and in one embodiment, two such squeegees may be used. A porous member is used to engage the substrate's undersurface during the vacuum draw, this member being positioned atop a base vacuum member through which the vacuum is drawn.
    Type: Application
    Filed: September 1, 2005
    Publication date: March 1, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Norman Card, John Lauffer
  • Patent number: 7126228
    Abstract: Improved methods and apparatus are provided for the handling and testing of semiconductor devices. One embodiment comprises a die carrier for one or more semiconductor dice having very fine pitch electrical I/O (input/output) elements. The semiconductor dice are temporarily attached to the die carrier in singulated form to enable testing the dice with conventional contact technology. The die carrier may include a flex circuit base substrate and a rigid support frame. Further embodiments comprise materials and methods for attaching the semiconductor dice to the die carrier and for providing a temporary electrical connection with the semiconductor dice during testing. Exemplary materials for providing the temporary electrical connection may comprise a conductive film or tape, a conductive or conductor-filled epoxy, resin or RTV adhesive-based materials, a water-soluble material impregnated with a conductive filler or non-reflowed solder paste.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: October 24, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Steven L. Hamren, Daniel P. Cram