Conductive Materials (epo) Patents (Class 257/E23.155)
  • Patent number: 9006895
    Abstract: A metal cap is formed on an exposed upper surface of a conductive structure that is embedded within an interconnect dielectric material. During the formation of the metal cap, metallic residues simultaneously form on an exposed upper surface of the interconnect dielectric material. A thermal nitridization process or plasma nitridation process is then performed which partially or completely converts the metallic residues into nitrided metallic residues. During the nitridization process, a surface region of the interconnect dielectric material and a surface region of the metal cap also become nitrided.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Stephan A. Cohen
  • Patent number: 8962479
    Abstract: A metal cap is formed on an exposed upper surface of a conductive structure that is embedded within an interconnect dielectric material. During the formation of the metal cap, metallic residues simultaneously form on an exposed upper surface of the interconnect dielectric material. A thermal nitridization process or plasma nitridation process is then performed which partially or completely converts the metallic residues into nitrided metallic residues. During the nitridization process, a surface region of the interconnect dielectric material and a surface region of the metal cap also become nitrided.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Stephan A. Cohen
  • Patent number: 8922016
    Abstract: A method for producing a composite material, associated composite material and associated semiconductor circuit arrangements is disclosed. A plurality of first electrically conducting material particles are applied to a carrier substrate and a second electrically conducting material is galvanically deposited on a surface of the first material particles in such a way that the second material mechanically and electrically bonds the plurality of first material particles to one another.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: December 30, 2014
    Assignee: Infineon Technologies AG
    Inventors: Oliver Hellmund, Daniel Kraft, Friedrich Kroener, Francisco Javier Santos Rodriguez, Carsten Von Koblinski
  • Patent number: 8907482
    Abstract: A system may include a package defining a cavity and an integrated circuit (IC) disposed within the cavity. The package may include a first electrically conductive package contact and a second electrically conductive package contact. The IC may include a first electrically conductive IC contact and a second electrically conductive IC contact. The system also may include a wire bond extending between and electrically connecting the first electrically conductive package contact and the first electrically conductive IC contact. The system further may include an electrically conductive adhesive extending between and electrically connecting the second electrically conductive package contact and the second electrically conductive IC contact. Use of wire bonds and electrically conductive adhesive may increase an interconnect density between the IC and the package, while not requiring an increase in size of the IC or a decrease in pitch between wire bonds.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: December 9, 2014
    Assignee: Honeywell International Inc.
    Inventor: David Scheid
  • Patent number: 8860147
    Abstract: One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: October 14, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Amitava Chatterjee, Howard Tigelaar, Victor Sutcliffe
  • Patent number: 8786091
    Abstract: A semiconductor apparatus with a penetrating electrode having a high aspect ratio is manufactured with a low-temperature process. In one embodiment a first electrode 3 and a second electrode 6 of a semiconductor substrate 1 that are provided at the front and rear surface sides, respectively, are electrically connected by a conductive object 7 filled in a contact hole 4 and an extended portion 6a of the second electrode 6 extends to the contact hole 4. Even though the contact hole 4 has a high aspect ratio, film formation using the low-temperature process is enabled by using the conductive object 7, instead of forming the second electrode 6 on a bottom portion of the contact hole 4.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: July 22, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tadayoshi Muta
  • Patent number: 8749058
    Abstract: The semiconductor device includes an interlayer insulating film, a wiring provided in the interlayer insulating film, and a SiN film provided over the interlayer insulating film and over the wiring. The peak positions of Si—N bonds of the SiN film, which are measured by FTIR, are within the range of 845 cm?1 to 860 cm?1. This makes it possible to inhibit current leakage in a silicon nitride film, which is a barrier insulating film for preventing the diffusion of wiring metal.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Usami, Hideaki Tsuchiya, Yukio Miura, Tomoyuki Nakamura, Koichi Ohto, Chikako Ohto, Shinji Yokogawa
  • Patent number: 8729702
    Abstract: A trench is opened in a dielectric layer. The trench is then lined with a barrier layer and a metal seed layer. The metal seed layer is non-uniformly doped and exhibits a vertical doping gradient varying as a function of trench depth. The lined trench is then filled with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the non-uniformly doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: May 20, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Chengyu Niu, Andrew Simon, Keith Kwong Hon Wong, Yun-Yu Wang
  • Publication number: 20140019716
    Abstract: Techniques are disclosed for forming a directly plateable diffusion barrier within an interconnect structure to prevent diffusion of interconnect fill metal into surrounding dielectric material and lower metal layers. The barrier can be used in back-end interconnect metallization processes and, in an embodiment, renders a seed layer unnecessary. In accordance with various example embodiments, the barrier can be implemented, for instance, as: (1) a single layer of ruthenium silicide (RuSix) or ruthenium silicide nitride (RuSixNy); (2) a bi-layer of Ru/RuSix, RuSix/Ru, Ru/RuSixNy, or RuSixNy/Ru; or (3) a tri-layer of Ru/RuSix/Ru or Ru/RuSixNy/Ru. In some embodiments, Si and/or N concentrations can be adjusted to alter the barrier's degree of diffusion protection, receptiveness to the fill metal, and/or electrical conductivity.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 16, 2014
    Inventor: Christopher J. Jezewski
  • Publication number: 20130299985
    Abstract: Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Various protocols can be employed during processing to avoid cross-contamination between copper-plated and non-copper-plated wafers. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.
    Type: Application
    Filed: May 8, 2012
    Publication date: November 14, 2013
    Applicant: SKYWORKS SOLUTIONS, INC.
    Inventor: Hong Shen
  • Patent number: 8569887
    Abstract: A copper interconnect line formed on a passivation layer is protected by a copper-containing material layer including a group III element, a group IV element, a group V element or combinations thereof.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: October 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Yi-Wen Wu, Chung-Shi Liu
  • Publication number: 20130256830
    Abstract: Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John E. Barth, JR., Herbert L. Ho, Babar A. Khan, Kirk D. Peterson
  • Publication number: 20130221527
    Abstract: An interconnect structure including a metallic cap that covers 80 to 99% of the entire surface of an underlying conductive metal feature is provided utilizing a metal reflow process. Laterally extending portions of the conductive metal feature are located on vertical edges of the metallic cap, and each of the laterally extending portions of the conductive metal feature has an uppermost surface that is coplanar with an uppermost surface of the metallic cap.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 29, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Chao-Kun Hu
  • Patent number: 8486767
    Abstract: An interconnect structure in a semiconductor device may be formed to include a number of segments. Each segment may include a first metal. A barrier structure may be located between the plurality of segments to enable the interconnect structure to avoid electromigration problems.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: July 16, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jun Zhai, Fei Wang
  • Publication number: 20130140563
    Abstract: A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Fu Kao, Cheng-Lin Huang, Jing-Cheng Lin
  • Publication number: 20130119547
    Abstract: An integrated circuit device includes a substrate through which a first through-hole extends, and an interlayer insulating film on the substrate, the interlayer insulating film having a second through-hole communicating with the first through-hole. A Through-Silicon Via (TSV) structure is provided in the first through-hole and the second through-hole. The TSV structure extends to pass through the substrate and the interlayer insulating film. The TSV structure comprises a first through-electrode portion having a top surface located in the first through-hole, and a second through-electrode portion having a bottom surface contacting with the top surface of the first through-electrode portion and extending from the bottom surface to at least the second through-hole. Related fabrication methods are also described.
    Type: Application
    Filed: September 5, 2012
    Publication date: May 16, 2013
    Inventors: Su-kyoung Kim, Gil-heyun Choi, Byung-Iyul Park, Kwang-jin Moon, Kun-sang Park, Dong-chan Lim, Do-sun Lee
  • Publication number: 20130119545
    Abstract: A semiconductor device and a method for forming the same are disclosed, which can protect a polysilicon layer of a bit line contact plug even when a critical dimension (CD) of the bit line is reduced by a fabrication change, thereby preventing defective resistivity caused by a damaged bit line contact plug from being generated. The semiconductor device includes one or more interlayer insulation film patterns formed over a semiconductor substrate, a bit line contact plug formed over the semiconductor substrate between the interlayer insulation films, and located below a top part of the interlayer insulation film pattern, and a bit line formed over the bit line contact plug.
    Type: Application
    Filed: January 10, 2012
    Publication date: May 16, 2013
    Applicant: Hynix Semiconductor Inc.
    Inventor: Un Hee LEE
  • Publication number: 20130105978
    Abstract: A silicon submount for a light emitting diode (LED) including a silicon base, a first insulating layer, a first electrode, a second electrode, and a reflective layer is provided. The silicon base has an upper surface and a lower surface, and a recess is disposed at the upper surface. The first insulating layer covers the upper surface and the lower surface of the silicon base. The first electrode and the second electrode are disposed on the first insulating layer on a bottom of the recess. The reflective layer is disposed on the first insulating layer on a sidewall of the recess. The first electrode, the second electrode, and the reflective layer are separated from one another and formed by the same material.
    Type: Application
    Filed: December 26, 2011
    Publication date: May 2, 2013
    Applicant: EPISIL TECHNOLOGIES INC.
    Inventor: Chih-Lung Hung
  • Publication number: 20130093093
    Abstract: A semiconductor device includes a substrate having a plurality of contact surfaces, an interlayer dielectric layer formed over the substrate and having a first open portion which exposes a part of the contact surfaces and a second open portion which exposes the other contact surfaces, a storage node contact (SNC) plug filling the first open portion, and a damascene structure filing the second open portion and including a bit line, a spacer formed on both sidewalls of the bit line, a capping layer formed over the bit line and the spacer, and an air gap formed between the bit line and the spacer. The bit line includes a conductive material of which the volume is contracted by a heat treatment to form the air gap.
    Type: Application
    Filed: December 28, 2011
    Publication date: April 18, 2013
    Inventor: Nam-Yeal LEE
  • Patent number: 8421246
    Abstract: A joint structure joins an electronic element 12 included in an electronic component to an electrode 14 included in that electronic component. The joint structure includes a solder layer, which contains 0.2 to 6% by weight of copper, 0.02 to 0.2% by weight of germanium and 93.8 to 99.78% by weight of bismuth, a nickel layer provided between the solder layer and the electrode, and a barrier layer provided between the nickel layer and the solder layer. Here, the barrier layer is formed so as to have an average thickness of from 0.5 to 4.5 ?m after the electronic element and the electrode are joined by the solder layer.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: April 16, 2013
    Assignee: Panasonic Corporation
    Inventors: Akio Furusawa, Shigeaki Sakatani, Taichi Nakamura, Takahiro Matsuo
  • Publication number: 20120326311
    Abstract: Alternative methods of fabricating an interconnect structure in which an enhanced diffusion barrier including an in-situ formed metal nitride liner formed between an interconnect dielectric material and an overlying metal diffusion barrier liner are provided. In one embodiment, the method includes forming at least one opening into an interconnect dielectric material. A nitrogen enriched dielectric surface layer is formed within exposed surfaces of the interconnect dielectric material utilizing thermal nitridation. A metal diffusion barrier liner is formed on the nitrogen enriched dielectric surface. During and/or after the formation of the metal diffusion barrier liner, a metal nitride liner forms in-situ in a lower region of the metal diffusion barrier liner. A conductive material is then formed on the metal diffusion barrier liner.
    Type: Application
    Filed: June 21, 2011
    Publication date: December 27, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Daniel C. Edelstein, Steven E. Molis
  • Patent number: 8329502
    Abstract: Method of applying a conformal coating to a highly structured substrate and devices made by the disclosed methods are disclosed. An example method includes the deposition of a substantially contiguous layer of a material upon a highly structured surface within a deposition process chamber. The highly structured surface may be associated with a substrate or another layer deposited on a substrate. The method includes depositing a material having an amorphous structure on the highly structured surface at a deposition pressure of equal to or less than about 3 mTorr. The method may also include removing a portion of the amorphous material deposited on selected surfaces and depositing additional amorphous material on the highly structured surface.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: December 11, 2012
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: David S. Ginley, John Perkins, Joseph Berry, Thomas Gennett
  • Publication number: 20120306081
    Abstract: According to one embodiment, a semiconductor device includes an interconnect provided on a first interlayer insulating film covering a semiconductor substrate in which an element is formed, a cap layer provided on the upper surface of the interconnect, and a barrier film provided between the interconnect and a second interlayer insulating film covering the interconnect. The interconnect includes a high-melting-point conductive layer, and the width of the interconnect is smaller than the width of the cap layer. The barrier film includes a compound of a contained element in the high-melting-point conductive layer.
    Type: Application
    Filed: March 22, 2012
    Publication date: December 6, 2012
    Inventors: Takeshi ISHIZAKI, Atsuko Sakata, Junichi Wada, Masahiko Hasunuma
  • Publication number: 20120292770
    Abstract: A device for preventing corrosion on sensors and a method of fabricating the same is disclosed, wherein the device comprises an insulation layer and an adhesion layer covering a metallization layer of a silicon sensor with a corrosion resistant layer located over the adhesion layer.
    Type: Application
    Filed: May 19, 2011
    Publication date: November 22, 2012
    Applicant: General Electric Company
    Inventors: Qiang Wang, Keith Matthew Jackson, Naresh Venkata Mantravadi
  • Publication number: 20120292773
    Abstract: A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.
    Type: Application
    Filed: May 18, 2011
    Publication date: November 22, 2012
    Applicant: Infineon Technologies AG
    Inventors: Khalil Hosseini, Hans-Joachim Schulze
  • Publication number: 20120273951
    Abstract: A contact structure for interconnecting a first substrate to an indium interconnect structure on a second substrate. The contact structure comprises a diffusive layer and a non-oxidizing layer, with a thickness of less than approximately 150 nm, positioned on the diffusive layer for alignment with the indium interconnect.
    Type: Application
    Filed: September 13, 2011
    Publication date: November 1, 2012
    Applicant: RAYTHEON COMPANY
    Inventors: Jonathan Getty, Andreas Hampp, Aaron M. Ramirez, Scott S. Miller
  • Patent number: 8294202
    Abstract: A semiconductor device structure, for improving the metal gate leakage within the semiconductor device. A structure for a metal gate electrode for a n-type Field Effect Transistor includes a capping layer; a first metal layer comprising Ti and Al over the capping layer; a metal oxide layer over the first metal layer; a barrier layer over the metal oxide layer; and a second metal layer over the barrier layer.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: October 23, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko Jangjian, Szu-An Wu, Sheng-Wen Chen
  • Patent number: 8278757
    Abstract: Printed electronic device comprising a substrate onto at least one surface of which has been applied a layer of an electrically conductive ink comprising functionalized graphene sheets and at least one binder. A method of preparing printed electronic devices is further disclosed.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: October 2, 2012
    Assignees: Vorbeck Materials Corporation, The Trustees of Princeton University
    Inventors: John M. Crain, John S. Lettow, Ilhan A. Aksay, Sibel A. Korkut, Katherine S. Chiang, Chuan-hua Chen, Robert K. Prud'Homme
  • Publication number: 20120228775
    Abstract: The present invention provides a method of fabricating an airgap-containing interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene airgap-containing low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating.
    Type: Application
    Filed: May 17, 2012
    Publication date: September 13, 2012
    Applicant: International Business Machines Corporation
    Inventor: Qinghuang Lin
  • Patent number: 8258628
    Abstract: An integrated circuit arrangement includes a substrate with a multiplicity of integrated semiconductor components arranged therein, the substrate having a wiring interconnect near to the substrate, a middle wiring interconnect and a wiring interconnect remote from the substrate, which are arranged in this order at increasing distance from the substrate.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: September 4, 2012
    Assignee: Infineon Technologies AG
    Inventors: Martina Hommel, Heinrich Koerner, Markus Schwerd, Martin Seck
  • Publication number: 20120199976
    Abstract: An interconnect structure including a lower interconnect level with a first dielectric layer having a first conductive material embedded therein; a dielectric capping layer located on the first dielectric layer and some portions of the first conductive material; an upper interconnect level including a second dielectric layer having at least one via opening filled with a second conductive material and at least one overlying line opening filled with the second conductive material disposed therein, wherein the at least one via opening is in contact with the first conductive material in the lower interconnect level by a via gouging feature; a dielectric liner on sidewalls of the at least one via opening; and a first diffusion barrier layer on sidewalls and a bottom of both the at least one via opening and the at least one overlying line opening. A method of forming the interconnect structure is also provided.
    Type: Application
    Filed: April 17, 2012
    Publication date: August 9, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Chao-Kun Hu
  • Publication number: 20120193696
    Abstract: In order to achieve the reduction of contact resistance by forming a metal silicide layer with a sufficient thickness in an interface between a polycrystalline silicon plug and an upper conductive plug, the polycrystalline silicon plug contains germanium, which is ion-implanted before forming the metal silicide layer.
    Type: Application
    Filed: January 25, 2012
    Publication date: August 2, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Yoichi FUKUSHIMA
  • Publication number: 20120181693
    Abstract: A semiconductor device may include an upper interconnection on a substrate and an anti-reflection pattern disposed on the upper interconnection. The anti-reflection pattern may include a compound including a metal, carbon and nitrogen.
    Type: Application
    Filed: September 23, 2011
    Publication date: July 19, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeeyong Kim, Jong-Hyun Park, Jin-Kyu Kang, Joonhee Lee
  • Publication number: 20120181694
    Abstract: The semiconductor device includes an interlayer insulating film, a wiring provided in the interlayer insulating film, and a SiN film provided over the interlayer insulating film and over the wiring. The peak positions of Si—N bonds of the SiN film, which are measured by FTIR, are within the range of 845 cm?1 to 860 cm?1. This makes it possible to inhibit current leakage in a silicon nitride film, which is a barrier insulating film for preventing the diffusion of wiring metal.
    Type: Application
    Filed: December 13, 2011
    Publication date: July 19, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Tatsuya Usami, Hideaki Tsuchiya, Yukio Miura, Tomoyuki Nakamura, Koichi Ohto, Chikako Ohto, Shinji Yokogawa
  • Publication number: 20120168949
    Abstract: A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.
    Type: Application
    Filed: March 13, 2012
    Publication date: July 5, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Kazuyoshi MAEKAWA, Kenichi Mori
  • Publication number: 20120153477
    Abstract: Methods for plating metal over features of a semiconductor wafer and devices that can be formed by these methods are disclosed. One such method includes forming a barrier layer over the substrate using electroless plating and forming a copper layer over the barrier layer. In some implementations, the semiconductor wafer is a GaAs wafer. Alternatively or additionally, the feature over which metal is plated can be a through-wafer via. In some implementations, a seed layer over the barrier layer can be formed using electroless plating.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 21, 2012
    Applicant: SKYWORKS SOLUTIONS, INC.
    Inventor: Hong Shen
  • Publication number: 20120153329
    Abstract: A wafer substrate bonding structure may be provided that includes: a first substrate; and a conductive thin film which is disposed on the first substrate and includes a resin and conductive corpuscles included in the resin.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 21, 2012
    Inventor: Bum Chul Cho
  • Publication number: 20120133044
    Abstract: According to one embodiment, a via and trench are formed in a semiconductor structure. The via and the trench are suitable for having a metal-based wire placed therein by damascene, dual damascene, plating and other suitable techniques. The via is etched into a dielectric layer of a semiconductor structure comprising a base cap layer, the dielectric layer formed over the base cap layer, and a hardmask formed over the dielectric layer. The via is filled with a sacrifice material, where the sacrifice material contains a metal or a metal compound, where the sacrifice material additionally forms a sacrifice layer over the hardmask layer. The sacrifice material placed in the via does not contain a material or film containing a Si—O bond. The sacrifice material is used as a support for a photomask that is placed over the sacrifice layer, where the photomask is developed to have a trench pattern formed therein.
    Type: Application
    Filed: November 30, 2010
    Publication date: May 31, 2012
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Yoshihiro Uozumi
  • Publication number: 20120119302
    Abstract: An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer. An interconnect is present within the via opening. A metal semiconductor alloy contact is present in the semiconductor substrate. The metal semiconductor alloy contact has a perimeter defined by a convex curvature relative to a centerline of the via opening. The endpoints for the convex curvature that defines the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening, a sidewall of the interconnect and an upper surface of the semiconductor substrate.
    Type: Application
    Filed: November 11, 2010
    Publication date: May 17, 2012
    Applicant: International Business Machines Corporation
    Inventors: Chengwen Pei, Jeffrey B. Johnson, Zhengwen Li, Jian Yu
  • Publication number: 20120098134
    Abstract: When connecting with a conventional Zn/Al/Zn cladding material, thickness of a connecting part needs to be less than double an existing high-lead solder (about 100 ?m) in order to make heat resistance in the connecting part at least equivalent to a level of the existing solder. Moreover, thickness of an Al layer needs to make as thick as possible in order to fully exhibit stress relaxation performance of the Al layer. Provided is a semiconductor device including a semiconductor element, a frame, and a connecting part which connects the semiconductor element and the frame to each other, in which an interface between the connecting part and the semiconductor element and an interface between the connecting part and the frame respectively have the area of Al oxide film which is more than 0% and less than 5% of entire area of the respective interfaces.
    Type: Application
    Filed: August 30, 2010
    Publication date: April 26, 2012
    Inventors: Masahide Okamoto, Osamu Ikeda, Yuki Murasato
  • Publication number: 20120091586
    Abstract: Method of applying a conformal coating to a highly structured substrate and devices made by the disclosed methods are disclosed. An example method includes the deposition of a substantially contiguous layer of a material upon a highly structured surface within a deposition process chamber. The highly structured surface may be associated with a substrate or another layer deposited on a substrate. The method includes depositing a material having an amorphous structure on the highly structured surface at a deposition pressure of equal to or less than about 3 mTorr. The method may also include removing a portion of the amorphous material deposited on selected surfaces and depositing additional amorphous material on the highly structured surface.
    Type: Application
    Filed: October 14, 2010
    Publication date: April 19, 2012
    Applicant: ALLIANCE FOR SUSTAINABLE ENERGY, LLC
    Inventors: David S. Ginley, John Perkins, Joseph Berry, Thomas Gennett
  • Publication number: 20120080794
    Abstract: The invention relates to a method for producing a metallization for at least one contact pad and a semiconductor wafer having metallization for at least one contact pad. The invention relates to a metallization (and a semiconductor wafer having corresponding metallization) and to a method for the production thereof that first of all can be produced by means of physical gas phase separation (dry separation) and secondly ensures sufficient adhesion of a lot bump.
    Type: Application
    Filed: March 18, 2010
    Publication date: April 5, 2012
    Applicant: FORSCHUNGSVERBUND BERLIN E.V.
    Inventors: Victor Sidorov, Rimma Zhytnytska, Joachim Wuerfl
  • Publication number: 20120080790
    Abstract: Apparatus and methods for uniform metal plating onto a semiconductor wafer, such as GaAs wafer, are disclosed. One such apparatus can include an anode and a showerhead body. The anode can include an anode post and a showerhead anode plate. The showerhead anode plate can include holes sized to dispense a particular plating solution, such as plating solution that includes gold, onto a wafer. The showerhead body can be coupled to the anode post and the showerhead anode plate. The showerhead body can be configured to create a seal sufficient to substantially prevent a reduction of pressure in the plating solution flowing from the anode post to holes of the showerhead anode plate.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 5, 2012
    Applicant: Skyworks Solutions, Inc.
    Inventors: Jens A. Riege, Heather L. Knoedler, Shiban K. Tiku
  • Publication number: 20120074572
    Abstract: One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.
    Type: Application
    Filed: September 28, 2010
    Publication date: March 29, 2012
    Inventors: Thomas FISCHER, Juergen FOERSTER, Werner ROBL, Andreas STUECKJUERGEN
  • Publication number: 20120068342
    Abstract: The present disclosure relates to the field of fabricating microelectronic devices, wherein a conductive adhesive is used as a temporary microelectronic wafer bonding adhesive to prevent damage to microelectronic devices resulting from electrical charge build-up on the microelectronic devices during the formation of through-silicon vias.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 22, 2012
    Inventor: Kevin J. Lee
  • Publication number: 20120061839
    Abstract: During the fabrication of sophisticated metallization systems of semiconductor devices, material deterioration of conductive cap layers may be significantly reduced by providing a noble metal on exposed surface areas after the patterning of the corresponding via openings. Hence, well-established wet chemical etch chemistries may be used while not unduly contributing to process complexity.
    Type: Application
    Filed: November 16, 2011
    Publication date: March 15, 2012
    Inventors: Volker Kahlert, Christof Streck
  • Publication number: 20120061836
    Abstract: One example embodiment includes a method for applying a transparent conducting oxide. The method includes providing a solution, where the solution includes a solvent, a zinc precursor and an yttrium precursor. The method also includes spraying the solution on a heated substrate, where the heated substrate turns the solution into an yttrium-doped zinc oxide film. The method further includes annealing the film on the substrate in a controlled environment.
    Type: Application
    Filed: September 15, 2010
    Publication date: March 15, 2012
    Applicant: TAO COMPANIES LLC
    Inventors: Lilly Q. Guo, Meng Tao, Kunhee Han
  • Publication number: 20110304047
    Abstract: A method for producing a composite material, associated composite material and associated semiconductor circuit arrangements is disclosed. A plurality of first electrically conducting material particles are applied to a carrier substrate and a second electrically conducting material is galvanically deposited on a surface of the first material particles in such a way that the second material mechanically and electrically bonds the plurality of first material particles to one another.
    Type: Application
    Filed: August 25, 2011
    Publication date: December 15, 2011
    Applicant: Infineon Technologies AG
    Inventors: Oliver HELLMUND, Daniel KRAFT, Friedrich KROENER, Francisco Javier SANTOS RODRIGUEZ, Carsten VON KOBLINSKI
  • Patent number: 8076778
    Abstract: A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: December 13, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuo Liang Wei, Hsu Sheng Yu, Hong-Ji Lee
  • Publication number: 20110241130
    Abstract: A semiconductor device includes a blocking structure between a metal layer and at least one underlying layer. The blocking structure has a first layer configured for preventing diffusion of metal from the metal layer into the at least one underlying layer, and a second layer configured for enhancing electrical performance of the semiconductor device.
    Type: Application
    Filed: April 2, 2010
    Publication date: October 6, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bor-Wen CHAN, Hsueh Wen Tsau