Including Internal Interconnections, E.g., Cross-under Constructions (epo) Patents (Class 257/E23.168)
  • Patent number: 9013031
    Abstract: A semiconductor package includes a lower package including a lower semiconductor chip on a lower package substrate, an upper package on the lower package, and a heat interface material between the lower package and the upper package. The upper package includes an upper semiconductor chip on an upper package substrate including a center portion adjacent to the lower semiconductor chip and an edge portion. The heat interface material is in contact with a top surface of the lower semiconductor chip and the upper package substrate. The upper package substrate includes a heat diffusion via penetrating the center portion and an interconnection via penetrating the edge portion. The interconnection via is spaced apart from the heat diffusion via.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yunhyeok Im, Jichul Kim, Kyol Park, Seongho Shin
  • Patent number: 9006904
    Abstract: An electronic package includes a substrate wafer with an interconnect network. A first chip is fixed to a front of the substrate, connected to the interconnect network and encapsulated by a body. A second chip is placed on a back side of the substrate wafer and connected to the interconnect network by back-side connection elements interposed between the back side of the substrate and a front side of the second chip. Front-side connection elements are placed on the front side of the substrate and connected to the interconnect network. The connection elements extend beyond the frontal face of the body. The package may be mounted on a board with an interposed thermally conductive material.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: April 14, 2015
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Dominique Marais, Jacques Chavade, Rémi Brechignac, Eric Saugier, Romain Coffy, Luc Petit
  • Patent number: 8987913
    Abstract: Disclosed herein is a deformable network structure, which includes a first device portion, a second device portion and at least one connector interconnecting between the first device portion and the second device portion. Moreover, the second device portion can be electrically connected to the first device portion through one of the connectors. The first and second device portions respectively have a first and a second center. Each of the connectors may be deformable from an initial state to a final state, such that a first distance between the first and second centers in the final state varies by at least 10% of a second distance between the first and second centers in the initial state.
    Type: Grant
    Filed: May 27, 2013
    Date of Patent: March 24, 2015
    Assignee: MonoLithe Semiconductor Inc.
    Inventors: Kevin T. Y. Huang, Hsiao-Huey Huang
  • Patent number: 8987128
    Abstract: An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Marc Tarabbia, Chinh Nguyen, David Doman, Juhan Kim, Xiang Qi, Suresh Venkatesan
  • Patent number: 8975761
    Abstract: A display apparatus and an organic display apparatus are disclosed. In one aspect, the display apparatus includes a display substrate divided into a display region for displaying an image via a plurality of pixels for emitting light and a non-display region around the display region. It includes a pad unit formed on the non-display region. It also includes a fan-out unit for connecting the display region and the pad unit. It further includes a plurality of line groups sequentially formed, wherein each line group includes a first fan-out line, a second fan-out line insulated from the first fan-out line by a first insulating layer, and a third fan-out line insulated from the second fan-out line by a second insulating layer, and wherein the third fan-out line at least partially overlaps with at least one of the first and second fan-out lines.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 10, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Young-Bae Jung
  • Patent number: 8969866
    Abstract: Provided is a structure to obtain a reliable electrical contact through a narrow contact hole formed in an insulating layer, which is required in the miniaturization of a semiconductor device. An exemplified structure includes a thin film transistor comprising: a lower electrode over and in contact with a semiconductor layer, the lower electrode comprising a metal or a metal compound; an insulating layer over the lower electrode, the insulating layer having a contact hole reaching the lower electrode; a conductive silicon whisker grown from a surface of the lower electrode; and an upper electrode over the insulating layer and in contact with the conductive silicon whisker. The ability of the conductive silicon whisker grown from the lower electrode to ohmically contact with the lower and upper electrodes leads to a reliable electrical contact between the thin film transistor and a wiring.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomokazu Yokoi, Kensuke Yoshizumi
  • Patent number: 8970048
    Abstract: A higher aspect ratio for upper level metal interconnects is described for use in higher frequency circuits. Because the skin effect reduces the effective cross-sectional area of conductors at higher frequencies, various approaches are described to reduce the effective RC delay in interconnects.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: March 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiro Inohara
  • Patent number: 8952521
    Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: February 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Maciej Wojnowski, Walter Hartner, Ottmar Geitner, Gottfried Beer, Klaus Pressel, Mehran Pour Mousavi
  • Patent number: 8866292
    Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A first chip is disposed in the substrate. The first chip includes a plurality of contact pads at the first major surface. A via bar is disposed in the substrate. An antenna structure is disposed within the via bar.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Maciej Wojnowski, Mehran Pour Mousavi
  • Patent number: 8802563
    Abstract: A method is provided which includes providing a dielectric material having a dielectric constant of about 4.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material and the upper surface of the at least one conductive material has hollow-metal related defects that extend inward into the at least one conductive material; and filling the hollow-metal related defects with a surface repair material.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Conal E. Murray
  • Patent number: 8786092
    Abstract: A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 22, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Mitsuru Okazaki, Youichi Kajiwara, Naoki Takahashi, Akira Shimizu
  • Patent number: 8779597
    Abstract: An apparatus includes a semiconductor chip with a base support structure having a surface and an opposed surface. At least one device structure extends from the surface of the base support structure. A first conductive region is coupled to the base support structure. At least a portion of the first conductive region extends below the opposed surface.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: July 15, 2014
    Inventor: Sang-Yun Lee
  • Patent number: 8772164
    Abstract: According to one embodiment, a method for forming an interconnection pattern includes forming an insulating pattern, forming a self-assembled film, and forming a conductive layer. The insulating pattern has a side surface on a major surface of a matrix. The self-assembled film has an affinity with a material of the insulating pattern on the side surface of the insulating pattern. The forming the conductive layer includes depositing a conductive material on a side surface of the self-assembled film.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhito Yoshimizu, Satoshi Wakatsuki, Hisashi Okuchi, Atsuko Sakata, Hiroshi Tomita
  • Patent number: 8766401
    Abstract: A semiconductor component and methods for manufacturing the semiconductor component that includes a three dimensional helically shaped common mode choke. In accordance with embodiments, a transient voltage suppression device may be coupled to the monolithically integrated common mode choke.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: July 1, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Phillip Holland, Rong Liu, Umesh Sharma, Der Min Liou, David D. Marreiro, Sudhama C. Shastri
  • Patent number: 8759975
    Abstract: A method for fabricating an integrated circuit structure and the resulting integrated circuit structure are provided. The method includes forming a low-k dielectric layer; form an opening in the low-k dielectric layer; forming a barrier layer covering a bottom and sidewalls of the low-k dielectric layer; performing a treatment to the barrier layer in an environment comprising a treatment gas; and filling the opening with a conductive material, wherein the conductive material is on the barrier layer.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Ming Lee, Minghsing Tsai, Syun-Ming Jang
  • Patent number: 8742565
    Abstract: An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Roger D. Weekly, Yaping Zhou
  • Patent number: 8736017
    Abstract: A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: May 27, 2014
    Assignee: SK Hynix Inc.
    Inventors: Se-Aug Jang, Hong-Seon Yang, Ja-Chun Ku, Seung-Ryong Lee
  • Patent number: 8698314
    Abstract: A semiconductor device of the invention include a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element comprises, a plurality of first electrodes formed along a first edge of a surface thereof, a plurality of second electrodes formed along an edge opposite to the first edge of the surface, a plurality of third electrodes formed in the neighborhood of a functional block, and an internal wiring for connecting the first electrodes and the third electrodes. The substrate comprises, a first wiring pattern for connecting the external input terminal and the first electrodes, a second wiring pattern for connecting the external output terminal and the second electrodes, and a third wiring pattern for connecting the first electrodes and the third electrodes.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: April 15, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Akira Nakayama
  • Patent number: 8686394
    Abstract: Some embodiments include methods of forming semiconductor constructions. Carbon-containing material is formed over oxygen-sensitive material. The carbon-containing material and oxygen-sensitive material together form a structure having a sidewall that extends along both the carbon-containing material and the oxygen-sensitive material. First protective material is formed along the sidewall. The first protective material extends across an interface of the carbon-containing material and the oxygen-sensitive material, and does not extend to a top region of the carbon-containing material. Second protective material is formed across the top of the carbon-containing material, with the second protective material having a common composition to the first protective material. The second protective material is etched to expose an upper surface of the carbon-containing material. Some embodiments include semiconductor constructions, memory arrays and methods of forming memory arrays.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Cinzia Perrone
  • Publication number: 20140089609
    Abstract: A system is provided that includes an interposer having memory controller circuitry embedded therein. The interposer includes conductive vias that are embedded within and that extend through the interposer. The memory controller circuitry can be coupled to some of the conductive vias. In some implementations, other ones of the conductive vias are configured to be coupled to a processor and a memory module that can be mounted along a surface of the interposer. Conductive links are disposed on a surface of the interposer to couple the processor and the memory module to the memory controller circuitry.
    Type: Application
    Filed: September 26, 2012
    Publication date: March 27, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Andrew G. Kegel, Gabriel H. Loh
  • Patent number: 8680626
    Abstract: An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: March 25, 2014
    Assignee: Tela Innovations, Inc.
    Inventors: Michael C. Smayling, Scott T. Becker
  • Patent number: 8680691
    Abstract: A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: March 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Syuuichi Kariyazaki
  • Publication number: 20140054784
    Abstract: A connector access region of an integrated circuit device includes a set of parallel conductors, extending in a first direction, and interlayer connectors. The conductors comprise a set of electrically conductive contact areas on different conductors which define a contact plane with the conductors extending below the contact plane. A set of the contact areas define a line at an oblique angle, such as less than 45° or 5° to 27°, to the first direction. The interlayer connectors are in electrical contact with the contact areas and extend above the contact plane. At least some of the interlayer connectors overlie but are electrically isolated from the electrical conductors adjacent to the contact areas with which the interlayer connectors are in electrical contact. The set of parallel conductors may include a set of electrically conductive layers with the contact plane being generally perpendicular to the electrically conductive layers.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Applicant: Macronix International Co., Ltd.
    Inventor: Shih-Hung Chen
  • Patent number: 8653663
    Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: February 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Kuang Kao, Huei-Wen Yang, Yung-Sheng Huang, Yu-Wen Lin
  • Publication number: 20140042642
    Abstract: A conductive line of a semiconductor device includes a conductive layer disposed on a semiconductor substrate. A thickness of the conductive layer is substantially larger than 10000 angstrom (?), and at least a side of the conductive layer has at least two different values of curvature.
    Type: Application
    Filed: August 8, 2012
    Publication date: February 13, 2014
    Inventors: Mu-Chin Chen, Yuan-Sheng Chiang, Chi-Sheng Hsiung
  • Publication number: 20140042627
    Abstract: A secure electronic structure is provided including a via array as a physical unclonable function (PUF). Specifically, the secure electronic structure includes an array of electrical contact vias located between a lower level of a first regularly spaced array of conductors and an upper level of a second regularly spaced array of conductors. Each electrical contact via of the via array is individually addressed through the first regularly spaced array of conductors in the lower level and the second regularly spaced array of conductors in the upper level and has a resistance value. Each resistance value of each electrical contact via forms a distribution of resistance values, wherein the distribution of resistance values is random. This random distribution of the resistance values of the array of electrical contact vias can be used as a physical unclonable function in the electronic structure of the present disclosure.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel C. Edelstein, Gregory M. Fritz, Stephen M. Gates, Dirk Pfeiffer
  • Patent number: 8648472
    Abstract: In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper portions of the first metal interconnect and the second metal interconnect are recessed to form recesses. A second insulating film filling the recesses is then formed above a substrate, and the upper portion of the second insulating film is planarized. Next, a hole and a trench are formed to extend halfway through the second insulating film, and ashing and polymer removal are performed. Subsequently to this, the hole and the trench are allowed to reach the first metal interconnect and the second metal interconnect.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: February 11, 2014
    Assignee: Panasonic Corporation
    Inventor: Shusuke Isono
  • Publication number: 20140027918
    Abstract: An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.
    Type: Application
    Filed: July 30, 2012
    Publication date: January 30, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Marc Tarabbia, Chinh Nguyen, David Doman, Juhan Kim, Xiang Qi, Suresh Venkatesan
  • Publication number: 20140027908
    Abstract: A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is then anisotropically etch to form horizontal interconnects. The interconnects are annealed to form a metal oxide barrier lining. A second low k dielectric layer is then depositing over the horizontal interconnects. Air gaps can be formed between adjacent interconnects to lower parasitic capacitance therebetween.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 30, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Tsung-Jung Tsai, Hsiang-Huan Lee, Ming Han Lee
  • Patent number: 8618637
    Abstract: A semiconductor package includes a semiconductor chip having a plurality of bonding pads. Through-electrodes are formed in the semiconductor chip and are electrically connected to the bonding pads. The through electrodes comprise a plurality of conductors and a plurality of voids that are defined by the conductors. Each conductor may include a plurality of nanowires grouped into a spherical shape having a plurality of voids, a plurality of nanowires grouped into a polygonal shape having a plurality of voids, or the conductors may include a plurality of micro solder balls. The voids of the through electrode absorb stress caused when head is generated during the driving of the semiconductor package.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: December 31, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Han Jun Bae, Woong Sun Lee
  • Patent number: 8618662
    Abstract: Metal nitride coatings containing carbon can be either electrically conductive or substantially non-conductive depending on the degree to which they have been exposed to an oxidative environment. Substantially non-conductive metal nitride coatings can be used as protective layers in electrical devices. Particularly in an electrical device containing carbon nanomaterials, the metal nitride coatings can be used to mask the device's operational characteristics. Such devices can contain an electrical interconnect containing a carbon nanomaterial and a substantially non-conductive coating on the carbon nanomaterial. The substantially non-conductive coating can contain at least one substantially non-conductive metal nitride layer and at least some carbon. Methods for making such devices and metal nitride coatings are also described herein.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: December 31, 2013
    Assignee: Lockheed Martin Corporation
    Inventors: Garo J. Derderian, Jonathan W. Ward
  • Patent number: 8610260
    Abstract: A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: December 17, 2013
    Assignee: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Wael Zohni, Belgacem Haba, Frank Lambrecht
  • Patent number: 8581349
    Abstract: A 3D memory device, including: a first memory layer including a first memory transistor with side gates; a second memory layer including a second memory transistor with side gates; and a periphery circuits layer including logic transistors for controlling the memory, the periphery circuits are covered by a first isolation layer, where the first memory layer includes a first monolithically mono-crystal layer directly bonded to a second isolation layer, and the second memory layer includes a second monolithically mono-crystal layer directly bonded to the second isolation layer, and the first mono-crystal layer is bonded on top of the first isolation layer, and the second memory transistor is self-aligned to the first memory transistor.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: November 12, 2013
    Assignee: Monolithic 3D Inc.
    Inventors: Deepak C. Sekar, Zvi Or-Bach, Brian Cronquist
  • Publication number: 20130270716
    Abstract: A semiconductor device including conductive lines configured to include first lines extending generally in parallel in a first direction and second lines extending generally in parallel in a second direction to intersect the first direction from the respective ends of the first lines and each second line having a width wider than the first line, and dummy patterns formed between the second lines.
    Type: Application
    Filed: August 10, 2012
    Publication date: October 17, 2013
    Applicant: SK hynix Inc.
    Inventors: Hyun Sub KIM, Sung Bo SHIM
  • Patent number: 8552562
    Abstract: A profiled contact for a device, such as a high power semiconductor device is provided. The contact is profiled in both a direction substantially parallel to a surface of a semiconductor structure of the device and a direction substantially perpendicular to the surface of the semiconductor structure. The profiling can limit the peak electric field between two electrodes to approximately the same as the average electrical field between the electrodes, as well as limit the electric field perpendicular to the semiconductor structure both within and outside the semiconductor structure.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: October 8, 2013
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Michael Shur, Remigijus Gaska
  • Patent number: 8547167
    Abstract: A die including a first set of power tiles arranged in a first array and having a first voltage; a second set of power tiles arranged in a second array offset from the first array and having a second voltage; a set of power mesh segments enclosed by the second set of power tiles and having the first voltage; a first power rail passing underneath the set of power mesh segments and the first set of power tiles; and a set of vias operatively connecting the power rail with the set of power mesh segments and the first plurality of power tiles.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: October 1, 2013
    Assignee: Oracle International Corporation
    Inventors: Aparna Ramachandran, Gary John Formica
  • Patent number: 8519515
    Abstract: A TSV structure includes a through via connecting a first side and a second side of a wafer, a conductive layer which fills up the through via, a through via dielectric ring surrounding and directly contacting the conductive layer, a first conductive ring surrounding and directly contacting the through via dielectric ring as well as a first dielectric ring surrounding and directly contacting the first conductive ring and surrounded by the wafer.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: August 27, 2013
    Assignee: United Microlectronics Corp.
    Inventors: Chien-Li Kuo, Chia-Fang Lin
  • Publication number: 20130214425
    Abstract: An electronic package includes a substrate wafer with an interconnect network. A first chip is fixed to a front of the substrate, connected to the interconnect network and encapsulated by a body. A second chip is placed on a back side of the substrate wafer and connected to the interconnect network by back-side connection elements interposed between the back side of the substrate and a front side of the second chip. Front-side connection elements are placed on the front side of the substrate and connected to the interconnect network. The connection elements extend beyond the frontal face of the body. The package may be mounted on a board with an interposed thermally conductive material.
    Type: Application
    Filed: October 18, 2012
    Publication date: August 22, 2013
    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventor: STMICROELECTRONICS (GRENOBLE 2) SAS
  • Publication number: 20130207266
    Abstract: The present invention provides a copper interconnect for III-V compound semiconductor devices, which comprises a metal contact layer and a copper-containing metal layer, in which the metal contact layer is formed of a material selected from a group consisting of Ti/Pd/Cu, Ti/NiV/Cu, TiW/TiWN/TiW/Cu, TiW/TiWN/TiW/Au, TiW/Cu, and TiW/Au, and the copper-containing metal layer comprises a copper layer. The copper-containing metal layer further includes a metal protection layer covering on the copper layer to prevent the copper layer from oxidation. The metal protection layer is formed of Ni/Au, Ni/Pd/Au, NiV/Au, or solder.
    Type: Application
    Filed: June 26, 2012
    Publication date: August 15, 2013
    Inventors: Chang-Hwang Hua, Wen Chu
  • Patent number: 8492263
    Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: July 23, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung Yu Wang, Chien-Hsiun Lee, Pei-Haw Tsao, Kuo-Chin Chang, Chung-Yi Lin, Bill Kiang
  • Patent number: 8487305
    Abstract: A semiconductor device includes a semiconductor substrate, and an insulating layer that is provided on the semiconductor substrate, wherein, in an internal circuit formation region of the insulating layer, a via hole and an interconnect trench, that is formed on the via hole and communicates with the via hole, are provided, in the via hole and the interconnect trench, a conductor is provided so as to integrally fill the via hole and said interconnect trench, in a dicing region of the insulating layer, a groove portion and an opening, that communicates with the groove portion and is formed to cover the groove portion when the semiconductor substrate is seen in plane view, are formed, and in the groove portion and the opening, a conductor is provided so as to integrally fill the groove portion and the opening.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: July 16, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Manabu Iguchi, Mami Miyasaka
  • Patent number: 8476763
    Abstract: Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: July 2, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hei-Seung Kim, In-Sun Park, Gil-Heyun Choi, Ji-Soon Park, Jong-Myeong Lee, Jong-Won Hong
  • Publication number: 20130161832
    Abstract: A semiconductor device includes: a punch stop region formed in a substrate; a plurality of buried bit lines formed over the substrate; a plurality of pillar structures formed over the buried bit lines; a plurality of word lines extending to intersect the buried bit lines and being in contact with the pillar structures; and an isolation layer isolating the word lines from the buried bit lines.
    Type: Application
    Filed: May 3, 2012
    Publication date: June 27, 2013
    Inventors: Heung-Jae CHO, Bong-Seok Jeon
  • Patent number: 8471387
    Abstract: Disclosed herein is an extendable network structure, which includes a first device portion, a second device portion and at least three connectors. The three connectors are connected to the first device portion. The second device portion is electrically connected to the first device portion through one of the three connectors. The first and second device portions respectively have a first and a second center. Each of the connectors may be extendable from an initial state to an extended state, such that a first distance between the first and second centers in the extended state is at least 1.1 fold of a second distance between the first and second centers in the initial state.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: June 25, 2013
    Assignee: Monolithe Semiconductor Inc.
    Inventor: Kevin T. Y. Huang
  • Publication number: 20130154055
    Abstract: A capacitor of a semiconductor device includes a capacitor structure configured to include electrode layers and dielectric layers alternately stacked, edge regions each stepwise patterned, and a central region disposed between the edge regions, sacrificial layers disposed within the respective electrode layers in the edge regions of the capacitor structure, and support plugs formed in the central region of the capacitor structure and configured to penetrate the electrode layers and the dielectric layers.
    Type: Application
    Filed: September 14, 2012
    Publication date: June 20, 2013
    Applicant: SK HYNIX INC.
    Inventors: Sun Mi PARK, Sang Hyun OH, Sang Bum LEE
  • Publication number: 20130154087
    Abstract: According to one embodiment, a method for forming an interconnection pattern includes forming an insulating pattern, forming a self-assembled film, and forming a conductive layer. The insulating pattern has a side surface on a major surface of a matrix. The self-assembled film has an affinity with a material of the insulating pattern on the side surface of the insulating pattern. The forming the conductive layer includes depositing a conductive material on a side surface of the self-assembled film.
    Type: Application
    Filed: June 18, 2012
    Publication date: June 20, 2013
    Inventors: Yasuhito YOSHIMIZU, Satoshi Wakatsuki, Hisashi Okuchi, Atsuko Sakata, Hiroshi Tomita
  • Publication number: 20130154015
    Abstract: A three-dimension circuit structure includes a substrate, a first conductive layer, a filled material and a second conductive layer. The substrate has an upper surface and a cavity located at the upper surface. The first conductive layer covers the inside walls of the cavity and protrudes out the upper surface. The filled material fills the cavity and covers the first conductive layer. The second conductive layer covers the filled material and a portion of the first conductive layer, and the first conductive layer and the second conductive layer encapsulate the filled material. The material of the filled material is different from that of the first conductive layer and the second conductive layer.
    Type: Application
    Filed: August 13, 2012
    Publication date: June 20, 2013
    Applicant: E Ink Holdings Inc.
    Inventors: Wei-Chou Lan, Ted-Hong Shinn, Henry Wang, Chia-Chun Yeh
  • Patent number: 8461045
    Abstract: An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: June 11, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Ching Hsu, Chen-Shien Chen, Hon-Lin Huang
  • Patent number: 8415796
    Abstract: A semiconductor device includes a semiconductor substrate including a bump electrode, a first insulating layer formed on the semiconductor substrate and arranged to a lateral direction of the bump electrode, a first wiring layer formed on the first insulating layer and connected to the bump electrode, a second insulating layer formed on the first wiring layer, a via hole formed in the second insulating layer, and reaching the first wiring layer, a second wiring layer formed on the second insulating layer and connected to the first wiring layer via a via conductor formed in the via hole, and an external connection terminal connected to the second wiring layer, wherein an elastic modulus of the second insulating layer is set lower than an elastic modulus of the first insulating layer.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: April 9, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Takaharu Yamano
  • Publication number: 20130069237
    Abstract: Some embodiments include constructions which have platinum-containing structures. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures and across metal oxide. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures, across a first material retaining the platinum-containing structures, and across metal oxide liners along sidewalls of the platinum-containing structures and directly between the platinum-containing structures and the first material. Some embodiments include methods of forming platinum-containing structures. In some embodiments, first material is formed across electrically conductive structures, and metal oxide is formed across the first material. Openings are formed to extend through the metal oxide and the first material to the electrically conductive structures. Platinum-containing material is formed within the openings and over the metal oxide.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 21, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Andrey V. Zagrebelny, Chet E. Carter, Andrew Carswell