Abstract: Interconnect structures including liner layers that are non-planar with at least the adjacent insulating layer and at least one capping layer on conductive features embedded in the insulating layer. The interconnect structure includes an insulating layer of a dielectric material having a top surface and a bottom surface between the top surface and a substrate. An opening, such as a trench, has sidewalls extending from the top surface of the insulating layer toward the bottom surface and is at least partially filled by a conductive feature. A capping layer is disposed on at least a top surface of the conductive feature. A conductive liner layer is disposed between the insulating layer and the conductive feature along at least the sidewalls of the opening. The conductive liner layer has sidewall portions projecting above the top surface of the insulating layer adjacent to the sidewalls of the opening.

Abstract: A method for making a circuit plate includes: forming first holes in an insulating layer; forming a conductive layer on the insulating layer such that a portion of the conductive layer fills the first holes; grinding the conductive layer such that the portion of the conductive layer remains in the first holes to form a pattern of conductive traces; forming a dielectric protective layer that covers the insulating layer and the conductive traces; forming a pattern of second holes in the protective layer such that a portion of each of the conductive traces is accessible through a respective one of the second holes; and forming conductive bumps that are respectively connected to the conductive traces.

Abstract: A leadframe of a leadless flip-chip package includes a plurality of inner leads, a nonconductive ink layer and a solder mask layer. The inner leads have a plurality of bump-connecting terminals, a plurality of outer terminals and a plurality of redistribution lead portions. A half-etched recession is formed on lower surfaces of the redistribution lead portions, and is filled with the non-conductive ink layer. The non-conductive ink layer fixes the redistribution lead portions onto the bump-connecting terminals. The solder mask layer is easily formed on the non-conductive ink layer and covers the inner leads.

Abstract: A semiconductor device having a contact barrier for insulating contacts with a large aspect ratio and having a fine pitch between adjacent conductive lines and a method of manufacturing the same are provided. The semiconductor device includes a buried contact formed in a region between two adjacent first conductive lines and two adjacent second conductive lines. Insulating lines define a width of the buried contact. To form the contact barrier, an interlayer dielectric layer formed on the second conductive lines is patterned to form a space and an insulating line having an etching ratio different from the interlayer dielectric layer is formed in the space. The interlayer dielectric layer is selectively wet etched relative to an insulating layer covering the second conductive line and the first insulating line to form buried contact hole. The buried contact hole is filled with conductive material to form a buried contact.

Abstract: A method of forming a metal line in a semiconductor device is disclosed. The method of forming a metal line in a semiconductor device includes forming an interlayer insulating film over a substrate. A via hole may be formed by selectively patterning the interlayer insulating film. A metal film may be formed over a surface of the interlayer insulating film including an inner portion of the via hole. The inner portion of the via hole may be filled with copper. A copper layer exposed over the surface of the interlayer insulating film may be deplated using reverse current to form a copper metal line and a recess region over the copper metal line. An upper insulating film may be formed over the surface of the interlayer insulating film including the recess region by deposition. An insulating cap layer may be selectively formed over only the recess region on the copper metal line by etching the upper insulating film.

Abstract: A semiconductor device according to an embodiment includes a first metal wiring formed on a semiconductor substrate; a first dielectric barrier layer formed on the first metal wiring; an inter-layer dielectric (ILD) layer formed on the first dielectric barrier layer; a plurality of second metal wirings formed on the ILD layer; and at least one hole formed in the ILD layer in regions between second metal wirings.

Abstract: A semiconductor device and a fabricating method thereof are provided. A PMD layer and at least one IMD layer are formed on a semiconductor substrate. A through-electrode penetrates through the PMD layer and the IMD layer, and a connecting electrode connects to the through-electrode.

Abstract: A semiconductor device and a fabricating method thereof are provided. A PMD layer is formed on a semiconductor substrate, and at least one IMD layer is formed on the PMD layer. A through-electrode penetrates through the semiconductor substrate, the PMD layer, and each IMD layer, and a heat emission wiring is formed on an underside of the semiconductor substrate.

Abstract: A semiconductor device includes a first interlayer insulating film formed above a semiconductor substrate, a first source line formed on the first interlayer insulating film, a second interlayer insulating film formed on the first source line, a plurality of bit lines formed on the second interlayer insulating film so as to extend in a direction, the bit lines being arranged at same width and same width, a third interlayer insulating film formed above the bit lines, a second source line formed on the third interlayer insulating film, and a source shunt line formed between the second and third interlayer insulating films, the source shunt line electrically connecting the first and second source lines to each other, the source shunt line being located between the bit lines so as to extend in the same direction as the bit lines, the source shunt line including a width same as the bit lines.

Abstract: A two-bits-per-cell flash memory cell is based on a localized trapping storage mechanism. The memory cell may be programmed via a hot hole injection mechanism and erased via a Fowler-Nordheim electron tunneling mechanism. The memory cells are arranged according to a virtual-ground wiring scheme. Gate structures of the memory cells are arranged in columns, and the widths of the columns are essentially equal to the distance between the columns. Bit lines elongate in pairs between the columns of memory cells and connect corresponding impurity regions being associated to one of the columns of memory cells. Separation devices separating the bit lines of each pair of bit lines are formed symmetrically to the edges of the neighboring columns of memory cells. Program cross-talk issues, concerning memory cells sharing the same bit line, may be avoided while memory cell size remains essentially unaffected.

Abstract: An interconnect structure and method for manufacturing are described wherein an insulating material adjacent to or at least partially surrounding a conductive interconnect has a coefficient of thermal expansion (CTE) equal to or larger than the CTE of the interconnect. For example, a copper-based damascene interconnect layer may be provided, wherein an inter-layer dielectric (ILD) a least partially surrounds the interconnect layer and a cap insulator is disposed on the interconnect layer. In such an embodiment, the CTE of the ILD and/or the cap insulator would be at least as large as the CTE of the interconnect layer. This may result in no stress or compressive stress being applied by the insulating material to the interconnect layer when the device has cooled, such as to room temperature, after formation of the various layers.

Abstract: Provided are a method of forming a bump whose upper surface is substantially flat and whose area can be enlarged in a uniform pad pitch to simplify mounting a liquid crystal display drive IC (LDI) and a semiconductor chip and a mount structure using the method to minimize a pad area inside the chip. Thus, the pad area on an edge of a conventional chip is minimized and the bump is formed in a substantially flat location inside the chip and an electrical connection between the pad and the bump is performed by a redistribution metal line.