Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof
Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.
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This application relates to the following co-pending applications, each of which is hereby incorporated by reference: U.S. application Ser. No. 13/591,924, filed with the United States Patent and Trademark Office (USPTO) on Aug. 22, 2012, and U.S. application Ser. No. 13/591,990, filed with USPTO on Aug. 22, 2012.
TECHNICAL FIELDEmbodiments of the present invention relate generally to microelectronic packaging and, more particularly, to stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof.
BACKGROUNDIt is often useful to combine multiple microelectronic devices, such as semiconductor die carrying integrated circuits (ICs), microelectromechanical systems (MEMS), optical devices, passive electronic components, and the like, into a single package that is both compact and structurally robust. Packaging of microelectronic devices has traditionally been carried-out utilizing a so-called two dimensional (2D) or non-stacked approach in which two or more microelectronic devices are positioned and interconnected in a side-by-side or laterally adjacent spatial relationship. More particularly, in the case of ICs formed on semiconductor die, packaging has commonly entailed the mounting of multiple die to a package substrate and the formation of desired electrical connections through wire bonding or flip-chip (FC) connections. The 2D microelectronic package may then later be incorporated into a larger electronic system by mounting the package substrate to a printed circuit board (PCB) or other component included within the electronic system.
As an alternative to 2D packaging technologies of the type described above, three dimensional (3D) packaging technologies have recently been developed in which microelectronic devices are disposed in a stacked arrangement and vertically interconnected to produce a stacked, 3D microelectronic package. Such 3D packaging techniques yield highly compact microelectronic packages well-suited for usage within mobile phones, digital cameras, digital music players, and other compact electronic devices. Additionally, such 3D packaging techniques enhance device performance by reducing interconnection length, and thus signal delay, between the packaged microelectronic devices. Considerable efforts have been expended in the development of so-called “Package-on-Package” or, more simply, “PoP” packaging technologies. In a conventional PoP packaging approach, vertical interconnection of the stacked microelectronic devices is performed on a package level. That is, subsequent to singulation into individual die via wafer dicing, the semiconductor die are encapsulated to produce a number of discrete die packages. The discrete die packages (also referred to as “package layers” when included within a PoP package) are then stacked and vertically interconnected to produce the completed PoP package. Emerging PoP technologies include Wire Bond (WB) Ball Grid Array (BGA) PoP, FC PoP, Thru Mold Via (TMV) FC PoP, and Redistributed Chip Package (RCP) PoP packaging approaches.
At least one example of the present invention will hereinafter be described in conjunction with the following figures, wherein like numerals denote like elements, and:
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures may be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.
DETAILED DESCRIPTIONThe following Detailed Description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any theory presented in the preceding Background or the following Detailed Description.
Terms such as “first,” “second,” “third,” “fourth,” and the like, if appearing in the description and the subsequent claims, may be utilized to distinguish between similar elements and are not necessarily used to indicate a particular sequential or chronological order. Such terms may thus be used interchangeably and that embodiments of the invention are capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, terms such as “comprise,” “include,” “have,” and the like are intended to cover non-exclusive inclusions, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term “coupled,” as appearing herein, is defined as directly or indirectly connected in an electrical or non-electrical manner. Furthermore, the terms “substantial” and “substantially” are utilized to indicate that a particular feature or condition is sufficient to accomplish a stated purpose in a practical manner and that minor imperfections or variations, if any, are not significant for the stated purpose.
As appearing herein, the term “microelectronic device” is utilized in a broad sense to refer to an electronic device, element, or component produced on a relatively small scale and amenable to packaging in the below-described manner. Microelectronic devices include, but are not limited to, integrated circuits formed on semiconductor die, microelectromechanical systems, passive electronic components, optical devices, and other small scale electronic devices capable of providing processing, memory, sensing, radiofrequency, optical, and actuator functionalities, to list but a few examples. Furthermore, the term “microelectronic package” is utilized herein to denote a structure or assembly including at least one and typically two or more microelectronic devices, which may or may not be electrically interconnected; and the term “stacked microelectronic package” is utilized to refer to a microelectronic package containing at least two microelectronic devices located within different levels or overlying layers of the microelectronic package. Finally, the term “stacked microelectronic devices” is utilized to collectively refer to two or more microelectronic devices, which are located on different levels of a stacked microelectronic package, as previously defined. The term “stacked microelectronic devices” thus does not require that one microelectronic device is necessarily positioned directly above or beneath another.
The following describes exemplary embodiments of a method for fabricating stacked microelectronic packages, which overcome the limitations associated with conventional PoP packaging approaches and other known packaging technologies of the type described above. In some, but not all, of the below-described embodiments, the fabrication method is performed through the processing of large scale, pre-singulated microelectronic device panels, which each contain a plurality of microelectronic devices embedded or encapsulated within a panel body. During processing, the device panels are laminated together or otherwise combined to produce panel stacks, which are later separated or singulated into a number of discrete package units each containing at least two packaged microelectronic devices. The microelectronic devices may be electrically interconnected by a number of package sidewall conductors or interconnects. Additionally or alternatively, the package sidewall conductors can be utilized to provide a convenient means of electrically coupling a microelectronic device contained within a lower package layer to contacts included within a contact formation formed over an upper package layer. In such embodiments wherein processing is performed on panel or partial panel level, the fabrication method improves efficiency, cost effectiveness, scalability, and overall productivity as compared to conventional packaging techniques wherein interconnection of stacked packages is carried-out on a die level or on a post-singulation package level. These benefits notwithstanding, embodiments of the fabricating method described herein can also be performed on a package level, as described more fully below in conjunction with
Exemplary method 30 commences with the production of a number of microelectronic device panels each containing an array of microelectronic devices (STEP 32,
Device panel 34 can be produced utilizing a fan-out wafer level packaging approach, such as a Redistributed Chip Packaging (RCP) manufacturing process. By way of non-limiting example, one RCP process suitable for fabricating device panel 34 may be performed as follows. First, microelectronic devices 38 are distributed in a desired spatial arrangement over the surface of a support substrate or carrier; e.g., devices 38 may be arranged over the carrier in a grid array of the type shown in
After encapsulation of microelectronic devices 38 within panel body 36, a plurality of package edge conductors is next fabricated over device surface 40 of device panel 34. As utilized herein, the term “package edge conductor” refers to an electrically-conductive element, such as a metal trace, a wire, an interconnect line, a metal-filled trench, a bond pad, or the like, which is electrically coupled to a microelectronic device embedded within a package or package layer and which extends to a sidewall or edge portion of the package to contact a sidewall conductor, such as the sidewall conductors described below in conjunction with
By way of non-limiting example,
Package edge conductors 42 extend from their respective microelectronic devices 38 to neighboring dicing streets 44, which surround or border each device 38 and which are generically represented in
Continuing with exemplary fabrication method 30, the microelectronic device panels are next consolidated into a panel stack (STEP 52,
When panels 34 and 54 are properly positioned within panel stack 56, the dicing streets of device panels 34 and 54 overlap, as taken along the vertical or z-axis (identified by legend 46 in
After consolidation of microelectronic device panels 34 and 54 into panel stack 56 in the above-described manner, a number of openings or trenches are next formed in microelectronic panel stack 56 at selected locations (STEP 62,
The illustrated example notwithstanding, trenches 64 need not extend entirely across the face of microelectronic panel stack 56 in all embodiments. Instead, in alternative embodiments, trenches 64 may be formed at discrete locations, whether by sawing or other material removal means, providing that trenches 64 intersect and expose package edge conductors 42 to enable interconnection of embedded microelectronic devices 38 in the manner described below. Furthermore, while conveniently formed to be vertically non-penetrating or blind, trenches 64 may be fully penetrating or partially penetrating in certain embodiments. For example, trenches 64 may be fully penetrating (that is, trenches 64 may extend entirely through lower device panel 54) in embodiments wherein lower device panel 54 is further releasably bonded to a support substrate and/or in embodiments wherein trenches 64 do not extend entirely across microelectronic panel stack 56. Moreover, in embodiments wherein vertical interconnection of the stacked microelectronic packages is required or desired only for one or two of the package sidewalls, a single series of generally parallel, non-intersecting trenches may be formed during STEP 62 of exemplary method 30 (
An electrically-conductive material is next deposited into trenches 64 such that the material contacts the terminal ends of package edge conductors 42 exposed through the vertical trench sidewalls (PROCESS BLOCK 70,
With continued reference to exemplary fabrication method 30 shown in
After deposition of the electrically-conductive material into conductor-exposing trenches 64, a thermal cure may be performed, if needed. If performed, the parameters of the thermal cure will vary depending upon the deposited volume and the particular composition of electrically-conductive material 90 deposited into trenches 64; however, to provide a generalized example in an embodiment wherein a metal-filled epoxy is utilized, an oven cure may be performed at a temperature of about 160° C. to about 300° C. for approximately one hour. As further indicated in
Next, at STEP 76 of exemplary method 30 (
Next, during STEP 78 of exemplary method 30 (
With the completion of STEP 78 (
The foregoing has thus described an embodiment of exemplary method 30 (
Advancing to STEP 80 of exemplary method 30 (
After deposition of the etch mask layer over the plated trench (STEP 80,
Next, selected portions of unpatterned metal film 110 plated or otherwise deposited onto the trench sidewalls are removed to define a plurality of sidewall conductors interconnecting the package layers. Patterning of metal film 110 may be performed as follows. First, at STEP 84 (
In certain embodiments of the above-described fabrication method, a dielectric material may further be deposited over the vertical package sidewalls and in contact with the sidewall conductors formed thereover. In this case, the dielectric material is preferably occupies the area between the neighboring sidewall conductors. Various different dielectric materials suitable for this purpose are known; and various ones of the application techniques described above with the application of the flowable conductive material can be employed to deposit the dielectric including, for example, needle dispensing, or screen-printing techniques. The deposition of such an dielectric material prevents or minimize dendritic growth that may otherwise occur due to surface migration of certain constituents (e.g., silver particles) included within the flowable conductive material from which the sidewall conductors are formed. In addition, the addition of such a dielectric material between the sidewall conductors may provide additional mechanical robustness and may be chosen to have better adhesive properties than the electrically-conductive material from which the sidewall conductors are formed.
The foregoing has thus provided embodiments of a method for fabricating a plurality of stacked microelectronic packages including a number of sidewall conductors or interconnects formed over the package sidewall. As embodiments of the above-described fabrication method are performed on a panel or partial panel level, significant improvements in manufacturing efficiency, cost effectiveness, scalability, and productivity can be realized. Embodiments of the above-described fabrication method also eliminate or reduce the need for vertical connection between package layers utilizing BGAs or similar contact formations thereby enabling a more compact vertical device profile and decreasing manufacturing complexity. Furthermore, embodiments of the fabrication method described above employ uniquely-formed sidewall connectors to interconnect package layers, which provide superior layer-to-layer interconnectivity as compared to BGAs or similar contact formations.
While described above in conjunction with a particular stacked microelectronic package type, it is emphasized that embodiments of exemplary method 30 (
As noted above, stacked microelectronic packages 140 are produced utilizing different paging approaches than was stacked microelectronic package 94 described above in conjunction with
While the above-described fabrication method was performed through the processing of large scale, pre-singulated microelectronic device panel, further embodiments of the fabricating method described herein can also be performed on a package level. This may be more fully appreciated by referring to
After bonding of package layers 172 and 174, patterned package edge conductors are formed over the vertical package sidewalls to interconnect package edge conductors 180 and, therefore, the microelectronic devices contained within the respective molded bodies 176 of the package layers. This may be accomplished utilizing essentially the same process as described above in conjunction with
It should thus be appreciated that there has been provided multiple exemplary embodiments of a method for fabricating stacked microelectronic packages, which provides excellent level-to-level interconnectivity through multiple package stacking, as well as package miniaturization and ultra high density package. In certain embodiments of the above-described method, device panels are produced to contain multiple semiconductor die (or other microelectronic devices), as well as package sidewall conductors (e.g., metal traces) connecting die pads to the saw scribes or dicing streets of the panel. Two or more panels are then laminated together with appropriate alignment and bonding material. A partial saw is applied to cut the panels to the bottommost panel and expose the package sidewall conductors. An electrically-conductive material, such as a metal-containing paste, is then applied to fill the grooves formed by partial saw. Laser ablation is then performed from top or device side of the panel stack to remove excess material in between the sidewall traces. Finally, the laminated panels are singulated into single units.
The foregoing has provided embodiments of a method for fabricating stacked microelectronic packages. In one embodiment, the method includes producing microelectronic device panels each comprising a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. The microelectronic device panels are arranged in a panel stack, and trenches are created in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages, either by fully separating the partially-completed stacked microelectronic packages into a number of discrete packages or by partially separating the stacked microelectronic packages into a number of strips. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.
In another embodiment, a method for fabricating stacked microelectronic packages includes obtaining, whether by independent fabrication or by purchase from a supplier, a partially-completed stacked microelectronic package having at least upper and lower package layers. The upper and lower package layers each include a package body, an electronic device embedded in the package body, and a plurality of package edge conductors extending from the electronic device to a sidewall of the package body. The plurality of package edge conductors are exposed through the sidewall of the package body. An unpatterned electrically-conductive layer is deposited over the package sidewall and contacts the exposed terminal ends of the plurality of package edge conductors. The unpatterned electrically-conductive layer is patterned to remove selected portions of the electrically-conductive layer and yield a plurality of sidewall conductors interconnecting the microelectronic devices included within the upper and lower package layers.
While at least one exemplary embodiment has been presented in the foregoing Detailed Description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing Detailed Description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention. It being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the invention as set-forth in the appended claims.
Claims
1. A method for fabricating stacked microelectronic packages, comprising:
- arranging microelectronic device panels in a panel stack, each microelectronic device panel comprising a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom;
- forming trenches in the panel stack, the trenches having sidewalls through which the plurality of package edge conductors are exposed;
- dispensing a metal-containing epoxy into the trenches in sufficient quantity to substantially fill the trenches and yield a plurality of epoxy-filled trenches
- separating the panel stack into partially-completed stacked microelectronic packages to produce unpatterned metal-containing epoxy layers contacting the plurality of package edge conductors, the panel stack separated along saw lanes extending through the epoxy-filled trenches to impart the unpatterned metal-containing epoxy layers with exposed sidewall surfaces; and
- patterning the unpatterned metal-containing epoxy layers to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic packages, wherein selected portions of the unpatterned metal-containing epoxy layers are removed at the exposed sidewall surfaces during patterning.
2. A method according to claim 1 wherein removing comprises patterning the unpatterned metal-containing epoxy layers using a laser ablation process.
3. A method according to claim 1 wherein each of the plurality of microelectronic device panels is produced using a process comprising:
- embedding microelectronic devices in an encapsulant having a device surface through which the microelectronic devices are exposed; and
- forming the package edge conductors over the device surface and electrically coupled to the microelectronic devices.
4. A method according to claim 1 further comprising depositing a dielectric material between neighboring ones of the plurality of sidewall conductors.
5. A method according to claim 1 wherein each microelectronic device panels comprises dicing streets to which the plurality of package edge conductors extend, and wherein the step of arranging comprises arranging the device panels in a panel stack such that the dicing streets of the device panels at least partially overlap, as taken along a centerline of the panel stack.
6. A method according to claim 5 wherein forming comprises cutting non-penetrating trenches into the panel stack along the dicing streets and transecting the plurality of package edge conductors.
7. A method according to claim 6 wherein cutting comprises cutting non-penetrating trenches into the panel stack having a first predetermined width, and wherein separating comprises singulating the panel stack into a plurality of stacked microelectronic packages utilizing a saw blade having thickness less than the first predetermined width.
8. A method according to claim 1 wherein the unpatterned paste layers are patterned subsequent to separation of the panel stack into partially-completed stacked microelectronic packages.
9. A method according to claim 1 wherein each microelectronic device panel further comprises one or more layers of dielectric material overlying the plurality of microelectronic devices and in which the plurality of edge conductors extend.
10. A method according to claim 2 wherein the laser ablation process is carried-out at laser energy levels less than about 4 Watts.
11. A method for fabricating a stacked microelectronic package, comprising:
- obtaining a partially-completed stacked microelectronic package having at least upper and lower package layers, the upper and lower package layers each comprising: a package body; a microelectronic device embedded in the package body; and one or more dielectric layers overlying the package body and the microelectronic device; and a plurality of package edge conductors formed in the one or more dielectric layers and extending from the microelectronic device to a sidewall of the stacked microelectronic package, the plurality of package edge conductors exposed through the sidewall of the stacked microelectronic package;
- producing an unpatterned metal-containing epoxy layer contacting the plurality of package edge conductors by dispensing a metal-containing epoxy over the sidewall of the package body, curing the metal-containing epoxy, and cutting through the metal-containing epoxy during package singulation; and
- patterning the unpatterned metal-containing epoxy layer by removing selected portions of the electrically-conductive layer at one or more surfaces created when cutting through the metal-containing epoxy layer during package singulation, the unpatterned metal-containing epoxy layer patterned to produce a plurality of sidewall conductors interconnecting the microelectronic devices included within the upper and lower package layers.
12. A method according to claim 8 wherein the unpatterned paste layers cover at least one side of each partially-completed stacked microelectronic packages.
13. A method according to claim 8 wherein the unpatterned paste layers extend around all four sides of each partially-completed stacked microelectronic packages.
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Type: Grant
Filed: Aug 22, 2012
Date of Patent: May 26, 2015
Patent Publication Number: 20140054796
Assignee: FREESCALE SEMICONDUCTOR INC. (Austin, TX)
Inventors: Zhiwei Gong (Chandler, AZ), Michael B Vincent (Chandler, AZ), Scott M Hayes (Chandler, AZ), Jason R Wright (Chandler, AZ)
Primary Examiner: Thao X Le
Assistant Examiner: Gardner W Swan
Application Number: 13/591,969
International Classification: H01L 21/30 (20060101); H01L 23/538 (20060101); H01L 21/78 (20060101); H01L 23/48 (20060101); H01L 23/31 (20060101); H01L 23/498 (20060101); H01L 21/56 (20060101); H01L 25/10 (20060101); H01L 23/00 (20060101);