Abstract: A method of fabricating a magnetic memory device comprises forming, on a substrate, a data storage structure including a bottom electrode, a magnetic tunnel junction pattern, and a top electrode, forming a first capping dielectric layer conformally covering lateral and top surfaces of the data storage structure, and forming a second capping dielectric layer on the first capping dielectric layer. The forming the first capping dielectric layer is performed by PECVD in which a first source gas, a first reaction gas, and a first purging gas are supplied. The forming the second capping dielectric layer Is performed by PECVD in which a second source gas, a second reaction gas, and a second purging gas are supplied. The first and second reaction gases are different from each other. The first and second purging gases are different from each other.

Abstract: Some embodiments relate to an integrated circuit including a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A dielectric layer is disposed over an upper surface of the bottom electrode. A top electrode is disposed over an upper surface of the dielectric layer and is in direct electrical contact with a lower surface of the upper metal layer.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

Abstract: A magnetic sensor includes a substrate including a top surface; an insulating layer disposed on the substrate, the insulating layer including first and second inclined surfaces each inclined with respect to the top surface of the substrate; and an MR element. The MR element is disposed on the first inclined surface or the second inclined surface. The MR element includes a first side surface including a first portion and a second portion, the first portion and the second portion having different angles with respect to the first inclined surface or the second inclined surface.

Abstract: An improved magnetic tunnel junction with two oxide interfaces on each side of a ferromagnetic layer (FML) leads to higher PMA in the FML. The novel stack structure allows improved control during oxidation of the top oxide layer. This is achieved by the use of a FML with a multiplicity of ferromagnetic sub-layers deposited in alternating sequence with one or more non-magnetic layers. The use of non-magnetic layers each with a thickness of 0.5 to 10 Angstroms and with a high resputtering rate provides a smoother FML top surface, inhibits crystallization of the FML sub-layers, and reacts with oxygen to prevent detrimental oxidation of the adjoining ferromagnetic sub-layers. The FML can function as a free or reference layer in an MTJ. In an alternative embodiment, the non-magnetic material such as Mg, Al, Si, Ca, Sr, Ba, and B is embedded by co-deposition or doped in the FML layer.

Abstract: A magnetic memory device includes a first magnetic layer extending in a first direction, a pinned layer on the first magnetic layer, and a second magnetic layer vertically overlapping with the pinned layer with the first magnetic layer interposed between the pinned layer and the second magnetic layer. The first magnetic layer includes, a plurality of magnetic domains arranged in the first direction, and at least one magnetic domain wall between the plurality of magnetic domains, and a magnetization direction of the second magnetic layer is substantially parallel to a top surface of the first magnetic layer.

Abstract: Permanent magnets and method of making the same are provided. The magnets include a magnetic layer having an insulation layer disposed thereon. The insulation layer is formed via additive manufacturing techniques such as laser melting such that it has discrete phases including a magnetic phase and an insulating phase.

Abstract: A magnetic sensor includes a substrate including a top surface; an insulating layer disposed on the substrate, the insulating layer including first and second inclined surfaces each inclined with respect to the top surface of the substrate; and an MR element structure. An MR element is disposed on the first inclined surface or the second inclined surface. The MR element includes a bottom surface facing the first inclined surface or the second inclined surface, a top surface, and a first surface connecting the bottom surface and the top surface and including two steps.

Abstract: A magnetic sensor includes an insulating layer, a first MR element, and a second MR element. The insulating layer includes a first layer and a second layer, and also includes first and second inclined surfaces formed across the first layer and the second layer. Each of the first and second MR elements includes a magnetization pinned layer and a free layer. The magnetization pinned layer and the free layer of the first MR element are disposed on the first inclined surface. The magnetization pinned layer and the free layer of the second MR element are disposed on the second inclined surface.

Abstract: A photodetection element includes a magnetic element including a first ferromagnetic layer to which light is applied, a second ferromagnetic layer, and a spacer layer sandwiched between the first ferromagnetic layer and the second ferromagnetic layer; a first electrode in contact with a first surface of the magnetic element, the first surface being located on a first ferromagnetic layer side of the magnetic element in a lamination direction; a second electrode in contact with a second surface of the magnetic element, the second surface being opposite to the first surface; and a first high thermal conductivity layer disposed outside of the first ferromagnetic layer and having higher thermal conductivity than the first electrode.

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, a RRAM device may include a first electrode, a second electrode, and a switching oxide layer positioned between the first electrode and the second electrode, wherein the switching oxide layer comprises at least one transition metal oxide. The second electrode may include a first layer comprising a first metallic material and a second layer comprising a second metallic material. In some embodiments, the first metallic material and the second metallic material may include titanium and tantalum, respectively. In some embodiments, the second electrode may include an alloy of tantalum. The alloy of tantalum may contain one or more of hafnium, molybdenum, niobium, tungsten, and/or zirconium. In some embodiments, the alloy of tantalum contains a plurality of alloys of tantalum.

Abstract: A magnetic device for magnetic random access memory (MRAM), spin torque MRAM, or spin torque oscillator technology is disclosed wherein a magnetic tunnel junction (MTJ) with a sidewall is formed between a bottom electrode and a top electrode. A passivation layer that is a single layer or multilayer comprising one of B, C, or Ge, or an alloy thereof wherein the B, C, and Ge content, respectively, is at least 10 atomic % is formed on the MTJ sidewall to protect the MTJ from reactive species during subsequent processing including deposition of a dielectric layer that electrically isolates the MTJ from adjacent MTJs, and during annealing steps around 400° C. in CMOS fabrication. The single layer is about 3 to 10 Angstroms thick and may be an oxide or nitride of B, C, or Ge. The passivation layer is preferably amorphous to prevent diffusion of reactive oxygen or nitrogen species.

Abstract: According to one embodiment, a memory device includes a memory cell including a magnetoresistive effect element. The magnetoresistive effect element includes a non-magnetic layer between first and second electrodes in the first direction, a first magnetic layer between the first electrode and the non-magnetic layer, a second magnetic layer between the second electrode and the non-magnetic layer, and a first layer between the second electrode and the second magnetic layer. The first layer includes oxygen and at least one selected from magnesium, transition metal, and lanthanoid, the first layer has a first size in the first direction, the non-magnetic layer has a second size in the first direction. The first size is 1.1 times or more and 2 times or less the second size.

Abstract: Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element that includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direction. The free layer includes a first region, a second region and a third region. The third region is formed from a third material that is configured to magnetically couple the first region and the second region. The first region is formed from a first material having a first predetermined magnetic moment, and the second region is formed from a second material having a second predetermined magnetic moment. The first predetermined magnetic moment is lower that the second predetermined magnetic moment.

Abstract: Some embodiments relate to an integrated chip. The integrated chip includes a memory cell over a substrate, where the memory cell comprises a data storage structure. A conductive interconnect is over the data storage structure and comprises a first protrusion adjacent to a first side of the data storage structure, where the first protrusion comprises a flat bottom surface. A spacer structure is disposed on the first side of the data storage structure. The spacer structure directly contacts the flat bottom surface of the first protrusion.

Abstract: One example magnetic random access memory includes a plurality of structural units and a plurality of voltage control lines. The plurality of voltage control lines are in parallel with each other. Planes in which the plurality of structural units are located are in parallel with each other, and a plane in which each of the plurality of structural units is located is perpendicular to the plurality of voltage control lines. Each structural unit includes a multi-layer storage structure including multiple layers that are stacked in sequence. Each layer of the multi-layer storage structure includes an electrode line and a plurality of storage units disposed on the electrode line. Each of the plurality of storage units includes a magnetic tunnel junction. A first end of each storage unit is connected to the electrode line, and a second end of each storage unit is connected to one of the plurality of voltage control lines.

Abstract: A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.

Abstract: A magnetic sensor includes a first insulating layer, a second insulating layer, a third insulating layer, a lower coil element located on an opposite side of the first insulating layer from the second insulating layer, and a second MR element. The second MR element includes a magnetization pinned layer and a free layer. The magnetization pinned layer and the free layer are located on an opposite side of the third insulating layer from the second insulating layer. The first and third insulating layers each contain a first insulating material. The second insulating layer contains a second insulating material.

Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes metal layers that are stacked over one another with dielectric layers disposed between. The metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ. A sidewall spacer surrounds an outer periphery of the top electrode. Less than an entirety of a top electrode surface is in direct electrical contact with a metal via connected to the upper metal layer.

Abstract: A semiconductor device includes a conductive pattern extending in a first direction, a magnetic tunnel junction pattern on the conductive pattern, and a capacitor on the magnetic tunnel junction pattern. The magnetic tunnel junction pattern is between the conductive pattern and the capacitor, and the magnetic tunnel junction pattern connects to the capacitor, and the conductive pattern is configured to apply spin-orbit torque to the magnetic tunnel junction pattern.

Abstract: The present disclosure is drawn to, among other things, an antifuse circuit. The antifuse circuit includes a plurality of antifuse bitcells and a reference resistor. Each antifuse bitcell includes two or more memory bits and a reference resistor. The two or more memory bits are configured to be in a programmed state and at least one unprogrammed state.

Abstract: A magnetic tunneling junction (MTJ) element includes a reference layer, a tunnel barrier layer on the reference layer, a free layer on the tunnel barrier layer, and a composite capping layer on the free layer. The composite capping layer comprises a diffusion-stop layer on the free layer, a light-element sink layer on the diffusion-stop layer, and an amorphous layer on the light-element sink layer.

Abstract: A magnetic tunnel junction includes at least one free layer, at least one reference layer, and at least one tunnel barrier separating the free layer and the reference layer, wherein the free layer is an inhomogeneous granular layer including at least two grains, each grain of the at least two grains being sensibly magnetically decoupled from the other adjacent grains of the at least two grains.

Abstract: A memory cell of a magnetic random access memory includes multiple layers disposed between a first metal layer and a second metal layer. At least one of the multiple layers include one selected from the group consisting of an iridium layer, a bilayer structure of an iridium layer and an iridium oxide layer, an iridium-titanium nitride layer, a bilayer structure of an iridium layer and a tantalum layer, and a binary alloy layer of iridium and tantalum.

Abstract: Disclosed is a memory device including a lower electrode, a seed layer, a synthetic antiferromagnetic layer, a magnetic tunnel junction, and an upper electrode laminated on a substrate, wherein the magnetic tunnel junction includes a pinned layer, a tunnel barrier layer, and free layers, wherein the free layers include a first free layer, a spacer layer, a coupling layer, a buffer layer, and a second free layer laminated in sequential order.

Abstract: A semiconductor structure and a fabrication method thereof. The semiconductor structure, includes: a substrate; and magnetic tunnel junctions on the substrate, that each magnetic tunnel junction of the magnetic tunnel junctions includes a first region and a second region adjacent to the first region, each magnetic tunnel junction includes a multilayered material including material layers stacked along a normal direction of the substrate, and the material layers of each magnetic tunnel junction include at least one material layer that is different in the first region and the second region. The storage capacity density of the semiconductor structure is high.

Abstract: A magnetic tunnel junction device is disclosed comprising a first device layer comprising a material having a magnetic moment; a second device layer comprising a material having a magnetic moment, e.g., wherein the magnetic moment of the material of the second device layer is different from that of the material of the first device layer; and a barrier layer, e.g., tunnel barrier, having a first interface to the first device layer comprising predominantly of a scandium nitride (ScN) material and having a second interface to the second device layer comprising predominantly of a scandium nitride (ScN) material.

Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.

Abstract: A memory device comprises a source region, a drain region, a channel region, a gate dielectric layer, an MTJ stack, and a metal gate. The source region and the drain region are over a substrate. The channel region is between the source region and the drain region. The gate dielectric layer is over the channel region. The MTJ stack is over the gate dielectric layer. The MTJ stack comprises a first ferromagnetic layer, a second ferromagnetic layer with a switchable magnetization, and a tunnel barrier layer between the first and second ferromagnetic layers. The metal gate is over the MTJ stack.

Abstract: A non-volatile associative memory cell includes: one magnetoresistance effect element including first and second ferromagnetic layers and a non-magnetic layer; first and second match lines connected to the magnetoresistance effect element in accordance with predetermined first and second search line voltages. The magnetoresistance effect element includes: first and second members. The first member includes first and second electrodes disposed at opposite ends. The first ferromagnetic layer is in the first or second member, the non-magnetic layer is stacked in the first direction, and the direction of internal magnetization of the first ferromagnetic layer changes in a case in which a current flows between the first and second electrodes. The non-magnetic and the second ferromagnetic layers are in the second member. A magnetoresistance effect element resistance value changes.

Abstract: A magnetic sensor includes an insulating layer, a first MR element, and a second MR element. The insulating layer includes a protruding surface including first and second inclined surfaces. Each of the first and second MR elements includes a magnetization pinned layer and a free layer. The magnetization pinned layer and the free layer of the first MR element are disposed on the first inclined surface. The magnetization pinned layer and the free layer of the second MR element are disposed on the second inclined surface. The dimension of the protruding surface in a direction parallel to the Z direction is in the range of 1.4 ?m to 3.0 ?m.

Abstract: A magnetoresistive random access memory (MRAM) cell includes a bar-type magnetic tunneling junction (MTJ), where the antiferromagnetic layer, the free layer, the barrier layer, and the reference layer have substantially aligned sidewalls. A spacer is against the sidewall of each of the antiferromagnetic layer, the free layer, the barrier layer, and the reference layer. A bar-type MTJ is manufactured from a single element of a pattern for isolated MTJs for MRAM cells. A barrier layer of a bar-type MTJ has a larger area than column-type MTJs, leading to extended MRAM cell lifetime because the barrier layer has a lower tunneling current density across the barrier layer.

Abstract: Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.

Abstract: A state detection sensor includes a housing and a position sensing component mounted in the housing. The position sensing component is being configured to provide position data in response to detecting the presence or position of vehicle structure relative to the sensor. The state detection sensor also includes an analog input component mounted in the housing. The analog input component is configured to provide external analog sensor data in response to an analog signal received from an external analog sensor to which the analog input component can be operatively connected. The state detection sensor further includes a component configured to communicate the position data and the external analog sensor data via a serial bus.

Abstract: A magnetic sensor includes an insulating layer including a protruding surface, a first MR element, and a second MR element. The protruding surface includes a first curved surface portion. The first curved surface portion includes a first portion including an upper end portion of the protruding surface, and a second portion continuous with the first portion at a position away from the upper end portion of the protruding surface. When the shape of the protruding surface is regarded as a function Z, the mean value of the absolute value of a second derivative Z? of the function Z corresponding to the first portion is smaller than the mean value of the absolute value of the second derivative Z? of the function Z corresponding to the second portion.

Abstract: A magnetoresistive memory cell includes a first electrode, a second electrode that is spaced from the first electrode, a magnetic tunnel junction layer stack located between the first electrode and the second electrode, the magnetic tunnel junction layer stack containing, from one side to another, a reference layer having a fixed reference magnetization direction, a tunnel barrier layer comprising a dielectric material, and a free layer, and an asymmetric magnetoresistance layer located between the magnetic tunnel junction layer stack and one of the first electrode and the second electrode.

Abstract: A spin-orbit-torque (SOT) magnetic device includes a bottom metal layer, a first magnetic layer disposed over the bottom metal layer, a spacer layer disposed over the first magnetic layer, and a second magnetic layer disposed over the spacer layer. A diffusion barrier layer for suppressing metal elements of the first magnetic layer from diffusing into the bottom metal layer is disposed between the bottom metal layer and the first magnetic layer.

Abstract: According to one embodiment, a magnetic sensor includes a first sensor part. The first sensor part includes a first magnetic member, a first counter magnetic member, and a first magnetic element. A direction from the first magnetic member toward the first counter magnetic member is along a first direction. The first magnetic element includes one or a plurality of first extension parts. The first extension part includes a first magnetic layer, a first counter magnetic layer, and a first nonmagnetic layer. The first magnetic layer includes a first portion, a first counter portion, and a first middle portion. A direction from the first portion toward the first counter portion is along the first direction. The first middle portion is between the first portion and the first counter portion. The first nonmagnetic layer is between the first counter magnetic layer and at least a portion of the first middle portion.

Abstract: Techniques for reducing damage in memory cells are provided. Memory cell structures are typically formed using dry etch and/or planarization processes which damage certain regions of the memory cell structure. In one or more embodiments, certain regions of the cell structure may be sensitive to damage. For example, the free magnetic region in magnetic memory cell structures may be susceptible to demagnetization. Such regions may be substantially confined by barrier materials during the formation of the memory cell structure, such that the edges of such regions are protected from damaging processes. Furthermore, in some embodiments, a memory cell structure is formed and confined within a recess in dielectric material.

Abstract: Provided is a magnetoresistive random-access memory (MRAM) cell. The MRAM cell comprises a top contact, a hard mask layer below the top contact, and a magnetic tunnel junction (MTJ) below the hard mask layer. The MRAM cell further comprises a diffusion barrier below the MTJ, a bottom contact below the diffusion barrier, and a magnetic liner arranged around the bottom contact.

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.

Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

Abstract: A display panel has an active area, and the active area has a camera region. The display panel includes a base, an insulating layer, and a plurality of transparent wirings. The insulating layer is disposed on the base. The insulating layer is provided with a plurality of first grooves located in the camera region. An included angle between a groove wall of a first groove and a surface on which an opening of the first groove is located is less than 90 degrees. The plurality of transparent wirings are disposed on groove walls of the plurality of first grooves.

Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.

Abstract: A wearable sensor apparatus includes a band shaped and sized to be worn on a finger or limb of a user, a plurality of sensor coils configured to detect a magnetic field. A processor configured to calculate a position of the wearable sensor apparatus based upon signals from the plurality of sensor coils, and a communication module configured to transmit the position of the wearable sensor apparatus.

Abstract: The present disclosure provides a semiconductor structure, and a method for fabricating a semiconductor structure, the method includes forming a bottom electrode, forming a magnetic tunneling junction (MTJ) layer over the bottom electrode, wherein the MTJ layer includes a first material, forming a top electrode over the MTJ layer, forming a first dielectric layer over the top electrode and the MTJ layer, and patterning the MTJ layer to form an MTJ, thereby generating residue over an outer sidewall of the first dielectric layer, wherein the residue comprises the first material, and the residue is apart from the bottom electrode, forming a second dielectric layer over the first dielectric layer to encapsulate the residue, and forming an insulation layer surrounding the second dielectric layer.

Abstract: Provided is a Hall element that detects a magnetic field. The Hall element includes a substrate including a semiconductor region, a first drive electrode arranged on the substrate, a first ground electrode arranged on the substrate separately from the first drive electrode in a first direction, a second ground electrode arranged on the substrate separately from the first drive electrode in a second direction different from the first direction, and a detection electrode group including a first electrode group that detects a Hall voltage generated by a current of components perpendicular to a surface of the substrate, the current flowing from the first drive electrode to the first ground electrode and the second ground electrode.

Abstract: A magnetic sensor includes a substrate including a top surface; an insulating layer disposed on the substrate, the insulating layer including first and second inclined surfaces each inclined with respect to the top surface of the substrate; and an MR element. The MR element is disposed on the first inclined surface or the second inclined surface. The MR element includes a first side surface including a first portion and a second portion, the first portion and the second portion having different angles with respect to the first inclined surface or the second inclined surface.

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ?1 and the core material exhibits a second resistivity ?2 and ?2 is less than ?1.