Abstract: A magnetic sensor includes an insulating layer including a protruding surface, a first MR element, and a second MR element. The protruding surface includes a first curved surface portion. The first curved surface portion includes a first portion including an upper end portion of the protruding surface, and a second portion continuous with the first portion at a position away from the upper end portion of the protruding surface. When the shape of the protruding surface is regarded as a function Z, the mean value of the absolute value of a second derivative Z? of the function Z corresponding to the first portion is smaller than the mean value of the absolute value of the second derivative Z? of the function Z corresponding to the second portion.

Abstract: A state detection sensor includes a housing and a position sensing component mounted in the housing. The position sensing component is being configured to provide position data in response to detecting the presence or position of vehicle structure relative to the sensor. The state detection sensor also includes an analog input component mounted in the housing. The analog input component is configured to provide external analog sensor data in response to an analog signal received from an external analog sensor to which the analog input component can be operatively connected. The state detection sensor further includes a component configured to communicate the position data and the external analog sensor data via a serial bus.

Abstract: A magnetoresistive memory cell includes a first electrode, a second electrode that is spaced from the first electrode, a magnetic tunnel junction layer stack located between the first electrode and the second electrode, the magnetic tunnel junction layer stack containing, from one side to another, a reference layer having a fixed reference magnetization direction, a tunnel barrier layer comprising a dielectric material, and a free layer, and an asymmetric magnetoresistance layer located between the magnetic tunnel junction layer stack and one of the first electrode and the second electrode.

Abstract: A spin-orbit-torque (SOT) magnetic device includes a bottom metal layer, a first magnetic layer disposed over the bottom metal layer, a spacer layer disposed over the first magnetic layer, and a second magnetic layer disposed over the spacer layer. A diffusion barrier layer for suppressing metal elements of the first magnetic layer from diffusing into the bottom metal layer is disposed between the bottom metal layer and the first magnetic layer.

Abstract: According to one embodiment, a magnetic sensor includes a first sensor part. The first sensor part includes a first magnetic member, a first counter magnetic member, and a first magnetic element. A direction from the first magnetic member toward the first counter magnetic member is along a first direction. The first magnetic element includes one or a plurality of first extension parts. The first extension part includes a first magnetic layer, a first counter magnetic layer, and a first nonmagnetic layer. The first magnetic layer includes a first portion, a first counter portion, and a first middle portion. A direction from the first portion toward the first counter portion is along the first direction. The first middle portion is between the first portion and the first counter portion. The first nonmagnetic layer is between the first counter magnetic layer and at least a portion of the first middle portion.

Abstract: Techniques for reducing damage in memory cells are provided. Memory cell structures are typically formed using dry etch and/or planarization processes which damage certain regions of the memory cell structure. In one or more embodiments, certain regions of the cell structure may be sensitive to damage. For example, the free magnetic region in magnetic memory cell structures may be susceptible to demagnetization. Such regions may be substantially confined by barrier materials during the formation of the memory cell structure, such that the edges of such regions are protected from damaging processes. Furthermore, in some embodiments, a memory cell structure is formed and confined within a recess in dielectric material.

Abstract: Provided is a magnetoresistive random-access memory (MRAM) cell. The MRAM cell comprises a top contact, a hard mask layer below the top contact, and a magnetic tunnel junction (MTJ) below the hard mask layer. The MRAM cell further comprises a diffusion barrier below the MTJ, a bottom contact below the diffusion barrier, and a magnetic liner arranged around the bottom contact.

Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.

Abstract: A display panel has an active area, and the active area has a camera region. The display panel includes a base, an insulating layer, and a plurality of transparent wirings. The insulating layer is disposed on the base. The insulating layer is provided with a plurality of first grooves located in the camera region. An included angle between a groove wall of a first groove and a surface on which an opening of the first groove is located is less than 90 degrees. The plurality of transparent wirings are disposed on groove walls of the plurality of first grooves.

Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.

Abstract: A wearable sensor apparatus includes a band shaped and sized to be worn on a finger or limb of a user, a plurality of sensor coils configured to detect a magnetic field. A processor configured to calculate a position of the wearable sensor apparatus based upon signals from the plurality of sensor coils, and a communication module configured to transmit the position of the wearable sensor apparatus.

Abstract: The present disclosure provides a semiconductor structure, and a method for fabricating a semiconductor structure, the method includes forming a bottom electrode, forming a magnetic tunneling junction (MTJ) layer over the bottom electrode, wherein the MTJ layer includes a first material, forming a top electrode over the MTJ layer, forming a first dielectric layer over the top electrode and the MTJ layer, and patterning the MTJ layer to form an MTJ, thereby generating residue over an outer sidewall of the first dielectric layer, wherein the residue comprises the first material, and the residue is apart from the bottom electrode, forming a second dielectric layer over the first dielectric layer to encapsulate the residue, and forming an insulation layer surrounding the second dielectric layer.

Abstract: Provided is a Hall element that detects a magnetic field. The Hall element includes a substrate including a semiconductor region, a first drive electrode arranged on the substrate, a first ground electrode arranged on the substrate separately from the first drive electrode in a first direction, a second ground electrode arranged on the substrate separately from the first drive electrode in a second direction different from the first direction, and a detection electrode group including a first electrode group that detects a Hall voltage generated by a current of components perpendicular to a surface of the substrate, the current flowing from the first drive electrode to the first ground electrode and the second ground electrode.

Abstract: A magnetic sensor includes a substrate including a top surface; an insulating layer disposed on the substrate, the insulating layer including first and second inclined surfaces each inclined with respect to the top surface of the substrate; and an MR element. The MR element is disposed on the first inclined surface or the second inclined surface. The MR element includes a first side surface including a first portion and a second portion, the first portion and the second portion having different angles with respect to the first inclined surface or the second inclined surface.

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ?1 and the core material exhibits a second resistivity ?2 and ?2 is less than ?1.

Abstract: A magnetic sensor includes a substrate including a top surface; an insulating layer disposed on the substrate, the insulating layer including first and second inclined surfaces each inclined with respect to the top surface of the substrate; and an MR element structure. An MR element is disposed on the first inclined surface or the second inclined surface. The MR element includes a bottom surface facing the first inclined surface or the second inclined surface, a top surface, and a first surface connecting the bottom surface and the top surface and including two steps.

Abstract: A magnetic sensor includes an insulating layer, a first MR element, and a second MR element. The insulating layer includes a first layer and a second layer, and also includes first and second inclined surfaces formed across the first layer and the second layer. Each of the first and second MR elements includes a magnetization pinned layer and a free layer. The magnetization pinned layer and the free layer of the first MR element are disposed on the first inclined surface. The magnetization pinned layer and the free layer of the second MR element are disposed on the second inclined surface.

Abstract: A magnetic tunnel junction memory device includes a vertical stack of magnetic tunnel junction NOR strings located over a substrate. Each magnetic tunnel junction NOR string includes a respective semiconductor material layer that contains a semiconductor source region, a plurality of semiconductor channels, and a plurality of semiconductor drain regions, a plurality of magnetic tunnel junction memory cells having a respective first electrode that is located on a respective one of the plurality of semiconductor drain regions, and a metallic bit line contacting each second electrode of the plurality of magnetic tunnel junction memory cells. The vertical stack of magnetic tunnel junction NOR strings may be repeated along a channel direction to provide a three-dimensional magnetic tunnel junction memory device.

Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.

Abstract: A method of forming a microelectronic device comprises forming a stack structure. Pillar structures are formed to vertically extend through the stack structure. At least one trench and additional trenches are formed to substantially vertically extend through the stack structure. Each of the additional trenches comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the at least one trench and the additional trenches. The dielectric structure comprises at least one angled portion proximate the horizontal boundary of the first portion of at least some of the additional trenches. The at least one angled portion extends at an acute angle to each of a first direction and a second direction transverse to the first direction. Microelectronic devices and electronic systems are also described.

Abstract: A via interconnect structure for an MRAM device is provided. The via interconnect structure includes an interlayer dielectric layer having a via formed therein, a magnetic metal layer formed in the via, the magnetic metal layer having a cavity formed therein, and a nonmagnetic metal layer formed in the cavity of the magnetic metal layer. The magnetic metal layer is configured such that magnetization vectors of the magnetic metal layer are least substantially in-plane relative to an MRAM stack structure of the MRAM device.

Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

Abstract: A resistive memory device includes a resistive memory cell, a source line connected to one end of the resistive memory cell, a bit line connected to another end of the resistive memory cell, and a sensing circuit connected to the source line and the bit line. The sensing circuit is configured to generate a pull-up signal that is pulled up from a first voltage level to a second voltage level, based on a read current flowing through the resistive memory cell, generate a pull-down signal that is pulled down from a third voltage level to a fourth voltage level, based on the read current, and determine data that is stored in the resistive memory cell, based on a difference between the generated pull-up signal and the generated pull-down signal.

Abstract: A magnetic field sensor structure includes a magnetoresistive sensor assembly and a transistor assembly. A dielectric layer is deposited on the transistor assembly. The dielectric layer includes a trench that exposes an interconnect of the transistor assembly. A damascene process is performed to form an ultra-thick metal (UTM) layer within the trench to create a first metal coil. The first metal coil is configured as a first reset component. Another dielectric layer is formed on the first metal coil. A flux guide is formed within the another dielectric layer. A second metal coil is formed over the another dielectric layer. The second metal coil is configured as a second reset component. The first reset component and the second reset component are configured as a reset mechanism, which is responsive to the transistor assembly and operable to magnetize the flux guide to a predetermined orientation.

Abstract: A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure, a conductor layer over and in contact with the layer of dielectric material and above the S/D contact structure, and an interconnect structure over and in contact with the conductor layer.

Abstract: Memory stacks and method of forming the same are provided. A memory stack includes a bottom electrode layer, a top electrode layer and a phase change layer between the bottom electrode layer and the top electrode layer. A width of the top electrode layer is greater than a width of the phase change layer. A first portion of the top electrode layer uncovered by the phase change layer is rougher than a second portion of the top electrode layer covered by the phase change layer.

Abstract: According to one embodiment of the invention, a magnetic sensor includes a first sensor part. The first sensor part includes a first magnetic member, a first counter magnetic member, and a first magnetic element. A direction from the first magnetic member to the first counter magnetic member is along a first direction. The first magnetic element includes one or a plurality of first extending portions. A first portion of the first extending portion overlaps the first magnetic member in a second direction crossing the first direction. A first counter portion of the first extending portion overlaps the first counter magnetic member in the second direction. A first direction length along the first direction of the first extending portion is longer than a third direction length along a third direction of the first extending portion. The third direction crosses a plane including the first direction and the second direction.

Abstract: A computing system is provided, including a processor configured to identify a plurality of measurement sequences that implement a logic gate. Each measurement sequence may include a plurality of measurements of a quantum state of a topological quantum computing device. The processor may be further configured to determine a respective estimated total resource cost of each measurement sequence of the plurality of measurement sequences. The processor may be further configured to determine a first measurement sequence that has a lowest estimated total resource cost of the plurality of measurement sequences. The topological quantum computing device may be configured to implement the logic gate by applying the first measurement sequence to the quantum state.

Abstract: Provided is an X-type 3-terminal STT-MRAM (spin orbital torque magnetization reversal component) having a high thermal stability index ? and a low writing current IC in a balanced manner. A magnetoresistance effect element has a configuration of channel layer (1)/barrier layer non adjacent magnetic layer (2b)/barrier layer adjacent magnetic layer (2a)/barrier layer (3).

Abstract: An illustrative memory cell disclosed herein includes a bottom electrode, a top electrode positioned above the bottom electrode and an MTJ (Magnetic Tunnel Junction) structure positioned above the bottom electrode and below the top electrode. In this example, the MTJ structure includes a first ferromagnetic material layer positioned above the bottom electrode, a non-magnetic insulation layer positioned above the first ferromagnetic material layer and a second ferromagnetic material layer positioned on the non-magnetic insulation layer, wherein there is a curved, non-planar interface between the non-magnetic insulation layer and the ferromagnetic material layer.

Abstract: A method of manufacturing a data storage device may include forming a magnetic tunnel junction layer on a substrate, irradiating a first ion beam on the magnetic tunnel junction layer to form magnetic tunnel junction patterns separated from each other, irradiating a second ion beam on the magnetic tunnel junction layer, and irradiating a third ion beam on the magnetic tunnel junction layer. The first ion beam may be irradiated at a first incident angle. The second ion beam may be irradiated at a second incident angle that may be smaller than the first incident angle. The third ion beam may be irradiated to form sidewall insulating patterns on sidewalls of the magnetic tunnel junction patterns based on re-depositing materials separated by the third ion beam on the sidewalls of the magnetic tunnel junction patterns.

Abstract: A semiconductor device including an SRAM capable of sensing a defective memory cell that does not satisfy desired characteristics is provided. The semiconductor device includes a memory cell, a bit line pair being coupled to the memory cell and having a voltage changed towards a power-supply voltage and a ground voltage in accordance with data of the memory cell in a read mode, and a specifying circuit for specifying a bit line out of the bit line pair. In the semiconductor device, a wiring capacitance is coupled to the bit line specified by the specifying circuit and a voltage of the specified bit line is set to a voltage between a power voltage and a ground voltage in a test mode.

Abstract: A semiconductor device includes a magnetic random access memory (MRAM). The MRAM comprises a plurality of MRAM cells including a first type MRAM cell and a second type MRAM cell. Each of the plurality of MRAM cells includes a magnetic tunneling junction (MTJ) layer including a pinned magnetic layer, a tunneling barrier layer and a free magnetic layer. A size of the MTJ film stack of the first type MRAM cell is different from a size of the MTJ film stack of the second type MRAM cell. In one or more of the foregoing and following embodiments, a width of the MTJ film stack of the first type MRAM cell is different from a width of the MTJ film stack of the second type MRAM cell.

Abstract: A current sensor integrated circuit configured to sense a current through a current conductor includes a lead frame at least one signal lead, a fan out wafer level package (FOWLP), and a mold material enclosing the FOWLP and a portion of the lead frame. The FOWLP includes a semiconductor die configured to support at least one magnetic field sensing element to sense a magnetic field associated with the current, wherein the semiconductor die has a first surface on which at least one connection pad is accessible, a redistribution layer in contact with the at least one connection pad, and an insulating layer in contact with the redistribution layer, wherein the insulating layer is configured to extend beyond a periphery of the semiconductor die by a minimum distance. The die connection pad is configured to be electrically coupled to the at least one signal lead.

Abstract: Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.

Abstract: A technique relates to an integrated circuit (IC). Pillars of a set of memory elements are formed. A bilayer dielectric is formed between the pillars, the bilayer dielectric having an upper dielectric material formed on a lower dielectric material without requiring an etch of the lower dielectric material prior to forming the upper dielectric material, thereby preventing a void in the bilayer dielectric, the lower dielectric material including one or more flowable dielectric materials.

Abstract: A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.

Abstract: The invention disclosed a method to make an implanted hard mask with ultra-small dimensions for fabricating integrated nonvolatile random access memory. Instead of directly depositing hard mask material on top of the memory film stack element, we first make ultra-small VIA holes on a pattern transfer molding (PTM) layer using a reverse memory mask, then fill in the hard mask material into the VIA holes within the PTM material. Ultra-small hard mask pillars are formed after removing the PTM material. To improve the adhesion of the hard mask pillars with the underneath memory stack element, a hard mask sustaining element (HMSE) is added below PTM. Due to a better materials adhesion between HMSE and the hard mask, a stronger hard mask array can be formed.

Abstract: A magnetic memory device includes a bottom electrode, a magnetic tunneling junction disposed over the bottom electrode, and a top electrode disposed over the magnetic tunneling junction, wherein the top electrode includes a first top electrode layer and a second top electrode layer above the first top electrode layer, and wherein the second top electrode layer is thicker than the first top electrode layer.

Abstract: A magnetic memory device includes a conductive line extending in a first direction, a magnetic line extending in a second direction intersecting the first direction on the conductive line, the magnetic line intersecting the conductive line, and a magnetic pattern disposed between the conductive line and the magnetic line. The magnetic pattern has first sidewalls opposite to each other in the first direction, and second sidewalls opposite to each other in the second direction. The second sidewalls of the magnetic pattern are aligned with sidewalls of the conductive line, respectively.

Abstract: A spin element includes a wiring, a laminated body including a first ferromagnetic layer laminated on the wiring, a first conductive part and a second conductive part which sandwich the first ferromagnetic layer in a plan view in a laminating direction, and a first high resistance layer which is in contact with the wiring between the first conductive part and the wiring and has an electrical resistivity equal to or higher than that of the wiring.

Abstract: A magnetic sensor comprising a resin layer having a first surface and a second surface, which is opposite to the first surface and a magnetoresistive effect unit that detects a magnetic field in a predetermined direction, wherein the magnetoresistive effect unit includes at least a first magnetoresistive effect unit that detects a magnetic field in a first direction, the first direction is a direction orthogonal to the first surface of the resin layer, an inclined surface that is inclined at a predetermined angle with respect to the first surface is formed in the first surface of the resin layer, and the first magnetoresistive effect unit is formed in the inclined surface.

Abstract: A resistive random-access memory (RRAM) system includes an RRAM cell. The RRAM cell includes a first select line and a second select line, a word line, a bit line, a first resistive memory device, a first switching device, a second resistive memory device, a second switching device, and a comparator. The first resistive memory device is coupled between a first access node and the bit line. The first switching device is coupled between the first select line and the first access node. The second resistive memory device is coupled between a second access node and the bit line. The second switching device is coupled between the second select line and the second access node. The comparator includes a first input coupled to the bit line, a second input, and an output.

Abstract: A magnetoresistive memory device according to one embodiment includes: first and second layer stacks, each of which includes: a first ferromagnetic layer having a magnetization directed in a first direction; a non-magnetic first conductive layer above the first ferromagnetic layer, a second ferromagnetic layer provided above the first conductive layer and having a magnetization directed in a second direction different from the first direction, a first insulating layer on an upper surface of the second ferromagnetic layer, and a third ferromagnetic layer above the first insulating layer. The second ferromagnetic layer of the second layer stack is thicker than the second ferromagnetic layer of the first layer stack.

Abstract: The present invention relates to a method of preparing an ASA graft copolymer, a method of preparing a thermoplastic resin composition including the ASA graft copolymer, and a method of manufacturing a molded article using the thermoplastic resin composition.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of memory elements on a first interconnect level, and forming an etch stop layer on the plurality of memory elements. A dielectric layer is formed on the etch stop layer, and a portion of the dielectric over the plurality of memory elements is removed to expose a portion of the etch stop layer. The method further includes removing the exposed portion of the etch stop layer. The removing of the portion of the dielectric layer and of the exposed portion of the etch stop layer forms a trench. A metallization layer is formed in the trench on the plurality of memory elements, wherein the metallization layer is part of a second interconnect level.