Including Component Using Galvano-magnetic Effects, E.g. Hall Effect (epo) Patents (Class 257/E27.005)
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Publication number: 20090229653Abstract: This invention discloses a stacked-layered thin film solar cell and a manufacturing method thereof. The stacked-layered thin film solar cell with a plurality of unit cells comprises a substrate, a first electrode layer, a first photoconductive layer, an interlayer, a second photoconductive layer, and a second electrode layer in a series stacked structure. It is characterized in that a first isolation groove and a second isolation groove are formed on borders of the second electrode layer and are extending downward to remove the first photoconductive layer. The first isolation groove is parallel with the unit cells and vertical to the second isolation groove. At least one outer groove is formed on the first electrode layer inside the first isolation groove and the second isolation groove, and at least one cutting groove inside the first isolation groove is formed on the interlayer.Type: ApplicationFiled: July 28, 2008Publication date: September 17, 2009Inventors: Chun-Hsiung Lu, Chien-Chung Bi
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Patent number: 7582926Abstract: The present invention provides a semiconductor storage device having: a first conductivity type region formed in a semiconductor layer; a second conductivity type region formed in the semiconductor layer in contact with the first conductivity type region; a memory functional element disposed on the semiconductor layer across the boundary of the first and second conductivity type regions; and an electrode provided in contact with the memory functional element and on the first conductivity type region via an insulation film, and a portable electronic apparatus comprising the semiconductor storage device. The present invention can fully cope with scale-down and high-integration by constituting a selectable memory cell substantially of one device.Type: GrantFiled: November 30, 2005Date of Patent: September 1, 2009Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Iwata, Akihide Shibata
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Patent number: 7518138Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice. A topological quantum computer encodes information in the configurations of different braids. The computer physically weaves braids in the 2D+1 space-time of the lattice, and uses this braiding to carry out calculations. A pair of quasi-particles, such as non-abelian anyons, can be moved around each other in a braid-like path. The quasi-particles can be moved as a result of a magnetic or optical field being applied to them, for example.Type: GrantFiled: August 31, 2004Date of Patent: April 14, 2009Assignee: Microsoft CorporationInventors: Michael Freedman, Chetan Nayak, Kirill Shtengel
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Publication number: 20090001351Abstract: The present invention relates to a thin film lamination to be used in a micro InSb thin film magnetic sensor which can directly detect a magnetic flux density with high sensitivity and has small power consumption and consumption current, and the InSb thin film magnetic sensor. The InSb thin film magnetic sensor uses an InSb thin film as a magnetic sensor section or a magnetic detecting section. The sensor includes an InSb layer that is an InSb thin film formed on a substrate, and an AlxGayIn1-x-ySb mixed crystal layer (0?x, y?1) which shows resistance higher than the InSb layer or insulation, or p-type conduction, and has a band gap larger than that of InSb. The mixed crystal layer is provided between the substrate and the InSb layer, and has a content of Al and Ga atoms (x+y) in the range of 5.0 to 17%.Type: ApplicationFiled: December 27, 2006Publication date: January 1, 2009Inventors: Ichiro Shibasaki, Hirotaka Geka, Atsushi Okamoto
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Patent number: 7449740Abstract: A semiconductor substrate has a cell region and a peripheral circuit region surrounding the cell region. In the cell region a plurality of lower electrodes are connected to a conductive region of the semiconductor substrate, and are arrayed along row and column directions. A dielectric layer is formed on the plurality of lower electrodes. An upper electrode is formed on the dielectric layer, entirely covering the cell region, and is formed extending to a portion of the peripheral circuit region that has a step coverage lower by a height of the lower electrode than the cell region. An edge of the upper electrode has square-shaped projections that are distanced from each other at a uniform interval and are repetitively arrayed. With the described structure, pattern defects can be sensed and controlled, preventing and substantially reducing process defect.Type: GrantFiled: April 13, 2005Date of Patent: November 11, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Je-Min Park
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Patent number: 7411263Abstract: A magnetic memory device includes a magnetoresistive element and a first wiring layer. The magnetoresistive element includes a fixed layer, a recording layer, and a non-magnetic layer interposed therebetween. The first wiring layer extends in a first direction and generates a magnetic field for recording data in the magnetoresistive element. The recording layer includes a base portion extending in a second direction rotated from the first direction by an angle falling within a range of more than 0° to not more than 20°, and first and second projections projecting from the first and second sides of the base portion in a third direction perpendicular to the second direction. The third and fourth sides of the base portion are inclined with respect to the third direction in the same rotational direction as a rotational direction in which the second direction is rotated.Type: GrantFiled: March 27, 2006Date of Patent: August 12, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Masahiko Nakayama, Tadashi Kai, Sumio Ikegawa, Yoshiaki Fukuzumi, Tatsuya Kishi
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Patent number: 7378698Abstract: A magnetic tunnel junction device includes a magnetically programmable free magnetic layer. The free magnetic layer includes a lamination of at least two ferromagnetic layers and at least one intermediate layer interposed between the at least two ferromagnetic layers.Type: GrantFiled: May 24, 2004Date of Patent: May 27, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Ki Ha, Jang-Eun Lee, Hyun-Jo Kim, Jun-Soo Bae, In-Gyu Baek, Se-Chung Oh
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Patent number: 7326982Abstract: A magnetic memory device comprising, a magneto-resistance effect element that is provided at an intersection between a first write line and a second write line. And the magneto-resistance effect element having, an easy axis that extends in a direction of extension of the first write line, and a first conductive layer for electrical connection to the magneto-resistance effect element, the first conductive layer having sides which are in flush with sides of the magneto-resistance effect element.Type: GrantFiled: September 3, 2004Date of Patent: February 5, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihisa Iwata, Yoshiaki Fukuzumi, Tadashi Kai
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Patent number: 7321131Abstract: Experiments suggest that the mathematically weakest non-abelian TQFT may be physically the most robust. Such TQFT's—the ?=5/2 FQHE state in particular—have discrete braid group representations, so one cannot build a universal quantum computer from these alone. Time tilted interferometry provides an extension of the computational power (to universal) within the context of topological protection. A known set of universal gates has been realized by topologically protected methods using “time-tilted interferometry” as an adjunct to the more familiar method of braiding quasi-particles. The method is “time-tilted interferometry by quasi-particles.” The system is its use to construct the gates {g1, g2, g3}.Type: GrantFiled: October 7, 2005Date of Patent: January 22, 2008Assignee: Microsoft CorporationInventors: Michael H. Freedman, Chetan V. Nayak
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Patent number: 7291891Abstract: A voltage is applied across gate electrodes (103A) and (103B) in a two-dimensional electronic system (101) placed under a magnetic field, and the polarity of an electric current passed between ohmic electrodes (102D) and (102S) is selected to bring about inversion of electron spins based on a non-equilibrium distribution of electrons in a quantum Hall edge state and to initialize the polarization of nuclear spins. An oscillatory electric field of a nuclear magnetic resonance frequency is applied to coplanar waveguides (104A) and (104B) to control the nuclear spin polarization. The controlled spin polarization is read out by measuring the Hall resistance from ohmic electrodes (102VA) and (102VB).Type: GrantFiled: December 5, 2002Date of Patent: November 6, 2007Assignee: Japan Science and Technology AgencyInventors: Tomoki Machida, Susumu Komiyama, Tomoyuki Yamazaki
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Patent number: 7285811Abstract: The present invention provides an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is provided in a trench in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. A first dielectric layer is deposited over the first conductor and insulating layer to a thickness at least greater than the thickness of a desired MRAM cell. The first dielectric layer is patterned and etched to form an opening over the first conductor for the cell shapes. The magnetic layers comprising the MRAM cell are consecutively formed within the cell shapes and the first dielectric layer.Type: GrantFiled: August 31, 2006Date of Patent: October 23, 2007Assignee: Micron Technology, Inc.Inventors: Donald L. Yates, Garry A. Mercaldi
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Patent number: 7265430Abstract: A semiconductor device, comprising a semiconductor chip; a pad electrode; an electrode portion; a wiring portion. An insulating portion is formed from electrically insulating material, covering the surface of the semiconductor chip and sealing the sensor element, wiring portion and electrode portion, in a state which exposes at least the electrode portion on the surface of the semiconductor chip. The electrode portion is placed in a position which does not overlap with the sensor element in the thickness direction of the semiconductor chip.Type: GrantFiled: April 28, 2006Date of Patent: September 4, 2007Assignee: Yamaha CorporationInventors: Hiroshi Naito, Hideki Sato
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Patent number: 7253490Abstract: A vertical Hall device includes: a substrate; a semiconductor region having a first conductive type and disposed in the substrate; and a magnetic field detection portion disposed in the semiconductor region. The magnetic field detection portion is capable of detecting a magnetic field parallel to a surface of the substrate in a case where a current flows through the magnetic field detection portion in a vertical direction of the substrate. The semiconductor region is a diffusion layer including a conductive impurity doped and diffused therein. The semiconductor region is made of diffusion layer so that the device has high design degree of freedom.Type: GrantFiled: March 17, 2005Date of Patent: August 7, 2007Assignee: DENSO CorporationInventor: Satoshi Oohira
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Patent number: 7250624Abstract: A quantum computer can only function stably if it can execute gates with extreme accuracy. “Topological protection” is a road to such accuracies. Quasi-particle interferometry is a tool for constructing topologically protected gates. Assuming the corrections of the Moore-Read Model for v= 5/2's FQHE (Nucl. Phys. B 360, 362 (1991)) we show how to manipulate the collective state of two e/4-charge anti-dots in order to switch said collective state from one carrying trivial SU(2) charge, |1>, to one carrying a fermionic SU(2) charge |?>. This is a NOT gate on the {|1>, |?>} qubit and is effected by braiding of an electrically charged quasi particle ? which carries an additional SU(2)-charge. Read-out is accomplished by ?-particle interferometry.Type: GrantFiled: September 23, 2005Date of Patent: July 31, 2007Assignee: Microsoft CorporationInventors: Michael H. Freedman, Chetan V. Nayak
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Patent number: 7193288Abstract: A ultrathin magnetoelectric transducer and its manufacturing method are provided which enable the quality of mounting to be inspected nondestructively, and can reduce a footprint. The magnetoelectric transducer has a substrate composed of a nonmagnetic substrate, and includes bottom surface connecting electrodes whose leads have a first thickness, and side electrodes which are exposed by dicing and have the first thickness. A more sensitive Hall element has a high-permeability magnetic substrate as the substrate, and includes the bottom surface connecting electrodes whose leads have the first thickness, and the side electrodes exposed by the dicing and having the first thickness. The bottom surface connecting electrodes of the leads with the first thickness are formed across the internal electrodes of adjacent magnetoelectric transducers with maintaining the first thickness. The side electrodes with the first thickness are formed by cutting the center between the adjacent magnetoelectric transducers.Type: GrantFiled: October 18, 2004Date of Patent: March 20, 2007Assignee: Asahi Kasei Electronics Co., Ltd.Inventors: Toshiaki Fukunaka, Atsushi Yamamoto
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Patent number: 7157760Abstract: The present invention provides a magnetic memory device capable of stably writing information by efficiently using a magnetic field generated by current flowing in a conductor, which can be manufactured more easily, and a method of manufacturing the magnetic memory device. The method includes: a stacked body forming step of forming a pair of stacked bodies S20a and S20b on a substrate 31; a lower yoke forming step of forming a lower yoke 4B so as to cover at least the pair of stacked bodies S20a and S20b; and a write line forming step of simultaneously forming a pair of first parts 6F and write bit lines 5a and 5b so as to be disposed adjacent to each other in a first level L1 via an insulating film 7A as a first insulating film on the lower yoke 4B. Thus, the manufacturing process can be more simplified.Type: GrantFiled: September 28, 2004Date of Patent: January 2, 2007Assignee: TDK CorporationInventor: Akifumi Kamijima
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Patent number: 7126202Abstract: A method and system for providing a magnetic element is disclosed. The magnetic element include providing a pinned layer, a spacer layer, and a free layer. The method and system also include providing a heat assisted switching layer and a spin scattering layer between the free layer and the heat assisted switching layer. The spin scattering layer is configured to more strongly scatter majority electrons than minority electrons. The heat assisted switching layer is for improving a thermal stability of the free layer when the free layer is not being switched. Moreover, the magnetic element is configured to allow the free layer to be switched due to spin transfer when a write current is passed through the magnetic element.Type: GrantFiled: November 16, 2004Date of Patent: October 24, 2006Assignee: Grandis, Inc.Inventors: Yiming Huai, Mahendra Pakala
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Patent number: 6963099Abstract: A magnetic memory device includes a magnetoresistance configured to store information. A first wiring is provided along a first direction. The first wiring has a function of applying a magnetic field to the magnetoresistance element. The first wiring has a first surface and a second surface. The second surface faces the magnetoresistance element and the first surface is opposite to it. The second surface is smaller in width than the first surface.Type: GrantFiled: August 10, 2004Date of Patent: November 8, 2005Assignee: Kabushiki Kaisha ToshibaInventor: Yoshiaki Fukuzumi