Abstract: The present invention relates to a method of preparing an ASA graft copolymer, a method of preparing a thermoplastic resin composition including the ASA graft copolymer, and a method of manufacturing a molded article using the thermoplastic resin composition.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of memory elements on a first interconnect level, and forming an etch stop layer on the plurality of memory elements. A dielectric layer is formed on the etch stop layer, and a portion of the dielectric over the plurality of memory elements is removed to expose a portion of the etch stop layer. The method further includes removing the exposed portion of the etch stop layer. The removing of the portion of the dielectric layer and of the exposed portion of the etch stop layer forms a trench. A metallization layer is formed in the trench on the plurality of memory elements, wherein the metallization layer is part of a second interconnect level.

Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

Abstract: Thermal field controlled electrical conductivity change devices and applications therefore are provided. In some embodiments, a thermal switch, comprises: a metal-insulator-transition (MIT) material; first and second terminals electrically coupled to the MIT material; and a heater disposed near the MIT material.

Abstract: A magnetic device may include a layer stack including a work function structure, a dielectric layer, and a ferromagnetic layer, where the ferromagnetic layer is positioned between the work function structure and the dielectric layer. The work function structure is configured to deplete electrons from the ferromagnetic layer or accumulate electrons in the ferromagnetic layer. A magnetization orientation of the ferromagnetic layer is configured to be switched by a voltage applied across the layer stack or by a voltage applied across or through the work function structure.

Abstract: A movement sensor comprises a multi-pole ring magnet, a semiconductor substrate, a first magnetic sensor formed on the semiconductor substrate, and a second magnetic sensor formed on the semiconductor substrate. The first magnetic sensor is configured to produce a first output signal in response to movement of the multi-pole ring magnet, and a centroid of the first and second magnetic sensors are separate and radially aligned on the semiconductor substrate relative to the multi-pole ring magnet. The second magnetic sensor is arranged at a predetermined angle with respect to the first magnetic sensor and is configured to produce a second output signal in response to the movement of the multi-pole ring magnet. The predetermined angle is between 0° and 90° exclusive and is configured to produce a difference in phase between the first and second output signals in response to the movement of the multi-pole ring magnet.

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.

Abstract: A method of forming a microelectronic device comprises forming a stack structure. Pillar structures are formed to vertically extend through the stack structure. At least one trench and additional trenches are formed to substantially vertically extend through the stack structure. Each of the additional trenches comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the at least one trench and the additional trenches. The dielectric structure comprises at least one angled portion proximate the horizontal boundary of the first portion of at least some of the additional trenches. The at least one angled portion extends at an acute angle to each of a first direction and a second direction transverse to the first direction. Microelectronic devices and electronic systems are also described.

Abstract: An integrated circuit device of the invention, includes: a first resistance variable memory element provided on a semiconductor substrate; a second resistance variable memory element provided on the semiconductor substrate; and a semiconductor circuit for controlling write and read of the first resistance variable memory element and the second resistance variable memory element, which is provided on the semiconductor substrate, in which the second resistance variable memory element has a write current that is smaller than a write current of the first resistance variable memory element, and the second resistance variable memory element is disposed farther from the semiconductor substrate than the first resistance variable memory element.

Abstract: A semiconductor device including at least one variable resistance device is provided. A variable resistance element includes: an ion supply layer having a top, a bottom and a sidewall connecting the top to the bottom; an ion-receiving layer having an inner sidewall connected to at least a portion of the sidewall of the ion supply layer; a gate pattern connected to an outer sidewall of the ion-receiving layer; and a source pattern connected to one of the top or bottom of the ion supply layer, and a drain pattern connected to the other one or the top or bottom of the ion supply layer. A resistance of the ion supply layer is varies depending on an amount of ions supplied from the ion supply layer to the ion-receiving layer in response to a voltage applied to the gate pattern.

Abstract: A current sensor includes a lead frame having a plurality of leads, at least two of which form a current conductor configured to carry a current that generates a magnetic field and a substrate having first and second opposing surfaces, the first surface proximate to said current conductor and the second surface distal from the current conductor. A first magnetic field transducer is disposed on the substrate and a first coil is disposed on the substrate adjacent to the first magnetic field transducer, wherein the first magnetic field transducer and the first coil are positioned on a first side of the current conductor. A second magnetic field transducer is disposed on the substrate and a second coil is disposed on the substrate adjacent to the second magnetic field transducer, wherein the second magnetic field transducer and the second coil are positioned on a second side of the current conductor.

Abstract: The present disclosure provides bit cells with data redundancy according to various aspects. In certain aspects, a bit cell includes a first memory element coupled to a write bit line, and a first write-access switch coupled between the first memory element and a ground. The bit cell also includes a second memory element coupled to the write bit line, and a second write-access switch coupled between the second memory element and the ground. The bit cell further includes a read-access switch coupled between the first memory element and a read bit line, wherein a control input of the read-access switch is coupled to a read-select line.

Abstract: A method of producing a multilayer magnetoelectronic device and a related device. The method includes depositing a multilayer structure including at least two ferromagnetic layers disposed one on top of the other and each having a magnetic anisotropy with a corresponding magnetic moment. A magnetization curve is specified for the magnetoelectronic device. The number of ferromagnetic layers and, for each of the ferromagnetic layers, the magnetic moment and the magnetic hardness for obtaining the specified magnetization curve are determined. For each of the ferromagnetic layers a magnetic material, a thickness, an azimuthal angle and an angle of incidence are determined for obtaining the determined magnetic moment and magnetic hardness of the respective ferromagnetic layer. The multilayer structure is deposited using the determined material, thickness, azimuthal angle and angle of incidence for each of the ferromagnetic layers.

Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.

Abstract: A spin-orbit-torque magnetization rotational element includes: a first ferromagnetic layer; and a spin-orbit torque wiring in which a first surface faces the first ferromagnetic layer and a long axis extends in a first direction when viewed in plan view from a lamination direction of the first ferromagnetic layer, wherein the first surface spreads along a reference plane orthogonal to the lamination direction of the first ferromagnetic layer, the spin-orbit torque wiring contains a first virtual cross-section which passes through a first end of the first ferromagnetic layer in the first direction and is orthogonal to the first direction and a second virtual cross-section which passes through a second end of the first ferromagnetic layer in the first direction and is orthogonal to the first direction, and an area of the first virtual cross-section is different from an area of the second virtual cross-section.

Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.

Abstract: A magnetic operational amplifier having a differential stage includes a first magnetic field effect transistor MAGFET and a differential signal conditioner, the differential signal conditioner including a load stage, a differential input pair connected to the load stage and a biasing current source connected to the differential input pair; the magnetic field effect transistor MAGFET being connected to the load stage as a second differential input pair and the differential signal conditioner including a second biasing current source connected to the magnetic field effect transistor MAGFET.

Abstract: The invention relates to a proximity magnetic induction switch control chip and a control method thereof. A proximity magnetic induction switch control chip includes a voltage regulator module, a control module, an output type detection module, a first controllable switch and a second controllable switch. An output type detection module detects proximity magnets. An output type detection module detects a load connected between a voltage input and a signal output of a proximity magnetic induction switch control chip or a load connected between a signal output and a ground terminal. The detection result is transmitted to the control module. The control module controls the first controllable switch or the second controllable switch to actuate the load according to the detection result.

Abstract: A method of forming a device that includes encapsulating a magnetic resistive access memory (MRAM) stack with a first patternable low-k dielectric material that is patterned by an exposure to produce a via pattern that extends to circuitry to logic devices. The via pattern is developed forming a via opening. The method further includes forming a second patternable low-k dielectric material over first patternable low-k dielectric material and filling the via opening. The second patternable low-k dielectric material is patterned by a light exposure to produce a first line pattern to the MRAM stack and a second line pattern to the via opening. The first line pattern and the second line pattern are developed to form trench openings. Thereafter, electrically conductive material is formed in the trench openings and the via opening.

Abstract: Apparatus and methods provide an output signal indicative of a failure of a filter circuit and/or a Schmitt trigger circuit of a magnetic field sensor. A magnetic field sensor includes one or more magnetic field sensing elements that generate a magnetic field signal, a filter circuit that filters the magnetic field signal, a Schmitt trigger circuit that compares the filtered signal to a Schmitt trigger threshold during a first time period, and a diagnostic circuit coupled to the filter circuit that compares the Schmitt trigger threshold to a diagnostic threshold during a second time period that does not overlap with the first time period. An output signal indicative of a failure is output when the diagnostic threshold is greater than a predetermined percentage or absolute value above or below the Schmitt trigger threshold.

Abstract: A method of forming a device that includes encapsulating a magnetic resistive access memory (MRAM) stack with a first patternable low-k dielectric material that is patterned by an exposure to produce a via pattern that extends to circuitry to logic devices. The via pattern is developed forming a via opening. The method further includes forming a second patternable low-k dielectric material over first patternable low-k dielectric material and filling the via opening. The second patternable low-k dielectric material is patterned by a light exposure to produce a first line pattern to the MRAM stack and a second line pattern to the via opening. The first line pattern and the second line pattern are developed to form trench openings. Thereafter, electrically conductive material is formed in the trench openings and the via opening.

Abstract: The present disclosure is directed towards a method for patterning a magnetic sensing layer. The method includes disposing a protective layer on a first of a substrate, disposing a first insulating layer on a first surface of protective layer. An opening is formed in the first insulating layer to expose the first surface of the protective layer. A magnetic sensing layer is disposed over the first insulating layer and a predetermined portion of the first surface of the protective layer within the opening. A second insulating layer can be disposed over the magnetic sensing layer. The second insulation layer and the magnetic sensing layer can be removed from the first insulation layer. Thus, the opening includes the magnetic sensing layer and the second insulation layer after the removal of the second insulation layer and magnetic sensing layer from the first insulation layer.

Abstract: A method of forming a device that includes encapsulating a magnetic resistive access memory (MRAM) stack with a first patternable low-k dielectric material that is patterned by a exposure to produce a via pattern that extends to circuitry to logic devices. The via pattern is developed forming a via opening. The method further includes forming a second patternable low-k dielectric material over first patternable low-k dielectric material and filling the via opening. The second patternable low-k dielectric material is patterned by a light exposure to produce a first line pattern to the MRAM stack and a second line pattern to the via opening. The first line pattern and the second line pattern are developed to form trench openings. Thereafter, electrically conductive material is formed in the trench openings and the via opening.

Abstract: According to an embodiment, a magnetic shield tray includes a main body with a plate form including a magnetic material, and mount portions as holes disposed in the main body. The magnetic material is exposed on an inner surface of the holes.

Abstract: The methods of manufacturing an MRAM device and MRAM devices are provided. The methods may include forming a first electrode on an upper surface of a substrate, forming a first magnetic layer on the first electrode, forming a tunnel barrier structure on the first magnetic layer, forming a second magnetic layer on the tunnel barrier structure, and forming a second electrode on the second magnetic layer. The tunnel barrier structure may include a first tunnel barrier layer and a second tunnel barrier layer that are sequentially stacked on the first magnetic layer and may have different resistivity distributions from each other along a horizontal direction that may be parallel to the upper surface of the substrate.

Abstract: A semiconductor device includes a magnetic random access memory (MRAM) cell. The MRAM cell includes a first magnetic layer disposed over a substrate, a first non-magnetic material layer made of a non-magnetic material and disposed over the first magnetic layer, a second magnetic layer disposed over the first non-magnetic material layer, and a second non-magnetic material layer disposed over the second magnetic layer. The second magnetic layer includes a plurality of magnetic material pieces separated from each other.

Abstract: Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element that includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direction. The free layer includes a first region, a second region and a third region. The third region is formed from a third material that is configured to magnetically couple the first region and the second region. The first region is formed from a first material having a first predetermined magnetic moment, and the second region is formed from a second material having a second predetermined magnetic moment. The first predetermined magnetic moment is lower that the second predetermined magnetic moment.

Abstract: Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element that includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direction. The free layer includes a first region, a second region and a third region. The third region is formed from a third material that is configured to magnetically couple the first region and the second region. The first region is formed from a first material having a first predetermined magnetic moment, and the second region is formed from a second material having a second predetermined magnetic moment. The first predetermined magnetic moment is lower that the second predetermined magnetic moment.

Abstract: A storage array and a storage chip and method for storing a logic relationship between objects. The storage array comprises first leading-out wires and second leading-out wires, and a storage unit is connected between each first leading-out wire and each second leading-out wire having different serial numbers. A controllable switch is connected between each first leading-out wire and each second leading-out wire having a same serial number. The storage chip comprises an interface module. A control module is used for producing a control signal. A driving module is used for producing write current, erase current or read current. A first decoder and a second decoder are used for gating the first leading-out wires and the second leading-out wires. A storage array is used for storing a logic relationship value. The storage method comprises write and read operations.

Abstract: Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element that includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direction. The free layer includes a first region, a second region and a third region. The third region is formed from a third material that is configured to magnetically couple the first region and the second region. The first region is formed from a first material having a first predetermined magnetic moment, and the second region is formed from a second material having a second predetermined magnetic moment. The first predetermined magnetic moment is lower that the second predetermined magnetic moment.

Abstract: A spin-orbit torque type magnetoresistance effect element including a magnetoresistance effect element having a first ferromagnetic metal layer with a fixed magnetization direction, a second ferromagnetic metal layer with a varying magnetization direction, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer; and spin-orbit torque wiring that extends in a first direction intersecting with a stacking direction of the magnetoresistance effect element and that is joined to the second ferromagnetic metal layer; wherein the magnetization of the second ferromagnetic metal layer is oriented in the stacking direction of the magnetoresistance effect element; and the second ferromagnetic metal layer has shape anisotropy, such that a length along the first direction is greater than a length along a second direction orthogonal to the first direction and to the stacking direction.

Abstract: An object of the present technology is to improve the performance of a memory cell that stores the value reflecting the direction of an electric current. The memory cell includes an N-type transistor, a P-type transistor, and a storage element. The N-type transistor supplies a current either from a source to a drain thereof or from the drain to the source. The P-type transistor supplies a current from a source to a drain thereof. The storage element stores a logical value reflecting the direction of the current supplied from the drain of the N-type transistor and from the drain of the P-type transistor.

Abstract: A method, computer program product, and circuit are provided for noise and bound management for a Resistive Processing Unit (RPU) array having an op-amp. The method includes reducing the noise in an output signal from the RPU array by using a largest value, in a sigma vector having a plurality of values, as a representation for a window for an input signal to the RPU array. The input signal to the RPU array is formed from the plurality of values. The method further includes sensing saturation at an output of the op-amp. The method also includes managing the bound to eliminate the saturation by reducing the plurality of values from which the input signal to the RPU is formed.

Abstract: A method for rewriting a semiconductor storage device includes: a first rewriting step of applying a pre-charge voltage to both of a plurality of bit lines and a plurality of source lines; a second rewriting step of applying a rewrite voltage to one of a selected bit line or a selected source line; a third rewriting step of applying a rewrite voltage to both of the selected bit line and the selected source line; a fourth rewriting step of applying a pre-charge voltage to one of the selected bit line or the selected source line; and a fifth rewriting step of applying a pre-charge voltage to both of the selected bit line and the selected source line.

Abstract: A method of manufacturing a magnetic-field sensor includes forming an insulating layer on a first surface of a substrate. First and second magnetoresistors are formed at different above the first surface of the substrate and are spaced apart from the first surface by different distances. The first and second magnetoresistors have respective main axes of magnetization transverse to one another, and respective secondary axes of magnetization transverse to one another. The method further includes forming a first magnetic-field generator configured to generate a first magnetic field having field lines along the main axis of magnetization of the first magnetoresistor, and forming a second magnetic-field generator configured to generate a second magnetic field having field lines along the main axis of magnetization of the second magnetoresistor.

Abstract: Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element that includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direction. The free layer includes a first region, a second region and a third region. The third region is formed from a third material that is configured to magnetically couple the first region and the second region. The first region is formed from a first material having a first predetermined magnetic moment, and the second region is formed from a second material having a second predetermined magnetic moment. The first predetermined magnetic moment is lower that the second predetermined magnetic moment.

Abstract: A method, computer program product, and circuit are provided for noise and bound management for a Resistive Processing Unit (RN) array having an op-amp. The method includes reducing the noise in an output signal from the RPU array by using a largest value, in a sigma vector having a plurality of values, as a representation for a window for an input signal to the RPU array. The input signal to the RPU array is formed from the plurality of values. The method further includes sensing saturation at an output of the op-amp. The method also includes managing the bound to eliminate the saturation by reducing the plurality of values from which the input sign to the RPU is formed.

Abstract: A method includes performing an ion beam etching process on a tunnel magnetoresistance (TMR) stack to remove material portions of a first magnetic layer and a tunnel barrier layer of the TMR stack. The ion beam etching process stops at a top surface of a second magnetic layer of the TMR stack. A protective layer is deposited over the TMR stack. Another etch process is performed to remove the protective layer such that a portion of the second magnetic layer is exposed from the protective layer and a spacer is formed from a remaining portion of the protective layer. The spacer surrounds sidewalls of the first magnetic layer and the tunnel barrier layer. The portion of the second magnetic layer exposed from the protective layer is removed so that a TMR sensor element remains, where the TMR sensor element includes a bottom magnet, a top magnet, and a tunnel junction.

Abstract: An integrated magnetoresistive device includes a substrate of semiconductor material that is covered, on a first surface, by an insulating layer. A magnetoresistor of ferromagnetic material extends within the insulating layer and defines a sensitivity plane of the sensor. A concentrator of ferromagnetic material includes at least one arm that extends in a transversal direction to the sensitivity plane and is vertically offset from the magnetoresistor. The concentrator concentrates deflects magnetic flux lines perpendicular to the sensitivity plane so as to generate magnetic-field components directed in a parallel direction to the sensitivity plane.

Abstract: A magnetic memory device and a method to make the device is disclosed. The magnetic memory device comprises a free magnetic layer that includes a hard magnetic material layer, a soft magnetic material layer and a coupling layer that is between the hard magnetic material layer and the soft magnetic material layer. The coupling layer comprises a magnetic material that has oxidized edges. In one embodiment, the magnetic material of the coupling layer comprises a Heusler alloy or a silicon-based magnetic material. A predetermined amount of the coupling layer is oxidized to controllably reduce the switching current Jc0 of the free magnetic layer to be about half of the switching current if the coupling layer comprised substantially all magnetic material and no oxide.

Abstract: A magnetic memory device may include tunnel junction unit cells, each including a pinned magnetic layer, an insulating layer, and a free magnetic layer which are sequentially stacked, a conductive line structure configured to supply an in-plane current to the unit cells and to include an antiferromagnetic layer, which is provided adjacent to the free magnetic layer, and a ferromagnetic layer, which is provided adjacent to the antiferromagnetic layer and has an in-plane magnetic anisotropy, and a voltage applying unit configured to independently apply a selection voltage to each of the tunnel junction unit cells. Each of the tunnel junction unit cells may have a magnetization direction that is selectively changed by the in-plane current and the selection voltage.

Abstract: A magnetic memory device is provided. The magnetic memory device includes a memory circuit comprising a first tunnel magnetoresistive element and a second tunnel magnetoresistive element coupled in series. An input node of the magnetic memory device is coupled to the first tunnel magnetoresistive element, wherein the input node is configured to receive a voltage signal. The first tunnel magnetoresistive element initially holds a first resistance value, wherein the first tunnel magnetoresistive element is short-circuited to hold a second resistance value after the voltage signal is received by the input node. End nodes of the memory circuit are coupled to defined voltages in a read mode. The magnetic memory device further includes a read-out circuit configured to measure a voltage at a sensing node in the read mode. The sensing node is interconnected between the first tunnel magnetoresistive element and the second tunnel magnetoresistive element.

Abstract: A high-density magnetic memory device includes: a heavy metal strip or an antiferromagnet strip with a thickness of 0-20 nm, and a plurality of magnetic tunnel junctions manufactured thereon, wherein each of the magnetic tunnel junctions represents a memory bit, which from bottom to top comprises a first ferromagnetic metal with a thickness of 0-3 nm, an oxide with a thickness of 0-2 nm, a second ferromagnetic metal with a thickness of 0-3 nm, a synthetic antiferromagnetic layer with a thickness of 10-20 nm and a No. X top electrode with a thickness of 10-200 nm, wherein an X value is a serial number of the memory bit; two ends of the heavy metal strip or the antiferromagnet strip are respectively plated with a first bottom electrode and a second bottom electrode. The write operation for the memory device of the present invention is accomplished by applying unidirectional write currents.

Abstract: According to an embodiment, a magnetic storage device includes a first, second, and third magnetoresistive effect elements, and a controller. The second and third magnetoresistive effect elements are in proximity to the first magnetoresistive effect element. When the controller receives an command which is associated with an operation of writing a first data item to the first magnetoresistive effect element, the controller is configured to perform a first operation of writing the first data item to the first magnetoresistive effect element, and a second operation of writing a second data item different from the first data item to the second magnetoresistive effect element and the third magnetoresistive effect element.

Abstract: A resistive random-access memory structure and a method for fabricating a resistive random-access memory structure are described. A first dielectric layer is formed on a substrate. A plurality of bottom electrodes are independently embedded in the first dielectric layer. A transition metal oxide layer covers the plurality of bottom electrodes and extends onto a portion of the first dielectric layer. The minimum distance between the bottom electrode and a sidewall of the transition metal oxide layer is a first distance. The first distance is in a range of 10 nm to 200 ?m. A top electrode is formed on the transition metal oxide layer.

Abstract: The disclosed technology generally relates to magnetic devices, and more particularly to spin torque devices. In one aspect, a spin torque majority gate device includes a free ferromagnetic layer, a spin mixing layer formed above the free ferromagnetic layer, a non-magnetic tunnelling layer formed above the spin mixing layer, and a plurality of input elements formed above the non-magnetic tunnelling layer, where each input element has a fixed ferromagnetic layer.

Abstract: A magnetic field sensor comprises a sensor bridge having multiple sensor legs. Each sensor leg includes magnetoresistive sense elements located in a plane of the magnetic field sensor. Each sense element comprises a pinned layer and a sense layer. The pinned layer has a reference magnetization oriented parallel to the plane and the sense layer has a sense magnetization oriented out-of-plane. A permanent magnet layer may be spaced apart from the sense elements which magnetically biases the sense magnetization of the sense layer into an out-of-plane direction that is non-perpendicular to the plane of the sensor. The sense magnetization is orientable from the out-of-plane direction toward the plane of the sensor in response to an external magnetic field. The permanent magnet layer enables detection of the external magnetic field in a sensing direction that is also perpendicular to the plane of the magnetic field sensor.

Abstract: A bitcell for storing a charge state, the bitcell including a spin hall metal for passing through a charge current, a magneto tunnel junction (MTJ) stack for generating and storing a non-volatile spin state corresponding to a binary bit in response to passage of the charge current through the spin hall metal, and for inducing the charge current corresponding to the non-volatile spin state in response to application of a read voltage, first and second write bitlines for sourcing the charge current through the spin hall metal in response to a write voltage being applied to both of the first and second write bitlines, and a read bitline for inducing the charge current through the spin hall metal in response to the read voltage being applied to the read bitline, and a first wordline and a second wordline for permitting a flow of the charge current through spin hall metal.

Abstract: A magnetoresistive memory cell includes a magnetoresistive tunnel junction stack and a dielectric encapsulation layer covering sidewall portions of the stack and being opened over a top of the stack. A conductor is formed in contact with a top portion of the stack and covering the encapsulation layer. A magnetic liner encapsulates the conductor and is gapped apart from the encapsulating layer covering the sidewall portions of the stack.

Abstract: A spin transistor memory according to an embodiment includes: a first semiconductor region, a second semiconductor region, and a third semiconductor region, each being of a first conductivity type and disposed in a semiconductor layer; a first gate disposed above the semiconductor layer between the first semiconductor region and the second semiconductor region; a second gate disposed above the semiconductor layer between the second semiconductor region and the third semiconductor region; and a first ferromagnetic layer, a second ferromagnetic layer, and a third ferromagnetic layer disposed on the first semiconductor region, the second semiconductor region, and the third semiconductor region respectively.