Abstract: A current sensor packaged in an integrated circuit package to include a magnetic field sensing circuit, a current conductor and an insulator that meets the safety isolation requirements for reinforced insulation under the UL 60950-1 Standard is presented. The insulator is provided as an insulation structure having at least two layers of thin sheet material. The insulation structure is dimensioned so that plastic material forming a molded plastic body of the package provides a reinforced insulation. According to one embodiment, the insulation structure has two layers of insulating tape. Each insulating tape layer includes a polyimide film and adhesive. The insulation structure and the molded plastic body can be constructed to achieve at least a 500 VRMS working voltage rating.

Abstract: An integrated circuit includes a magnetic field sensor and an injection molded magnetic material enclosing at least a portion of the magnetic field sensor.

Abstract: A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a first pinned layer having a first pinned layer magnetization, a first nonmagnetic spacer layer, and a free layer having an easy axis. The first nonmagnetic spacer layer is between the first pinned layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction and such that the free layer employs precessional switching.

Abstract: A method of bonding a semiconductor substrate having a substrate 11 formed with a MEMS sensor and a substrate 21 having a bonding portion 30b film-formed by contacting an aluminum containing layer 31 with a germanium layer 32 on either a front surface or a rear surface and formed with an integrated circuit that controls the MEMS sensor, either a front surface or a rear surface of the substrate 11 is put to contact directly on the bonding portion of the substrate 21 to bond by eutectic bonding with pressurization and heating.

Abstract: A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni.

Abstract: An integrated passive component having a semiconductor body, arranged on a metal substrate and having a first surface, and a plurality of metal surfaces formed on the surface, and an integrated circuit formed on the surface of the semiconductor body, whereby the integrated circuit is connected by traces to the metal surfaces, and having a dielectric passivation layer formed on the surface, and the metal surfaces are connected to pins by bonding wires, and a first coil former, formed above the dielectric layer, with a winding, whereby the winding has a first connector and a second connector, and whereby the winding is formed as a wire or litz wire and the first connector of the winding is connected to a first metal surface and the second connector to a second metal surface.

Abstract: A magnetoresistive element according to an embodiment includes: a first to third ferromagnetic layers, and a first nonmagnetic layer, the first and second ferromagnetic layers each having an axis of easy magnetization in a direction perpendicular to a film plane, the third ferromagnetic layer including a plurality of ferromagnetic oscillators generating rotating magnetic fields of different oscillation frequencies from one another. Spin-polarized electrons are injected into the first ferromagnetic layer and induce precession movements in the plurality of ferromagnetic oscillators of the third ferromagnetic layer by flowing a current between the first and third ferromagnetic layers, the rotating magnetic fields are generated by the precession movements and are applied to the first ferromagnetic layer, and at least one of the rotating magnetic fields assists a magnetization switching in the first ferromagnetic layer.

Abstract: A semiconductor device and associated methods, the semiconductor device including a semiconductor layer including a first region and a second region, a first contact plug disposed on the semiconductor layer and electrically connected to the first region, a second contact plug disposed on the semiconductor layer and electrically connected to the second region, a conductive layer electrically connected to the first contact plug, the conductive layer having a side surface and a bottom surface, and an insulating layer disposed between the conductive layer and the second contact plug so as to insulate the conductive layer from the second contact plug, the insulating layer facing the side surface and a portion of the bottom surface of the conductive layer.

Abstract: A semiconductor device includes: a spin torque written in-plane magnetization magnetoresistive element, placed over the main surface of a semiconductor substrate, whose magnetization state can be changed according to the direction of a current flow; and a first wiring electrically coupled with the magnetoresistive element and extended toward the direction along the main surface. The aspect ratio of the magnetoresistive element as viewed in a plane is a value other than 1. In a memory cell area where multiple memory cells in which the magnetoresistive element and a switching element are electrically coupled with each other are arranged, the following measure is taken: multiple magnetoresistive elements adjoining to each other in the direction of length of each magnetoresistive element as viewed in a plane are so arranged that they are not on an identical straight line extended in the direction of length.

Abstract: An aspect of the present embodiment, there is provided magnetic random access memory device including a semiconductor substrate, a selection transistor on the semiconductor substrate, the selection transistor including a diffusion layer, a contact plug on diffusion layer, an amorphous film on the contact plug, a lower electrode provided on the amorphous film, a first magnetic layer, a nonmagnetic layer, a second magnetic layer, an upper electrode stacked in an order and a sidewall contact film on the contact plug, the sidewall contact film being in contact with a sidewall of the upper electrode.

Abstract: The semiconductor device includes a memory cell including a plurality of magnetoresistive elements disposed therein, and a peripheral circuit region disposed around the memory cell region. The magnetoresistive element includes a magnetization fixed layer, a magnetization free layer, and a tunneling insulation layer. The semiconductor device includes, above the magnetoresistive elements, a plurality of first wires extending in the direction along the main surface. In the peripheral circuit region, there is disposed a multilayer structure of lamination of a layer equal in material to the magnetization free layer, a layer equal in material to the tunneling insulation layer, and a layer equal in material to the magnetization fixed layer so as to overlap a second wire formed of the same layer as the first wire in plan view. The multilayer structure does not overlap both of a pair of adjacent second wires in plan view in the peripheral circuit region.

Abstract: A semiconductor device with an integrated circuit on a semiconductor substrate comprises a Hall effect sensor in a first active region and a lateral high voltage MOS transistor in a second active region. The semiconductor device of the present invention is characterized in that the structure of the integrated Hall effect sensor is strongly related with the structure of a high-voltage DMOS transistor. The integrated Hall effect sensor is in some features similar to a per se known high-voltage DMOS transistor having a double RESURF structure. The control contacts of the Hall effect sensor correspond to the source and drain contacts of the high-voltage DMOS transistor. The semiconductor device of the present invention allows a simplification of the process integration.

Abstract: A mounting structure for mounting a chip type electric element on a flexible board includes: the flexible board having a first land, on which a first lead terminal of another electric element is soldered; and the chip type electric element having a long side. A whole of the long side of the chip type electric element faces a long side of the first land. A length of the long side of the first land is defined as IA, and a distance between one long side of the first land and one long side of the chip type electric element is defined as IB, the one long side of the first land facing the chip type electric element but opposite to the one long side of the chip type electric element. The length of IA is equal to or larger than the distance of IB.

Abstract: A FinFET (100) comprises a fin-shaped layer-section (116) of a single-crystalline active semiconductor layer (104) extending on an insulating substrate layer (106) along a longitudinal fin direction between, a source layer-section (122), and a drain layer-section (124) of the single-crystalline active semiconductor layer (104). Furthermore, two separate gate-electrode layers (138.1, 138.2) are provided, which do not form sections of the single-crystalline active semiconductor layer, each of the gate-electrode layers facing one of the opposite side faces of the fin-shaped layer-section (116). Each gate-electrode layer is connected with a respective separate gate contact (154, 156).

Abstract: A method of manufacturing a magnetoresistive effect element includes forming a first electrode above a substrate, forming a metal layer of a metal material above the first electrode, forming a first magnetic layer above the metal layer, forming a tunnel insulating film above the first magnetic layer, forming a second magnetic layer above the tunnel insulating film, forming a second electrode layer above the second magnetic layer, patterning the second electrode layer, patterning the second magnetic layer, the tunnel insulating film, the first magnetic layer and the metal layer, while depositing sputtered particles of the metal film on side walls of the second magnetic layer, the tunnel insulating film, the first magnetic layer and the metal layer to form a sidewall metal layer, and oxidizing the sidewall metal layer to form an insulative sidewall metal oxide layer.

Abstract: Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.

Abstract: In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate. First trenches are formed within the substrate adjacent the first inductor coil. The first trenches are filled at least partially with a magnetic fill material. At least a first portion of the substrate underlying the first inductor coil is thinned. A backside magnetic layer is formed under the first portion of the substrate. The backside magnetic layer and the magnetic fill material form at least a part of a magnetic core region of the first inductor coil.

Abstract: A magnetic memory according to an embodiment includes: at least one memory cell comprising a magnetoresistive element as a memory element, and first and second electrodes that energize the magnetoresistive element. The magnetoresistive element includes: a first magnetic layer having a variable magnetization direction perpendicular to a film plane; a tunnel barrier layer on the first magnetic layer; and a second magnetic layer on the tunnel barrier layer, and having a fixed magnetization direction perpendicular to the film plane. The first magnetic layer including: a first region; and a second region outside the first region so as to surround the first region, and having a smaller perpendicular magnetic anisotropy energy than that of the first region. The second magnetic layer including: a third region; and a fourth region outside the third region, and having a smaller perpendicular magnetic anisotropy energy than that of the third region.

Abstract: Provided is a memory device employing magnetic domain wall movement. The memory device includes a writing track and a column structure. The writing track forms magnetic domains that have predetermined magnetization directions. The column structure is formed on the writing track and includes at least one interconnecting layer and at least one storage track.

Abstract: The invention relates to a magnetic sensor and a magnetic memory which sense magnetic information held by a ferromagnetic body without a current flowing through the ferromagnetic body. The magnetic sensor and magnetic memory use a magnetoresistive effect generated in a current that flows through a metal layer along an interface, on at least the interface side, with a ferromagnetic dielectric layer and said metal layer being joined through said interface.

Abstract: A magnetic memory element includes: a first magnetization free layer formed of a ferromagnetic material having perpendicular magnetic anisotropy; a second magnetization free layer provided near the first magnetization free layer and formed of a ferromagnetic material having in-plane magnetic anisotropy; a reference layer formed of a ferromagnetic material having in-plane magnetic anisotropy; and a non-magnetic layer provided between the second magnetization free layer and the reference layer. The first magnetization free layer includes: a first magnetization fixed region of which magnetization is fixed, a second magnetization fixed region of which magnetization is fixed, and a magnetization free region which is connected to the first magnetization fixed region and the second magnetization fixed region, and of which magnetization can be switched. The second magnetization free layer is included in the first magnetization free layer in a plane parallel to a substrate.

Abstract: A magnetoresistive effect element includes: a magnetization free layer; a non-magnetic insertion layer provided adjacent to the magnetization free layer; a magnetic insertion layer provided adjacent to the non-magnetic insertion layer and opposite to the magnetization free layer with respect to the non-magnetic insertion layer; a spacer layer provided adjacent to the magnetic insertion layer and opposite to the non-magnetic insertion layer with respect to the magnetic insertion layer; and a first magnetization fixed layer provided adjacent to the spacer layer and opposite to the magnetic insertion layer with respect to the spacer layer. The magnetization free layer and the first magnetization fixed layer have magnetization components in directions approximately perpendicular to a film surface. The magnetization free layer includes two magnetization fixed portions and a domain wall motion portion arranged between the two magnetization fixed portions.

Abstract: A magnetic memory device is provided. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and the pinned pattern is interposed between the invariable pinning pattern and the tunnel barrier pattern. A storage free pattern is interposed between the tunnel barrier pattern and the variable pinning pattern, and a guide free pattern is interposed between the storage free pattern and the variable pinning pattern. A free reversing pattern is interposed between the storage and guide free patterns. The free reversing pattern reverses a magnetization direction of the storage free pattern and a magnetization direction of the guide free pattern in the opposite directions.

Abstract: A semiconductor device with an integrated circuit on a semiconductor substrate comprises a Hall effect sensor in a first active region and a lateral high voltage MOS transistor in a second active region. The semiconductor device of the present invention is characterized in that the structure of the integrated Hall effect sensor is strongly related with the structure of a high-voltage DMOS transistor. The integrated Hall effect sensor is in some features similar to a per se known high-voltage DMOS transistor having a double RESURF structure. The control contacts of the Hall effect sensor correspond to the source and drain contacts of the high-voltage DMOS transistor. The semiconductor device of the present invention allows a simplification of the process integration.

Abstract: A multi-level lithography processes for the fabrication of suspended structures are presented. The process is based on the differential exposure and developing conditions of several a plurality of resist layers, without harsher processes, such as etching of sacrificial layers or the use of hardmasks. These manufacturing processes are readily suited for use with systems that are chemically and/or mechanically sensitive, such as graphene. Graphene p-n-p junctions with suspended top gates formed through these processes exhibit high mobility and control of local doping density and type. This fabrication technique may be further extended to fabricate other types of suspended structures, such as local current carrying wires for inducing local magnetic fields, a point contact for local injection of current, and moving parts in microelectromechanical devices.

Abstract: A nonvolatile memory device including a lower electrode, a resistor structure disposed on the lower electrode, a middle electrode disposed on the resistor structure, a diode structure disposed on the middle electrode, and an upper electrode disposed on the diode structure. A nonvolatile memory device wherein the resistor structure includes one resistor and the diode structure includes one diode. An array of nonvolatile memory device as described above. Methods of manufacturing a nonvolatile memory device and an array of nonvolatile memory device.

Abstract: Provided are a multi-purpose magnetic film structure using a spin charge, a method of manufacturing the same, a semiconductor device having the same, and a method of operating the semiconductor memory device. The multi-purpose magnetic film structure includes a lower magnetic film, a tunneling film formed on the lower magnetic film, and an upper magnetic film formed on the tunneling film, wherein the lower and upper magnetic films are ferromagnetic films forming an electrochemical potential difference therebetween when the lower and upper magnetic films have opposite magnetization directions.

Abstract: A Hall effect element includes a Hall plate with an outer perimeter. The outer perimeter includes four corner regions, each tangential to two sides of a square outer boundary associated with the Hall plate, and each extending along two sides of the square outer boundary by a corner extent. The outer perimeter also includes four indented regions. Each one of the four indented regions deviates inward toward a center of the Hall plate. The Hall plate further includes a square core region centered with and smaller than the square outer boundary. A portion of each one of the four indented regions is tangential to a respective side of the square core region. Each side of the square core region has a length greater than twice the corner extent and less than a length of each side of the square outer boundary.

Abstract: Stress sensors and stress sensor integrated circuits using one or more nanowire field effect transistors as stress-sensitive elements, as well as design structures for a stress sensor integrated circuit embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and related methods thereof. The stress sensors and stress sensor integrated circuits include one or more pairs of gate-all-around field effect transistors, which include one or more nanowires as a channel region. The nanowires of each of the field effect transistors are configured to change in length in response to a mechanical stress transferred from an object. A voltage output difference from the field effect transistors indicates the magnitude of the transferred mechanical stress.

Abstract: Magnetic tunnel junctions having a specular insulative spacer are disclosed. The magnetic tunnel junction includes a free magnetic layer, a reference magnetic layer, an electrically insulating and non-magnetic tunneling barrier layer separating the free magnetic layer from the reference magnetic layer, and an electrically insulating and electronically reflective layer positioned to reflect at least a portion of electrons back into the free magnetic layer.

Abstract: A Spin-Dependent Tunnelling cell comprises a first barrier layer of a first material and a second barrier layer of a second material sandwiched between a first ferromagnetic layer and a second ferromagnetic layer. The first and second barrier layers are formed to a combined thicknesses so that a Tunnelling Magnetoresistance versus voltage characteristic of the cell has a maximum at a non-zero bias voltage.

Abstract: A magnetic memory device including a Magnetic Tunnel Junction (MTJ) device comprises a substrate and Front End of Line (FEOL) circuitry. A Via level (VA) InterLayer Dielectric (ILD) layer, a bottom conductor layer, and an MTJ device formed over the top surface of the VA ILD layer are formed over a portion of the substrate. An alignment region including alignment marks extends through the bottom conductor layer and extends down into the device below the top surface of the VA ILD layers is juxtaposed with the MJT device.

Abstract: A method and system for providing a magnetic element that can be used in a magnetic memory is disclosed. The magnetic element includes pinned, nonmagnetic spacer, and free layers. The spacer layer resides between the pinned and free layers. The free layer can be switched using spin transfer when a write current is passed through the magnetic element. The free layer includes a first ferromagnetic layer and a second ferromagnetic layer. The second ferromagnetic layer has a very high perpendicular anisotropy and an out-of-plane demagnetization energy. The very high perpendicular anisotropy energy is greater than the out-of-plane demagnetization energy of the second layer.

Abstract: A spin-tunnel transistor having a tunnel barrier layer formed of an antiferromagnetic material which is exchange coupled with a first or second ferromagnetic metal layer of a base B formed adjoining to the antiferromagnetic material, so as to fix magnetization of the adjoining ferromagnetic layer. The base B includes a nonmagnetic metal layer which is formed between the first and second ferromagnetic metal layers and decouple magnetization coupling between the first and second ferromagnetic metal layers. The base B is formed between a collector and an emitter to form tri-terminal device. Those spin-tunnel transistor may be used as a sensor of a magnetic reproducing head used in a hard disk drive.

Abstract: Provided are a multi-purpose magnetic film structure using a spin charge, a method of manufacturing the same, a semiconductor device having the same, and a method of operating the semiconductor memory device. The multi-purpose magnetic film structure includes a lower magnetic film, a tunneling film formed on the lower magnetic film, and an upper magnetic film formed on the tunneling film, wherein the lower and upper magnetic films are ferromagnetic films forming an electrochemical potential difference therebetween when the lower and upper magnetic films have opposite magnetization directions.

Abstract: This invention provides a magnetic shielding package structure of a magnetic memory device, in which at least a magnetic memory device is embedded between a magnetic shielding substrate and a magnetic shielding layer. A plurality of through vias is formed in the magnetic shielding substrate or the magnetic shielding layer, and a plurality of conductive contacts passes through the through vias such that electrical connection between the magnetic memory device and the external is established.

Abstract: A technique includes forming overlaying magnetic metal layers over a semiconductor substrate. The technique includes forming at least one resistance layer between the magnetic metal layers.

Abstract: A magnetic signal transmission line includes a one-dimensional array of a plurality of single-magnetization domains each formed in a ferromagnetic body. The anisotropic energy of the single-magnetization domains is zero to 120% of the interactive energy acting between dipoles in adjacent single-magnetization domains. The single-magnetization domains are formed by sputtering iron onto a silicon substrate by using a mask.

Abstract: A spin transistor includes a non-magnetic semiconductor substrate having a channel region, a first area, and a second area. The channel region is between the first and the second areas. The spin transistor also includes a first conductive layer located above the first area and made of a ferromagnetic material magnetized in a first direction; and a second conductive layer located above the second area and made of a ferromagnetic material magnetized in one of the first direction and a second direction that is antiparallel with respect to the first direction. The channel region introduces electron spin between the conductive layers. The spin transistor also includes a gate electrode located between the conductive layers and above the channel region; and a tunnel barrier film located between the non-magnetic semiconductor substrate and at least one of the conductive layers.

Abstract: In one embodiment, the present invention includes a hybrid device having a first die including a semiconductor device and a second die coupled to the first die, where the second die includes a magnetic structure. The first die may be a semiconductor substrate, while the second die may be a magnetic substrate, and the first die may be stacked on the second die, in one embodiment. Other embodiments are described and claimed.

Abstract: A method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of memory cells includes: forming a fixed magnetic layer having magnetic moments fixed in a predetermined direction; forming a tunnel layer over the fixed magnetic layer; forming a free magnetic layer, having magnetic moments aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer; forming a hard mask on the free magnetic layer partially covering the free magnetic layer; and unmagnetizing portions of the free magnetic layer uncovered by the hard mask for defining one or more magnetic tunnel junction (MTJ) units.

Abstract: The present invention is directed to the use of perovskite manganite thin films and other magnetic films that exhibit both planar Hall effect and biaxial magnetic anisotropy to form the active area in magnetic sensor devices and in magnetic bit cells used in magnetoresistive random access memory (MRAM) devices. The manganite thin films of the invention are ferromagnetic manganites of the formula R1-xAxMnO3, wherein R is a rare-earth metal, A is an alkaline earth metal, and x is generally between about 0.15 and about 0.5.

Abstract: An electric field read/write head, a method of manufacturing the same, and a data read/write device including the electric field read/write head are provided. The data read/write device includes an electric field read/write head which reads and writes data to and from a recording medium. The electric field read/write head includes a semiconductor substrate, a resistance region, source and drain regions, and a write electrode. The semiconductor substrate includes a first surface and a second surface with adjoining edges. The resistance region is formed to extend from a central portion at one end of the first surface to the second surface. The source region and the drain region are formed at either side of the resistance region and are separated from the first surface. The write electrode is formed on the resistance region with an insulating layer interposed between the write electrode and the resistance region.

Abstract: An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structures levels and elongated interconnects.

Abstract: A spin transfer torque magnetic random access memory (STT-MRAM) device comprises adjacent magnetic tunneling junctions (MTJ), respectively, formed in different layers, thereby preventing interference between the MTJs and securing thermal stability.

Abstract: Methods and apparatus for providing an integrated circuit including a substrate having a magnetic field sensor, first and second conductive layers generally parallel to the substrate, and a dielectric layer disposed between the first and second conductive layers such that the first and second conductive layers and the dielectric layer form a capacitor, wherein a slot is formed in at least one of the first and second conductive layers proximate the magnetic field sensor for reducing eddy currents in the first and second conductive layers.

Abstract: A driving circuit includes a power supply, an input capacitor, a Hall sensor, a first amplifier, a second amplifier, a full-bridge driver circuit, and a first operational amplifier. The input capacitor is coupled to the power supply. The input end of the first amplifier and the second amplifier is coupled to the output end of the Hall sensor. The control end of the full-bridge driver circuit is coupled to the output end of the first amplifier and the output end of the second amplifier. The first operational amplifier includes a first input end for receiving a first reference voltage and a second input end coupled to the first output end of the full-bridge driver circuit.

Abstract: Disclosed are a thin film transistor and a method for fabricating the same. The thin film transistor is capable of a fine current control. The thin film transistor includes a semiconductor layer comprising a channel; a gate electrode overlying the semiconductor layer; a source electrode connected to a first end of the semiconductor layer; a drain electrode connected to a second end of the semiconductor layer; and a conductive line connected to one of the source and drain electrodes. The conductive line is configured to generate a magnetic field penetrating through at least a portion of the semiconductor layer when an electrical current flows through the conductive line.

Abstract: An integrated circuit current sensor includes a lead frame having at least two leads coupled to provide a current conductor portion, and a substrate having a first surface in which is disposed one or more magnetic field sensing elements, with the first surface being proximate to the current conductor portion and a second surface distal from the current conductor position. In one particular embodiment, the substrate is disposed having the first surface of the substrate above the current conductor portion and the second surface of the substrate above the first surface. In this particular embodiment, the substrate is oriented upside-down in the integrated circuit in a flip-chap arrangement. The current sensor can also include an electromagnetic shield disposed between the current conductor portion and the magnetic field sensing elements.

Abstract: A quantum computer can only function stably if it can execute gates with extreme accuracy. “Topological protection” is a road to such accuracies. Quasi-particle interferometry is a tool for constructing topologically protected gates. Assuming the corrections of the Moore-Read Model for ?=5/2's FQHE (Nucl. Phys. B 360, 362 (1991)) we show how to manipulate the collective state of two e/4-charge anti-dots in order to switch said collective state from one carrying trivial SU(2) charge, |1>, to one carrying a fermionic SU(2) charge |?>. This is a NOT gate on the {|1>, |?>} qubit and is effected by braiding of an electrically charged quasi particle ? which carries an additional SU(2)-charge. Read-out is accomplished by ?-particle interferometry.